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Conv TTL Blocking - Gateware
Commit 1fa8d796 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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multiboot works

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doc/multiboot/fig/multiboot-bd.png
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doc/multiboot/fig/multiboot-bd.svg
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......@@ -234,7 +234,7 @@
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......
hdl/multiboot/rtl/multiboot_fsm.vhd
View file @ 1fa8d796
......@@ -15,7 +15,7 @@
-- three sequences:
-- - SPI -- shift out up to three bytes (based on the NBYTES)
-- value in FAR
-- - BOOTSTS -- read a configuration register from the Xilinx FPGA
-- - RDCFGREG -- read a configuration register from the Xilinx FPGA
-- configuration logic
-- - IPROG -- issue an IPROG command to the Xilinx FPGA configuration
-- logic
......@@ -56,7 +56,8 @@ entity multiboot_fsm is
rst_n_i : in std_logic;
-- Control register inputs
reg_rdbootsts_i : in std_logic;
reg_rdcfgreg_i : in std_logic;
reg_cfgregadr_i : in std_logic_vector(5 downto 0);
reg_iprog_i : in std_logic;
-- Multiboot and golden bitstream start addresses
......@@ -64,8 +65,8 @@ entity multiboot_fsm is
reg_mbbar_i : in std_logic_vector(31 downto 0);
-- Outputs to status register
reg_bootsts_img_o : out std_logic_vector(15 downto 0);
reg_bootsts_valid_o : out std_logic;
reg_cfgreg_img_o : out std_logic_vector(15 downto 0);
reg_cfgreg_valid_o : out std_logic;
-- Flash access register signals
reg_far_data_i : in std_logic_vector(23 downto 0);
......@@ -121,22 +122,22 @@ architecture behav of multiboot_fsm is
GBA_H,
IPROG_CMD,
IPROG,
-- BOOTSTS read states
BOOTSTS_CMD,
BOOTSTS_NOOP_1,
BOOTSTS_NOOP_2,
BOOTSTS_NOOP_3,
BOOTSTS_NOOP_4,
BOOTSTS_SETRD_1,
BOOTSTS_SETRD_2,
BOOTSTS_SETRD_3,
BOOTSTS,
BOOTSTS_SETWR_1,
BOOTSTS_SETWR_2,
BOOTSTS_SETWR_3,
-- RDCFGREG read states
RDCFGREG_CMD,
RDCFGREG_NOOP_1,
RDCFGREG_NOOP_2,
RDCFGREG_NOOP_3,
RDCFGREG_NOOP_4,
RDCFGREG_SETRD_1,
RDCFGREG_SETRD_2,
RDCFGREG_SETRD_3,
RDCFGREG,
RDCFGREG_SETWR_1,
RDCFGREG_SETWR_2,
RDCFGREG_SETWR_3,
DESYNC_CMD,
DESYNC,
-- NOOPs after BOOTSTS and IPROG sequences
-- NOOPs after RDCFGREG and IPROG sequences
FINAL_NOOP_1,
FINAL_NOOP_2,
PREPARE_IDLE
......@@ -170,7 +171,7 @@ begin
-- Form state machine command vector from inputs
fsm_cmd <= reg_far_xfer_i &
reg_iprog_i &
reg_rdbootsts_i;
reg_rdcfgreg_i;
-- Assign SPI outputs
spi_cs_o <= reg_far_cs_i;
......@@ -182,18 +183,18 @@ begin
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
state <= IDLE;
fsm_cmd_reg <= (others => '0');
icap_dat_o <= (others => '0');
icap_ce_n_o <= '1';
icap_wr_n_o <= '1';
reg_bootsts_img_o <= (others => '0');
reg_bootsts_valid_o <= '0';
reg_far_ready_o <= '1';
reg_far_data_o <= (others => '0');
spi_data_int <= (others => '0');
spi_cnt <= "00";
spi_xfer_o <= '0';
state <= IDLE;
fsm_cmd_reg <= (others => '0');
icap_dat_o <= (others => '0');
icap_ce_n_o <= '1';
icap_wr_n_o <= '1';
reg_cfgreg_img_o <= (others => '0');
reg_cfgreg_valid_o <= '0';
reg_far_ready_o <= '1';
reg_far_data_o <= (others => '0');
spi_data_int <= (others => '0');
spi_cnt <= "00";
spi_xfer_o <= '0';
else
......@@ -278,7 +279,7 @@ begin
state <= SYNC_NOOP;
-- and the NOOP after the sync words, after which we go to IPROG or
-- BOOTSTS read, depending on what command we got at the beginning
-- RDCFGREG read, depending on what command we got at the beginning
when SYNC_NOOP =>
icap_dat_o <= x"2000";
icap_ce_n_o <= '0';
......@@ -287,7 +288,7 @@ begin
when "010" =>
state <= GEN_1;
when "001" =>
state <= BOOTSTS_CMD;
state <= RDCFGREG_CMD;
when others =>
state <= IDLE;
end case;
......@@ -357,83 +358,83 @@ begin
state <= FINAL_NOOP_1;
--====================================================================
-- BOOTSTS read sequence
-- RDCFGREG read sequence
-- as per Table 6-1, p.113 [1], starting from step 6
--====================================================================
-- write type1 packet header to read BOOTSTS register
-- write type1 packet header to read RDCFGREG register
-- (packet headers can be found on page 93 of [1])
when BOOTSTS_CMD =>
when RDCFGREG_CMD =>
icap_ce_n_o <= '0';
icap_wr_n_o <= '0';
icap_dat_o <= x"2c01";
state <= BOOTSTS_NOOP_1;
icap_dat_o <= "001" & "01" & reg_cfgregadr_i & "00001"; --x"2c01";
state <= RDCFGREG_NOOP_1;
-- then four noops
when BOOTSTS_NOOP_1 =>
when RDCFGREG_NOOP_1 =>
icap_dat_o <= x"2000";
icap_ce_n_o <= '0';
icap_wr_n_o <= '0';
state <= BOOTSTS_NOOP_2;
state <= RDCFGREG_NOOP_2;
when BOOTSTS_NOOP_2 =>
when RDCFGREG_NOOP_2 =>
icap_dat_o <= x"2000";
icap_ce_n_o <= '0';
icap_wr_n_o <= '0';
state <= BOOTSTS_NOOP_3;
state <= RDCFGREG_NOOP_3;
when BOOTSTS_NOOP_3 =>
when RDCFGREG_NOOP_3 =>
icap_dat_o <= x"2000";
icap_ce_n_o <= '0';
icap_wr_n_o <= '0';
state <= BOOTSTS_NOOP_4;
state <= RDCFGREG_NOOP_4;
when BOOTSTS_NOOP_4 =>
when RDCFGREG_NOOP_4 =>
icap_dat_o <= x"2000";
icap_ce_n_o <= '0';
icap_wr_n_o <= '0';
state <= BOOTSTS_SETRD_1;
state <= RDCFGREG_SETRD_1;
-- smooth transition of the ICAP write input from write to read
-- (keep CS high while changing WRITE)
when BOOTSTS_SETRD_1 =>
when RDCFGREG_SETRD_1 =>
icap_ce_n_o <= '1';
icap_wr_n_o <= '0';
state <= BOOTSTS_SETRD_2;
state <= RDCFGREG_SETRD_2;
when BOOTSTS_SETRD_2 =>
when RDCFGREG_SETRD_2 =>
icap_ce_n_o <= '1';
icap_wr_n_o <= '1';
state <= BOOTSTS_SETRD_3;
state <= RDCFGREG_SETRD_3;
when BOOTSTS_SETRD_3 =>
when RDCFGREG_SETRD_3 =>
icap_ce_n_o <= '0';
icap_wr_n_o <= '1';
state <= BOOTSTS;
state <= RDCFGREG;
-- this is where we actually read the value of BOOTSTS;
-- this is where we actually read the value of RDCFGREG;
-- data retrieved by ICAP interface is valid when busy is low
when BOOTSTS =>
when RDCFGREG =>
icap_ce_n_o <= '0';
icap_wr_n_o <= '1';
if (icap_busy_i = '0') then
reg_bootsts_img_o <= icap_dat_i;
reg_bootsts_valid_o <= '1';
state <= BOOTSTS_SETWR_1;
reg_cfgreg_img_o <= icap_dat_i;
reg_cfgreg_valid_o <= '1';
state <= RDCFGREG_SETWR_1;
end if;
-- smooth transition of the ICAP write input from read to write
-- (keep CS high while changing WRITE)
when BOOTSTS_SETWR_1 =>
when RDCFGREG_SETWR_1 =>
icap_ce_n_o <= '1';
icap_wr_n_o <= '1';
state <= BOOTSTS_SETWR_2;
state <= RDCFGREG_SETWR_2;
when BOOTSTS_SETWR_2 =>
when RDCFGREG_SETWR_2 =>
icap_ce_n_o <= '1';
icap_wr_n_o <= '0';
state <= BOOTSTS_SETWR_3;
state <= RDCFGREG_SETWR_3;
when BOOTSTS_SETWR_3 =>
when RDCFGREG_SETWR_3 =>
icap_ce_n_o <= '0';
icap_wr_n_o <= '0';
if (icap_busy_i = '0') then
......
hdl/multiboot/rtl/multiboot_regs.vhd
View file @ 1fa8d796
......@@ -54,12 +54,13 @@ entity multiboot_regs is
wb_stall_o : out std_logic;
-- Fields of control register
multiboot_cr_rdbootsts_o : out std_logic;
multiboot_cr_iprog_o : out std_logic;
multiboot_cr_rdcfgreg_o : out std_logic;
multiboot_cr_cfgregadr_o : out std_logic_vector(5 downto 0);
multiboot_cr_iprog_o : out std_logic;
-- Fields of status register
multiboot_sr_bootsts_img_i : in std_logic_vector(15 downto 0);
multiboot_sr_valid_i : in std_logic;
multiboot_sr_cfgreg_img_i : in std_logic_vector(15 downto 0);
multiboot_sr_valid_i : in std_logic;
-- Fields of bitstream address registers
multiboot_gbbar_o : out std_logic_vector(31 downto 0);
......@@ -77,12 +78,13 @@ end multiboot_regs;
architecture behav of multiboot_regs is
signal multiboot_cr_rdbootsts_int : std_logic;
signal multiboot_cr_rdcfgreg_int : std_logic;
signal multiboot_cr_cfgregadr_int : std_logic_vector(5 downto 0);
signal multiboot_cr_iprog_int : std_logic;
signal multiboot_cr_iprog_unl_int : std_logic;
signal multiboot_cr_flr_int : std_logic;
signal multiboot_cr_flw_int : std_logic;
signal multiboot_sr_bootsts_img_int : std_logic_vector(15 downto 0);
signal multiboot_sr_cfgreg_img_int : std_logic_vector(15 downto 0);
signal multiboot_sr_valid_int : std_logic;
signal multiboot_sr_flrrdy_int : std_logic;
signal multiboot_sr_flwrdy_int : std_logic;
......@@ -108,10 +110,10 @@ begin
wrdata_reg <= wb_dat_i;
rwaddr_reg <= wb_adr_i;
multiboot_sr_bootsts_img_int <= multiboot_sr_bootsts_img_i;
multiboot_sr_valid_int <= multiboot_sr_valid_i;
multiboot_sr_cfgreg_img_int <= multiboot_sr_cfgreg_img_i;
multiboot_sr_valid_int <= multiboot_sr_valid_i;
multiboot_far_ready_int <= multiboot_far_ready_i;
multiboot_far_ready_int <= multiboot_far_ready_i;
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
......@@ -120,7 +122,8 @@ begin
ack_sreg <= (others => '0');
ack_in_progress <= '0';
rddata_reg <= (others => '0');
multiboot_cr_rdbootsts_int <= '0';
multiboot_cr_rdcfgreg_int <= '0';
multiboot_cr_cfgregadr_int <= (others => '0');
multiboot_cr_iprog_int <= '0';
multiboot_cr_iprog_unl_int <= '0';
multiboot_gbbar_int <= (others => '0');
......@@ -134,7 +137,7 @@ begin
ack_sreg(0) <= ack_sreg(1);
ack_sreg(1) <= '0';
if (ack_in_progress = '1') then
multiboot_cr_rdbootsts_int <= '0';
multiboot_cr_rdcfgreg_int <= '0';
multiboot_far_xfer_int <= '0';
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
......@@ -145,19 +148,15 @@ begin
case rwaddr_reg is
when "000" =>
if (wb_we_i = '1') then
multiboot_cr_rdbootsts_int <= wrdata_reg(0);
multiboot_cr_cfgregadr_int <= wrdata_reg(5 downto 0);
multiboot_cr_rdcfgreg_int <= wrdata_reg(6);
multiboot_cr_iprog_unl_int <= wrdata_reg(16);
if (multiboot_cr_iprog_unl_int = '1') then
multiboot_cr_iprog_int <= wrdata_reg(17);
end if;
end if;
rddata_reg(0) <= multiboot_cr_rdbootsts_int;
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(5 downto 0) <= multiboot_cr_cfgregadr_int;
rddata_reg(6) <= multiboot_cr_rdcfgreg_int;
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
......@@ -188,7 +187,7 @@ begin
when "001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(15 downto 0) <= multiboot_sr_bootsts_img_int;
rddata_reg(15 downto 0) <= multiboot_sr_cfgreg_img_int;
rddata_reg(16) <= multiboot_sr_valid_int;
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
......@@ -255,8 +254,11 @@ begin
-- Drive the stall line
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- Read BOOTSTS register
multiboot_cr_rdbootsts_o <= multiboot_cr_rdbootsts_int;
-- Configuration register address
multiboot_cr_cfgregadr_o <= multiboot_cr_cfgregadr_int;
-- Read configuration register
multiboot_cr_rdcfgreg_o <= multiboot_cr_rdcfgreg_int;
-- IPROG
multiboot_cr_iprog_o <= multiboot_cr_iprog_int;
......
hdl/multiboot/rtl/xil_multiboot.vhd
View file @ 1fa8d796
......@@ -87,12 +87,13 @@ architecture behav of xil_multiboot is
wb_stall_o : out std_logic;
-- Fields of control register
multiboot_cr_rdbootsts_o : out std_logic;
multiboot_cr_iprog_o : out std_logic;
multiboot_cr_rdcfgreg_o : out std_logic;
multiboot_cr_cfgregadr_o : out std_logic_vector(5 downto 0);
multiboot_cr_iprog_o : out std_logic;
-- Fields of status register
multiboot_sr_bootsts_img_i : in std_logic_vector(15 downto 0);
multiboot_sr_valid_i : in std_logic;
multiboot_sr_cfgreg_img_i : in std_logic_vector(15 downto 0);
multiboot_sr_valid_i : in std_logic;
-- Fields of bitstream address registers
multiboot_gbbar_o : out std_logic_vector(31 downto 0);
......@@ -117,7 +118,8 @@ architecture behav of xil_multiboot is
rst_n_i : in std_logic;
-- Control register inputs
reg_rdbootsts_i : in std_logic;
reg_rdcfgreg_i : in std_logic;
reg_cfgregadr_i : in std_logic_vector(5 downto 0);
reg_iprog_i : in std_logic;
-- Multiboot and golden bitstream start addresses
......@@ -125,8 +127,8 @@ architecture behav of xil_multiboot is
reg_mbbar_i : in std_logic_vector(31 downto 0);
-- Outputs to status register
reg_bootsts_img_o : out std_logic_vector(15 downto 0);
reg_bootsts_valid_o : out std_logic;
reg_cfgreg_img_o : out std_logic_vector(15 downto 0);
reg_cfgreg_valid_o : out std_logic;
-- Flash access register signals
reg_far_data_i : in std_logic_vector(23 downto 0);
......@@ -197,9 +199,10 @@ architecture behav of xil_multiboot is
-- Signal declarations
--============================================================================
-- Control and status register signals
signal rdbootsts : std_logic;
signal rdcfgreg : std_logic;
signal cfgregadr : std_logic_vector(5 downto 0);
signal iprog : std_logic;
signal bootsts_img : std_logic_vector(15 downto 0);
signal cfgreg_img : std_logic_vector(15 downto 0);
signal sr_valid : std_logic;
signal gbbar, mbbar : std_logic_vector(31 downto 0);
......@@ -253,10 +256,11 @@ begin
wb_ack_o => wbs_o.ack,
wb_stall_o => wbs_o.stall,
multiboot_cr_rdbootsts_o => rdbootsts,
multiboot_cr_rdcfgreg_o => rdcfgreg,
multiboot_cr_cfgregadr_o => cfgregadr,
multiboot_cr_iprog_o => iprog,
multiboot_sr_bootsts_img_i => bootsts_img,
multiboot_sr_cfgreg_img_i => cfgreg_img,
multiboot_sr_valid_i => sr_valid,
multiboot_gbbar_o => gbbar,
......@@ -279,14 +283,15 @@ begin
clk_i => clk_i,
rst_n_i => rst_n_i,
reg_rdbootsts_i => rdbootsts,
reg_rdcfgreg_i => rdcfgreg,
reg_cfgregadr_i => cfgregadr,
reg_iprog_i => iprog,
reg_gbbar_i => gbbar,
reg_mbbar_i => mbbar,
reg_bootsts_img_o => bootsts_img,
reg_bootsts_valid_o => sr_valid,
reg_cfgreg_img_o => cfgreg_img,
reg_cfgreg_valid_o => sr_valid,
reg_far_data_i => far_data_out,
reg_far_data_o => far_data_in,
......
hdl/multiboot/syn/conv_ttl_blo.gise 0 → 100644
View file @ 1fa8d796
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="conv_ttl_blo.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="conv_ttl_blo.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="conv_ttl_blo.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="conv_ttl_blo.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="conv_ttl_blo.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="conv_ttl_blo.xst"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="conv_ttl_blo_xst.xrpt"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1382087311" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1382087311">
<status xil_pn:value="SuccessfullyRun"/>
</transform>
<transform xil_pn:end_ts="1382087311" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1700432985017783241" xil_pn:start_ts="1382087311">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1382087311" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5050901284947628582" xil_pn:start_ts="1382087311">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1382087311" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1382087311">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1382087311" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2180482239361632071" xil_pn:start_ts="1382087311">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1382087311" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1382087311">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1382087311" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-6206634123545964380" xil_pn:start_ts="1382087311">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1382087321" xil_pn:in_ck="-7576895194167686066" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8267614965335338665" xil_pn:start_ts="1382087311">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo.lso"/>
<outfile xil_pn:name="conv_ttl_blo.prj"/>
<outfile xil_pn:name="conv_ttl_blo.syr"/>
<outfile xil_pn:name="conv_ttl_blo.xst"/>
<outfile xil_pn:name="conv_ttl_blo_xst.xrpt"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1382087321" xil_pn:in_ck="3498961748663175870" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3953035127305197084" xil_pn:start_ts="1382087321">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
</transforms>
</generated_project>
hdl/multiboot/syn/run.tcl 0 → 100644
View file @ 1fa8d796
project open conv_ttl_blo.xise
process run {Generate Programming File} -force rerun_all
hdl/release/syn/conv_ttl_blo.gise
View file @ 1fa8d796
......@@ -30,6 +30,7 @@
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="conv_ttl_blo.bgn" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:fileType="FILE_BIN" xil_pn:name="conv_ttl_blo.bin"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="conv_ttl_blo.bit" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="conv_ttl_blo.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="conv_ttl_blo.cmd_log"/>
......@@ -74,35 +75,35 @@
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1381853702" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1381853702">
<transform xil_pn:end_ts="1382087370" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1382087370">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1381853702" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1700432985017783241" xil_pn:start_ts="1381853702">
<transform xil_pn:end_ts="1382087370" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1700432985017783241" xil_pn:start_ts="1382087370">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1381853702" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5050901284947628582" xil_pn:start_ts="1381853702">
<transform xil_pn:end_ts="1382087370" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5050901284947628582" xil_pn:start_ts="1382087370">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1381853702" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1381853702">
<transform xil_pn:end_ts="1382087370" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1382087370">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1381853702" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2180482239361632071" xil_pn:start_ts="1381853702">
<transform xil_pn:end_ts="1382087370" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2180482239361632071" xil_pn:start_ts="1382087370">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1381853702" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1381853702">
<transform xil_pn:end_ts="1382087370" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1382087370">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1381853702" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-6206634123545964380" xil_pn:start_ts="1381853702">
<transform xil_pn:end_ts="1382087370" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-6206634123545964380" xil_pn:start_ts="1382087370">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1381853724" xil_pn:in_ck="3190287689474023470" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8267614965335338665" xil_pn:start_ts="1381853702">
<transform xil_pn:end_ts="1382359472" xil_pn:in_ck="3190287689474023470" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8267614965335338665" xil_pn:start_ts="1382359451">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -120,11 +121,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1381853724" xil_pn:in_ck="3498961748663175870" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3953035127305197084" xil_pn:start_ts="1381853724">
<transform xil_pn:end_ts="1382087394" xil_pn:in_ck="3498961748663175870" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3953035127305197084" xil_pn:start_ts="1382087394">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1381853733" xil_pn:in_ck="4600148398000832553" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7879307074684351365" xil_pn:start_ts="1381853724">
<transform xil_pn:end_ts="1382359479" xil_pn:in_ck="4600148398000832553" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7879307074684351365" xil_pn:start_ts="1382359472">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
......@@ -133,9 +134,11 @@
<outfile xil_pn:name="conv_ttl_blo.ngd"/>
<outfile xil_pn:name="conv_ttl_blo_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1381853789" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1381853733">
<transform xil_pn:end_ts="1382359619" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1382359479">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo.pcf"/>
<outfile xil_pn:name="conv_ttl_blo_map.map"/>
......@@ -146,8 +149,9 @@
<outfile xil_pn:name="conv_ttl_blo_summary.xml"/>
<outfile xil_pn:name="conv_ttl_blo_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1381853845" xil_pn:in_ck="-9057307156948659133" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1381853789">
<transform xil_pn:end_ts="1382359669" xil_pn:in_ck="-9057307156948659133" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1382359619">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo.ncd"/>
......@@ -160,19 +164,20 @@
<outfile xil_pn:name="conv_ttl_blo_pad.txt"/>
<outfile xil_pn:name="conv_ttl_blo_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1381853881" xil_pn:in_ck="-336926714118358808" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1381853845">
<transform xil_pn:end_ts="1382431700" xil_pn:in_ck="-336926714118358808" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3952527596078283548" xil_pn:start_ts="1382431666">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo.bgn"/>
<outfile xil_pn:name="conv_ttl_blo.bin"/>
<outfile xil_pn:name="conv_ttl_blo.bit"/>
<outfile xil_pn:name="conv_ttl_blo.drc"/>
<outfile xil_pn:name="conv_ttl_blo.ut"/>
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1381853845" xil_pn:in_ck="4600148398000832422" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1381853834">
<transform xil_pn:end_ts="1382359669" xil_pn:in_ck="4600148398000832422" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1382359661">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/release/syn/conv_ttl_blo.xise
View file @ 1fa8d796
......@@ -56,7 +56,7 @@
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -164,7 +164,7 @@
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x0b170000" xil_pn:valueState="non-default"/>
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
......@@ -175,7 +175,7 @@
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="-g next_config_register_write:Disable" xil_pn:valueState="non-default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -243,7 +243,7 @@
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
......@@ -313,7 +313,7 @@
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0x1FFF" xil_pn:valueState="non-default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<!-- -->
......
hdl/release/top/conv_ttl_blo.vhd
View file @ 1fa8d796
......@@ -125,7 +125,7 @@ architecture behav of conv_ttl_blo is
-- Constant declarations
--============================================================================
-- Firmware version
constant c_fwvers : std_logic_vector(15 downto 0) := x"0200";
constant c_fwvers : std_logic_vector(15 downto 0) := x"0201";
-- Number of Wishbone masters and slaves, for wb_crossbar
constant c_nr_masters : natural := 1;
......
hdl/vbcp_wb/rtl/vbcp_wb.vhd
View file @ 1fa8d796
......@@ -13,7 +13,7 @@
-- This module implements an I2C to Wishbone bridge for VME64x crates,
-- following the protocol defined in [1]. It uses a low-level I2C slave module
-- reacting to transfers initiated by an I2C master, in this case, a VME64x
-- system monitor (SysMon) [2]. i
-- system monitor (SysMon) [2].
--
-- The I2C slave module sets its done_p_o pin high when the I2C address received
-- from the SysMon corresponds to the slave address and every time a byte has
......
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