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Conv TTL Blocking - Gateware
Commit 1a34f694 authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
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Small modification in p_inhibit_first_pulse process, now checks that all lines… 

Small modification in p_inhibit_first_pulse process, now checks that all lines are low before end of 100us first pulse inhibit period.
parent 257f2226
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sim/Release/burst_ctrl_tb.vhd
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sim/Release/testbenchv4.vhd
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syn/Release/iseconfig/conv_ttl_blo.xreport
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syn/Release/testbench_envsettings.html
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......@@ -22,7 +22,7 @@
</tr>
<tr>
<td>Path</td>
<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files (x86)\Skype\Phone\;<br>C:\EDA\Cadence\SPB_166\tools\pspice;<br>C:\EDA\Cadence\SPB_166\tools\capture;<br>C:\EDA\Cadence\SPB_166\tools\bin;<br>C:\EDA\Cadence\SPB_166\openaccess\bin\win32\opt;<br>C:\EDA\Cadence\SPB_166\tools\fet\bin;<br>C:\EDA\Cadence\SPB_166\tools\pcb\bin;<br>C:\EDA\Cadence\SPB_166\tools\specctra\bin;<br>C:\EDA\Cadence\SPB_166\tools\libutil\bin;<br>C:\Program Files\TortoiseGit\bin;<br>C:\Users\debouhir\Documents\MikTex\miktex\bin\;<br>C:\Program Files\wbgen2-bin.tar\bin;<br>C:\Program Files\Git\cmd;<br>C:\modeltech64_10.1c\win64</td>
<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files (x86)\Skype\Phone\;<br>C:\EDA\Cadence\SPB_166\tools\pspice;<br>C:\EDA\Cadence\SPB_166\tools\capture;<br>C:\EDA\Cadence\SPB_166\tools\bin;<br>C:\EDA\Cadence\SPB_166\openaccess\bin\win32\opt;<br>C:\EDA\Cadence\SPB_166\tools\fet\bin;<br>C:\EDA\Cadence\SPB_166\tools\pcb\bin;<br>C:\EDA\Cadence\SPB_166\tools\specctra\bin;<br>C:\EDA\Cadence\SPB_166\tools\libutil\bin;<br>C:\Program Files\TortoiseGit\bin;<br>C:\Users\debouhir\Documents\MikTex\miktex\bin\;<br>C:\Program Files\wbgen2-bin.tar\bin;<br>C:\Program Files\Git\cmd;<br>C:\VXIPNP\WinNT\Bin;<br>C:\modeltech64_10.1c\win64</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
......@@ -95,7 +95,7 @@
<tr>
<td>-p</td>
<td>&nbsp;</td>
<td>xc6slx4-3-tqg144</td>
<td>xc6slx45t-3-fgg484</td>
<td>&nbsp;</td>
</tr>
<tr>
......
syn/Release/testbench_summary.html
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......@@ -7,16 +7,17 @@
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>conv_ttl_blo.xise</TD>
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
<TD ALIGN=LEFT><font color='red'; face='Arial'><b>X </b></font><A HREF_DISABLED='C:/Users/debouhir/work/CONV-TTL-BLO/conv-ttl-blo/conv-ttl-blo-gw/syn/Release\_xmsgs/pn_parser.xmsgs?&DataKey=Error'>1 Error</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>conv_ttl_blo</TD>
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
<TD>New</TD>
<TD>New (Failed)</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc6slx4-3tqg144</TD>
<TD>xc6slx45t-3fgg484</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
......@@ -40,7 +41,10 @@
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
<TD>&nbsp;</TD>
<TD>
<A HREF_DISABLED='C:/Users/debouhir/work/CONV-TTL-BLO/conv-ttl-blo/conv-ttl-blo-gw/syn/Release\testbench_envsettings.html'>
System Settings</A>
</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
<TD>&nbsp;&nbsp;</TD>
</TR>
......@@ -71,8 +75,9 @@
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/debouhir/work/CONV-TTL-BLO/conv-ttl-blo/conv-ttl-blo-gw/syn/Release\isim.log'>ISIM Simulator Log</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Tue 7. Feb 16:41:32 2017</TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 11/10/2016 - 12:17:10</center>
<br><center><b>Date Generated:</b> 02/13/2017 - 18:37:49</center>
</BODY></HTML>
\ No newline at end of file
syn/Release/transcript
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top/Release/conv_ttl_blo.vhd
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......@@ -52,6 +52,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
......@@ -82,10 +83,10 @@ entity conv_ttl_blo is
vme_sysreset_n_i : in std_logic;
vme_ga_i : in std_logic_vector(4 downto 0);
vme_gap_i : in std_logic;
-- PCB version recognition
pcbrev_i : in std_logic_vector(5 downto 0);
pcbrev_i : in std_logic_vector(5 downto 0);
-- Channel enable
global_oen_o : out std_logic;
ttl_oen_o : out std_logic;
......@@ -197,9 +198,9 @@ architecture arch of conv_ttl_blo is
-- TTL & RS485 signals
signal rs485_fs : std_logic_vector(c_nr_chans-1 downto 0);
signal pulse_in : std_logic_vector(c_nr_chans-1 downto 0);
signal inv_pulse_in_n : std_logic_vector(c_nr_inv_chans-1 downto 0);
signal inv_pulse_in_n : std_logic_vector(c_nr_inv_chans-1 downto 0);
signal pulse_out : std_logic_vector(c_nr_chans-1 downto 0);
signal inv_pulse_out : std_logic_vector(c_nr_inv_chans-1 downto 0);
signal inv_pulse_out : std_logic_vector(c_nr_inv_chans-1 downto 0);
signal pulse_ttl : std_logic_vector(c_nr_chans-1 downto 0);
signal pulse_blo : std_logic_vector(c_nr_chans-1 downto 0);
signal inhibit_first_pulse : std_logic;
......@@ -207,8 +208,8 @@ architecture arch of conv_ttl_blo is
signal inhibit_cnt : unsigned(10 downto 0);
--Temperature model constantstemp_decre_step_lg
signal temp_decre_step_lg : t_temp_decre_step;
signal temp_decre_step_sh : t_temp_decre_step;
signal temp_decre_step_lg : t_temp_decre_step;
signal temp_decre_step_sh : t_temp_decre_step;
-- Line signals -- for reflection in line status register of conv_common_gw
signal line_ttl : std_logic_vector(c_nr_chans-1 downto 0);
......@@ -217,7 +218,7 @@ architecture arch of conv_ttl_blo is
-- Switch signals (for inverting switch inputs to the common g/w)
signal sw_ttl : std_logic;
signal burst_en_n : std_logic;
signal burst_en_n : std_logic;
signal sw_gp : std_logic_vector(7 downto 0);
signal pgen_duty_cycle_div_lg : natural range 8 to 300;
......@@ -228,7 +229,7 @@ architecture arch of conv_ttl_blo is
-- Channel LED signals
signal led_pulse : std_logic_vector(c_nr_chans-1 downto 0);
signal led_inv_pulse : std_logic_vector(c_nr_inv_chans-1 downto 0);
signal led_inv_pulse : std_logic_vector(c_nr_inv_chans-1 downto 0);
signal led_rear : std_logic_vector(c_nr_chans-1 downto 0);
-- I2C LEDs
......@@ -298,7 +299,7 @@ begin
inhibit_first_pulse <= '1';
elsif (inhibit_first_pulse = '1') then
inhibit_cnt <= inhibit_cnt + 1;
if (inhibit_cnt = 1999) then
if (inhibit_cnt >= 1999 and and_reduce(ttl_n_i)='1') then
inhibit_first_pulse <= '0';
end if;
end if;
......@@ -317,11 +318,7 @@ begin
end if;
end if;
end process;
-- Pulse input valid only after inhibit period is over
pulse_in <= (pulse_ttl or pulse_blo) when (inhibit_first_pulse_d0 = '0') else
(others => '0');
......@@ -335,23 +332,22 @@ begin
-- Switch inputs for reflection in status register
sw_gp <= not sw_gp_n_i;
-- Switch to determine short or long pulse mode.
-- ON switch means SHORT 250ns pulse repetition with max frequency 2MHz
-- OFF switch means LONG 1.2us pulse repetition with max freq ~104kHz
--Note that this burst mode functionality is activated only for PCB v4 or later
--The FPGA
-- Functionality enabled for versions 4 and above
-- when version is below 4 then disable burst functionality
-- burst_en_n <= '0' when pcbrev_i (5 downto 0) >= "010000" else '1';
-- burst_en_n <= '0' when pcbrev_i (5 downto 0) >= "010000" else '1';
--**************************************************************************
--This change code is only used as a hack for v3 boards, which are able to
--**************************************************************************
--This change code is only used as a hack for v3 boards, which are able to
-- support v4 functionality
burst_en_n <= '0' when sw_gp_n_i(6)= '0'
else '1';
--**************************************************************************
burst_en_n <= '0' when sw_gp_n_i(6)= '0'
else '1';
--**************************************************************************
--============================================================================
-- Instantiate common generic gateware for converter boards
--============================================================================
......@@ -360,33 +356,33 @@ begin
(
g_nr_chans => 6,
g_nr_inv_chans => 4,
g_board_id => c_board_id,
g_gwvers => c_gwvers,
g_pgen_fixed_width => true,
g_pgen_pwidth_lg => 24,
g_pgen_pwidth_sh => 5,
g_pgen_pperiod_cont=> 4800,
-- Minimum period supported for 1.2us pulse ~ max freq 104kHz
g_pgen_pperiod_lg => 191,
-- Minimum period supported for 250ns pulse ~ max freq 2MHz
g_pgen_pperiod_sh => 9,
g_pgen_gf_len => 1,
g_temp_decre_step_lg => (0,0,0,0,0,0,0,0,2500,731,220,250,40,85,50,125),
g_temp_decre_step_sh => (0,0, 769, 31, 104, 14, 82, 0 ,0, 0, 0, 0, 0, 0, 0, 0),
g_burstctrl_1_pulse_temp_rise_lg => x"17700", --96000
g_burstctrl_1_pulse_temp_rise_sh => x"01388", --5000
g_burstctrl_max_temp_lg_sh=> x"02540BE400", -- 10^10 --In final release use this value
-- g_burstctrl_max_temp_lg_sh=> x"00000F4240", --10^6 --This value is used to speed up simulation
g_with_pulse_cnt => true,
g_with_pulse_timetag => true,
g_with_man_trig => true,
g_man_trig_pwidth => 24,
g_with_thermometer => true,
g_bicolor_led_columns => c_bicolor_led_cols,
g_bicolor_led_lines => c_bicolor_led_lines
g_nr_chans => 6,
g_nr_inv_chans => 4,
g_board_id => c_board_id,
g_gwvers => c_gwvers,
g_pgen_fixed_width => true,
g_pgen_pwidth_lg => 24,
g_pgen_pwidth_sh => 5,
g_pgen_pperiod_cont => 4800,
-- Minimum period supported for 1.2us pulse ~ max freq 104kHz
g_pgen_pperiod_lg => 191,
-- Minimum period supported for 250ns pulse ~ max freq 2MHz
g_pgen_pperiod_sh => 9,
g_pgen_gf_len => 1,
g_temp_decre_step_lg => (0,0,0,0,0,0,0,0,2500,731,220,250,40,85,50,125),
g_temp_decre_step_sh => (0,0, 769, 31, 104, 14, 82, 0 ,0, 0, 0, 0, 0, 0, 0, 0),
g_burstctrl_1_pulse_temp_rise_lg => x"17700", --96000
g_burstctrl_1_pulse_temp_rise_sh => x"01388", --5000
g_burstctrl_max_temp_lg_sh=> x"02540BE400", -- 10^10 --In final release use this value
-- g_burstctrl_max_temp_lg_sh=> x"00000F4240", --10^6 --This value is used to speed up simulation
g_with_pulse_cnt => true,
g_with_pulse_timetag => true,
g_with_man_trig => true,
g_man_trig_pwidth => 24,
g_with_thermometer => true,
g_bicolor_led_columns => c_bicolor_led_cols,
g_bicolor_led_lines => c_bicolor_led_lines
)
port map
(
......@@ -400,12 +396,16 @@ begin
-- Glitch filter active-low enable signal
gf_en_n_i => sw_gp_n_i(0),
-- Burst mode enable signal. Mode disabled for all versions of board
burst_en_n_i => burst_en_n,
-- Pulse width selection, port low means 250ns, high means 1.2us.
pulse_width_sel_n_i => sw_gp_n_i(1),
-- Burst mode enable signal. Mode disabled for all versions of board
burst_en_n_i => burst_en_n,
-- Pulse width selection, port low means 250ns, high means 1.2us.
-- Switch to determine short or long pulse mode.
-- ON switch means SHORT 250ns pulse repetition with max frequency 2MHz
-- OFF switch means LONG 1.2us pulse repetition with max freq ~104kHz
pulse_width_sel_n_i => sw_gp_n_i(1),
-- Channel enable
global_ch_oen_o => global_oen_o,
......@@ -415,19 +415,19 @@ begin
-- Front panel channels
pulse_i => pulse_in,
pulse_ttl_i => pulse_ttl,
pulse_blo_i => pulse_blo,
pulse_ttl_i => pulse_ttl,
pulse_blo_i => pulse_blo,
pulse_o => pulse_out,
-- Inverted pulse I/O
inv_pulse_i_n => inv_pulse_in_n,
inv_pulse_o => inv_pulse_out,
-- Inverted pulse I/O
inv_pulse_i_n => inv_pulse_in_n,
inv_pulse_o => inv_pulse_out,
-- Channel leds
-- Channel leds
led_pulse_o => led_pulse,
-- inverted channel leds
led_inv_pulse_o => led_inv_pulse,
-- inverted channel leds
led_inv_pulse_o => led_inv_pulse,
-- I2C LED signals -- conect to a bicolor LED of choice
-- led_i2c_o pulses four times on I2C transfer
......@@ -476,7 +476,7 @@ begin
sw_other_i => (others => '0'),
-- PCB Version information
hwvers_i => pcbrev_i,
hwvers_i => pcbrev_i,
-- RTM lines
rtmm_i => rtmm_i,
rtmp_i => rtmp_i,
......
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