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Conv TTL Blocking - Gateware
Commit 1a34f694 authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
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Small modification in p_inhibit_first_pulse process, now checks that all lines… 

Small modification in p_inhibit_first_pulse process, now checks that all lines are low before end of 100us first pulse inhibit period.
parent 257f2226
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sim/Release/burst_ctrl_tb.vhd
View file @ 1a34f694
......@@ -58,8 +58,17 @@ architecture behav of testbench is
-- Clock periods
constant c_clk_20_per : time := 50 ns;
constant random_intervals : boolean := false;
constant c_pgen_pwidth : natural := 5;
constant c_pgen_pwidth: natural := 5;
constant c_pgen_duty_cycle_div : natural := 2;
constant pwidth_sel : std_logic := '0';
constant gf_en_n :std_logic:= '0';
constant test_pgen : boolean:=false;
-- constant g_temp_decre_step_in: t_temp_decre_step := (0,0,0,0,0,0,0,0,2500,731,220,250,40,85,50,125);
constant g_temp_decre_step_in: t_temp_decre_step := (0, 0, 769, 31, 104, 14, 82, 0 ,0, 0, 0, 0, 0, 0, 0, 0);
-- constant g_1_pulse_temp_rise_in :unsigned (19 downto 0) := x"17700";
constant g_1_pulse_temp_rise_in :unsigned (19 downto 0) :=x"01388";
type t_time_array is array (2 downto 0) of integer;
component conv_pulse_gen is
generic
......@@ -93,6 +102,8 @@ architecture behav of testbench is
-- Trigger input, has to be '1' to assure pulse output with delay no greater
-- than internal gate delays.
trig_a_i : in std_logic;
trig_r_edge_p_i : in std_logic; --synced 1 cycle-long r edge output
trig_f_edge_p_i : in std_logic; --synced 1 cycle-long f edge output
-- Pulse error output, pulses high for one clock cycle when a pulse arrives
-- within a pulse period
......@@ -128,6 +139,7 @@ end component conv_pulse_gen;
pulse_burst_i : in std_logic;
pulse_r_edge_p_i : in std_logic;
pulse_f_edge_p_i : in std_logic;
temp_rise_o :out unsigned (39 downto 0);
pulse_burst_o : out std_logic;
-- Burst error output, pulses high for one clock cycle when a pulse arrives
......@@ -141,21 +153,41 @@ end component conv_pulse_gen;
-- Signal declarations
signal clk_20 : std_logic;
signal rst : std_logic;
signal rst_n : std_logic;
signal en : std_logic;
signal burst_train_d0 : std_logic;
signal burst_train_d1 : std_logic;
-- signal burst_train_d2 : std_logic;
signal burst_train : std_logic;
signal burst_train_f_edge : std_logic;
signal burst_train_r_edge : std_logic;
signal burst_train_redge_in : std_logic;
signal burst_train_fedge_in : std_logic;
signal burst_train_regulated_dyn : std_logic;
signal rand_num : integer := 0;
signal pulse_outp_err_p :std_logic;
signal burst_outp_err_p :std_logic;
signal pulse_outp :std_logic;
signal pgen_pwidth : integer;
signal pgen_duty_cycle_div : integer;
signal temp_rise : unsigned (39 downto 0);
signal pnumber : integer;
signal period_array_lg : t_time_array;
signal period_array_sh : t_time_array;
signal pwidth_array_lg : t_time_array;
signal pwidth_array_sh : t_time_array;
signal t_start : TIME := NOW;
signal t_sim1 :TIME := 0 ns;
signal t_sim2 :TIME := 0 ns;
signal t_sim3 :TIME := 0 ns;
--==============================================================================
-- architecture begin
--==============================================================================
......@@ -171,6 +203,8 @@ end component conv_pulse_gen;
--============================================================================
-- Instantiate the DUT: Dynamic
--============================================================================
cmp_pulse_gen_sh : conv_pulse_gen
generic map
(
......@@ -181,14 +215,15 @@ end component conv_pulse_gen;
port map
(
clk_i => clk_20,
rst_n_i => rst,
rst_n_i => rst_n,
gf_en_n_i => '1',
gf_en_n_i => gf_en_n,
en_i => '1',
trig_a_i => burst_train,
trig_a_i => burst_train_d1,
trig_r_edge_p_i => burst_train_redge_in,
trig_f_edge_p_i => burst_train_fedge_in,
pulse_err_p_o => pulse_outp_err_p,
pulse_o => pulse_outp,
......@@ -196,32 +231,42 @@ end component conv_pulse_gen;
pulse_f_edge_p_o => burst_train_f_edge
);
cmp_dut : conv_dyn_burst_ctrl
generic map
(
g_pwidth => c_pgen_pwidth, --
-- g_temp_decre_step => (0,0,0,0,0,0,0,0,2500,731,220,250,40,85,50,125),
g_temp_decre_step => (0, 0, 769, 31, 104, 14, 82, 0 ,0, 0, 0, 0, 0, 0, 0, 0),
g_1_pulse_temp_rise => x"01388",
-- g_1_pulse_temp_rise => x"17700", -- for 1.2us pulse
g_temp_decre_step => g_temp_decre_step_in,
g_1_pulse_temp_rise => g_1_pulse_temp_rise_in,
g_max_temp => x"00000F4240" --10^6
-- g_max_temp => x"02540BE400" --10^10
)
port map(
clk_i => clk_20,
rst_n_i => rst,
rst_n_i => rst_n,
en_i => en,
en_i => '1',
pulse_burst_i => pulse_outp,
pulse_r_edge_p_i => burst_train_r_edge,
pulse_f_edge_p_i => burst_train_f_edge,
temp_rise_o => temp_rise,
pulse_burst_o => burst_train_regulated_dyn,
burst_err_p_o => burst_outp_err_p
);
cmp_sync_ffs : gc_sync_ffs
port map
(
clk_i => clk_20,
rst_n_i => rst_n,
data_i => burst_train_d1,
ppulse_o => burst_train_redge_in,
npulse_o => burst_train_fedge_in
);
--============================================================================
-- Generate clock signals
--============================================================================
......@@ -251,11 +296,11 @@ end process p_ran_gen;
process
begin
rst <= '1';
rst_n <= '1';
wait for 2500 ns;
rst <= '0';
rst_n <= '0';
wait for 2000 ns;
rst <= '1';
rst_n <= '1';
wait;
end process;
......@@ -280,51 +325,149 @@ end process p_ran_gen;
-- port map
-- (
-- clk_i => clk_20,
-- rst_n_i => rst,
-- rst_n_i => rst_n,
-- data_i => burst_train,
-- npulse_o => burst_train_f_edge,
-- ppulse_o => burst_train_r_edge
-- );
period_array_lg <= (8000 , 9600 , 20000 );
pwidth_array_lg <= (2000 , 500 , 1200 );
period_array_sh <= (450 , 500 , 1000 );
pwidth_array_sh <= (400 , 100 , 250 );
-- p_sel_params : process
-- variable interval : time;
-- begin
-- -- if rst_n = '1' and en = '1' then
-- --for gf_en_n in
-- if pwidth_sel = '1' then
-- for pwidth_index in 2 downto 0 loop
-- for period_index in 2 downto 0 loop
-- pnumber <= 0;
-- while pnumber < 9 loop
-- -- if random_intervals then
-- -- interval := rand_num * 1 ns;
-- -- if interval < 250 ns then
-- -- interval := 250 ns;
-- -- end if;
-- -- else
-- interval := (period_array_lg(period_index) - pwidth_array_lg(pwidth_index))*1ns;
-- -- end if;
-- burst_train <= '0';
-- wait for interval;
-- burst_train <= '1';
-- wait for pwidth_array_lg(pwidth_index)*1ns;-- changes pulse width
-- burst_train <= '0';
-- pnumber <= pnumber + 1;
-- end loop;
-- wait for 0.1 ms;
-- end loop;
-- wait for 0.2 ms;
-- end loop;
-- wait for 0.5 ms;
-- else
-- for pwidth_index in 2 downto 0 loop
-- for period_index in 2 downto 0 loop
-- pnumber<=0;
-- while pnumber < 9 loop
-- -- if random_intervals then
-- -- interval := rand_num * 1 ns;
-- -- if interval < 250 ns then
-- -- interval := 250 ns;
-- -- end if;
-- -- else
-- interval := (period_array_sh(period_index) - pwidth_array_sh(pwidth_index))*1ns;
-- -- end if;
-- burst_train <= '0';
-- wait for interval;
-- burst_train <= '1';
-- wait for pwidth_array_sh(pwidth_index)*1ns;-- changes pulse width
-- burst_train <= '0';
-- pnumber <= pnumber+1;
-- end loop;
-- wait for 0.01 ms;
-- end loop;
-- wait for 0.02 ms;
-- end loop;
-- wait for 0.05 ms;
-- -- end if;
-- end if;
-- end process p_sel_params;
p_stim_burst1 : process
p_delay : process (clk_20)
begin
if rising_edge(clk_20) then
if (rst_n = '0') then
burst_train_d0 <= '0';
burst_train_d1 <= '0';
else
burst_train_d0 <= burst_train;
burst_train_d1 <= burst_train_d0;
end if;
end if;
end process p_delay;
p_stim_burst1 : process
variable interval : time;-- := 1000 ns;
variable period1 : time := 450 ns;--changes pulse frequency
variable period1 : time := 250 ns;--changes pulse frequency
variable period2 : time := 2000 ns;--changes pulse frequency
variable pwidth : time := 250 ns;
begin
while t_sim1 < 50000 us loop
-- while true loop
t_sim1 <= NOW - t_start;
if random_intervals then
interval := rand_num * 1 ns;
if interval < 250 ns then
interval := 250 ns;
variable period3 : time := 450 ns;--changes pulse frequency
variable pwidth : time := 100 ns;
begin
while t_sim1 < 10000 us loop
t_sim1 <= NOW - t_start;
if random_intervals then
interval := rand_num * 1 ns;
if interval < 250 ns then
interval := 250 ns;
end if;
else
interval := period1 - pwidth;
end if;
else
interval := period1 - pwidth;
end if;
burst_train <= '0';
wait for interval;
burst_train <= '1';
wait for pwidth;-- changes pulse width
burst_train <= '0';
end loop;
while t_sim2 < 10000 us loop
t_sim2 <= NOW - t_sim1;
if random_intervals then
interval := rand_num * 1 ns;
else
interval := period2 - pwidth;
end if;
burst_train <= '0';
wait for interval;
burst_train <= '1';
wait for pwidth;
burst_train <= '0';
end loop;
burst_train <= '0';
wait for 5 ms;
while t_sim3 < 30000 us loop
t_sim3 <= NOW - t_sim1;
interval := period3 - pwidth;
burst_train <= '0';
wait for interval;
burst_train <= '1';
wait for pwidth;-- changes pulse width
burst_train <= '0';
end loop;
while t_sim2 < 100000 us loop
t_sim2 <= NOW - t_sim1;
if random_intervals then
interval := rand_num * 1 ns;
else
interval := period2 - pwidth;
end if;
burst_train <= '0';
wait for interval;
burst_train <= '1';
wait for pwidth;
burst_train <= '0';
end loop;
end process p_stim_burst1;
......
sim/Release/testbenchv4.vhd
View file @ 1a34f694
......@@ -326,6 +326,7 @@ architecture behav of testbench is
signal inv_flag_n : boolean;
signal rand_num : integer := 0;
signal j : integer := 0;
--==============================================================================
-- architecture begin
--==============================================================================
......@@ -471,6 +472,7 @@ begin
blo_pulse <= blo_outp when (oe = '1') and (blo_oe = '1') else (others => '0');
inv_pulse <= inv_outp when (oe = '1') and (inv_oe = '1') else (others => '0');
--============================================================================
--PCB version
--============================================================================
......@@ -521,27 +523,30 @@ end process p_ran_gen;
--============================================================================
-- Pulse stimuli
--============================================================================
blo_inp(6) <= '0';
--blo_inp(6) <= '0';
-- gen_pulse_chain : for i in 6 downto 2 generate
-- blo_inp(i) <= blo_outp(i);
-- end generate gen_pulse_chain;
inv_inp_n <= not inv_inp; --This line is to recover from the inverting buffer which exists on the board
blo_inp(1) <= blo_outp(2);
ttl_inp_n(1) <= '1';
p_stim_pulse : process
p_stim_pulse : process
variable interval : time;-- := 1000 ns;
variable period : time := 500 ns;--changes pulse frequency
variable period : time := 450 ns;--changes pulse frequency
--variable period2 : time := 20000 ns;--changes pulse frequency
variable pwidth : time := 250 ns;
variable pwidth : time := 250 ns;
begin
ttl_inp_n(6 downto 1) <= (others => '1');
inv_inp (4 downto 1) <= (others => '0');
blo_inp(6 downto 1) <= (others => '0');
--wait until inv_flag_n = true;
ttl_inp_n(6 downto 2) <= (others => '1');
inv_inp (4 downto 1) <= (others => '0');
blo_inp(6 downto 2) <= (others => '0');
--wait until inv_flag_n = true;
while true loop
--while (inv_flag_n = true) loop
if random_intervals then
......@@ -550,22 +555,25 @@ end process p_ran_gen;
interval := 250 ns;
end if;
else
interval := period - pwidth;--changes pulse frequencyccc
interval := period - pwidth;--changes pulse frequency
end if;
--Activate for loop if all channels should be testfed
--for j in 2 downto 2 loop --change loop counter range to change number of channels to be tested
j<=0;
while j <99 loop --change loop counter range to change number of channels to be tested
ttl_inp_n(2) <= '1'; --testing only channel 1
wait for interval;
ttl_inp_n(2) <= '0';
wait for pwidth;
ttl_inp_n(2) <= '1';
if ttl_outp(2) /= '1' then
assert false report "ttl_outp not '1'" severity warning;
end if;
if blo_outp(2) /= '1' then
assert false report "blo_outp not '1'" severity warning;
end if;
--blo_inp(j) <= '0';
--wait for 10 us;
--blo_inp(j) <= '1';
......@@ -577,41 +585,47 @@ end process p_ran_gen;
--if blo_outp(j) /= '1' then
-- assert false report "blo_outp not '1'" severity warning;
--end if;
--end loop;
j<=j+1;
end loop;
wait for 1 us;
while (inv_flag_n = false) loop
for j in 4 downto 1 loop
inv_inp(j) <= '0';
wait for 240 us;
inv_inp(j) <= '1';
wait for 450 ns;
if inv_outp(j) /= '1' then
assert false report "inv_ttl_outp not '1'" severity warning;
end if;
wait for 50 ns;
inv_inp(j) <= '0';
if blo_outp(6) /= '1' then
assert false report "blo_outp not '1'" severity warning;
end if;
end loop;
end loop;
-- while (inv_flag_n = false) loop
-- for j in 4 downto 1 loop
-- inv_inp(j) <= '0';
-- wait for 240 us;
-- inv_inp(j) <= '1';
-- wait for 450 ns;
-- if inv_outp(j) /= '1' then
-- assert false report "inv_ttl_outp not '1'" severity warning;
-- end if;
-- wait for 50 ns;
-- inv_inp(j) <= '0';
-- if blo_outp(6) /= '1' then
-- assert false report "blo_outp not '1'" severity warning;
-- end if;
-- end loop;
-- end loop;
end loop;
end process p_stim_pulse;
process
begin
inv_flag_n <= true;
wait for 50 ms;
inv_flag_n <= false;
wait for 50 ms;
inv_flag_n <= true;
wait for 10 ms;
inv_flag_n <= false;
wait;
end process;
-- process
-- begin
-- inv_flag_n <= true;
-- wait for 50 ms;
-- inv_flag_n <= false;
-- wait for 50 ms;
-- inv_flag_n <= true;
-- wait for 10 ms;
-- inv_flag_n <= false;
-- wait;
-- end process;
-- ============================================================================
-- I2C master
......@@ -619,283 +633,283 @@ end loop;
--------------------------------------------------------------------------
-- First, the component instantiation
--------------------------------------------------------------------------
cmp_master : i2c_master_byte_ctrl
port map
(
clk => clk_20,
rst => rst,
nReset => rst_n,
ena => '1',
clk_cnt => x"0027",
input signals
start => mst_sta,
stop => mst_sto,
read => mst_rd,
write => mst_wr,
ack_in => mst_ack,
din => mst_dat_in,
output signals
cmd_ack => mst_cmd_ack,
ack_out => ack_fr_slv,
i2c_busy => open,
i2c_al => open,
dout => mst_dat_out,
i2c lines
scl_i => scl,
scl_o => scl_fr_mst,
scl_oen => scl_en_mst,
sda_i => sda,
sda_o => sda_fr_mst,
sda_oen => sda_en_mst
);
Then, the tri-state_i2c_mst buffers on the line
mscl(0) <= scl_fr_mst when (scl_en_mst = '0') else
'1';
msda(0) <= sda_fr_mst when (sda_en_mst = '0') else
'1';
--------------------------------------------------------------------------
-- Bus model instantiation and connection to master and slaves
--------------------------------------------------------------------------
cmp_i2c_bus : i2c_bus_model
generic map
(
g_nr_masters => c_nr_masters,
g_nr_slaves => c_nr_slaves
)
port map
(
mscl_i => mscl,
msda_i => msda,
sscl_i => sscl,
ssda_i => ssda,
scl_o => scl,
sda_o => sda
);
--------------------------------------------------------------------------
-- This FSM controls the signals to the master component to implement the I2C
-- protocol defined together with ELMA. The FSM is controlled by the
-- stimuli process below
--------------------------------------------------------------------------
p_mst_fsm : process (clk_20) is
begin
if rising_edge(clk_20) then
if (rst_n = '0') then
state_i2c_mst <= IDLE;
mst_sta <= '0';
mst_wr <= '0';
mst_sto <= '0';
mst_rd <= '0';
mst_dat_in <= (others => '0');
mst_ack <= '0';
cnt <= (others => '0');
once <= true;
byte_cnt <= (others => '0');
rcvd <= (others => '0');
send <= (others => '0');
else
case state_i2c_mst is
when IDLE =>
if (mst_fsm_start = '1') then
state_i2c_mst <= I2C_ADDR;
send <= std_logic_vector(send_val);
end if;
when I2C_ADDR =>
mst_sta <= '1';
mst_wr <= '1';
mst_dat_in <= slv_addr & '0';
if (mst_cmd_ack = '1') then
mst_sta <= '0';
mst_wr <= '0';
state_i2c_mst <= I2C_ADDR_ACK;
end if;
when I2C_ADDR_ACK =>
cnt <= cnt + 1;
if (cnt = 7) then
if (ack_fr_slv = '0') then
state_i2c_mst <= WB_ADDR_B0;
else
state_i2c_mst <= ERR;
end if;
end if;
when WB_ADDR_B0 =>
mst_wr <= '1';
mst_dat_in <= adr(15 downto 8);
if (mst_cmd_ack = '1') then
mst_wr <= '0';
state_i2c_mst <= WB_ADDR_B0_ACK;
end if;
when WB_ADDR_B0_ACK =>
cnt <= cnt + 1;
if (cnt = 7) then
if (ack_fr_slv = '0') then
state_i2c_mst <= WB_ADDR_B1;
else
state_i2c_mst <= ERR;
end if;
end if;
when WB_ADDR_B1 =>
mst_wr <= '1';
mst_dat_in <= adr(7 downto 0);
if (mst_cmd_ack = '1') then
mst_wr <= '0';
state_i2c_mst <= WB_ADDR_B1_ACK;
end if;
when WB_ADDR_B1_ACK =>
cnt <= cnt + 1;
if (cnt = 7) then
if (ack_fr_slv = '0') then
state_i2c_mst <= ST_OP;
else
state_i2c_mst <= ERR;
end if;
end if;
when ST_OP =>
if (mst_fsm_op = '1') then
state_i2c_mst <= RD_RESTART;
else
state_i2c_mst <= WR;
end if;
when RD_RESTART =>
mst_wr <= '1';
mst_dat_in <= slv_addr & '1';
mst_sta <= '1';
if (mst_cmd_ack = '1') then
mst_sta <= '0';
mst_wr <= '0';
state_i2c_mst <= RD_RESTART_ACK;
end if;
when RD_RESTART_ACK =>
cnt <= cnt + 1;
if (cnt = 7) then
if (ack_fr_slv = '0') then
state_i2c_mst <= RD;
else
state_i2c_mst <= ERR;
end if;
end if;
when RD =>
mst_rd <= '1';
mst_ack <= '0';
if (byte_cnt = 3) then
mst_ack <= '1';
end if;
if (mst_cmd_ack = '1') then
mst_rd <= '0';
byte_cnt <= byte_cnt + 1;
rcvd <= mst_dat_out & rcvd(31 downto 8);
mst_ack <= '0';
state_i2c_mst <= RD;
if (byte_cnt = 3) then
state_i2c_mst <= STO;
end if;
end if;
when RD_ACK =>
cnt <= cnt + 1;
if (cnt = 7) then
byte_cnt <= byte_cnt + 1;
rcvd <= mst_dat_out & rcvd(31 downto 8);
mst_ack <= '0';
state_i2c_mst <= RD;
if (byte_cnt = 3) then
state_i2c_mst <= STO;
end if;
end if;
when WR =>
mst_wr <= '1';
mst_dat_in <= send(7 downto 0);
if (mst_cmd_ack = '1') then
mst_wr <= '0';
state_i2c_mst <= WR_ACK;
end if;
when WR_ACK =>
cnt <= cnt + 1;
if (cnt = 7) then
if (ack_fr_slv = '0') then
byte_cnt <= byte_cnt + 1;
send <= x"00" & send(31 downto 8);
state_i2c_mst <= WR;
if (byte_cnt = 3) then
state_i2c_mst <= STO;
end if;
else
state_i2c_mst <= ERR;
end if;
end if;
when STO =>
mst_sto <= '1';
if (mst_cmd_ack = '1') then
mst_sto <= '0';
state_i2c_mst <= IDLE;
end if;
when ERR =>
if (once) then
report("Error!");
once <= false;
end if;
when others =>
state_i2c_mst <= ERR;
end case;
end if;
end if;
end process p_mst_fsm;
--------------------------------------------------------------------------
-- Process to "stimulate" the master FSM above
--------------------------------------------------------------------------
p_stim_mst_fsm : process (rst_n, inv_flag_n, state_i2c_mst)
begin
if (rst_n = '0') then
mst_fsm_start <= '0';
mst_fsm_op <= '0';
slv_addr <= "1011110";
adr <= (others => '0');
buf_byte_cnt <= 0;
elsif (not inv_flag_n) and (state_i2c_mst = IDLE) then
mst_fsm_start <= '1';
mst_fsm_op <= '1';
buf_byte_cnt <= buf_byte_cnt + 1;
case buf_byte_cnt is
when 0 =>
adr(11 downto 0) <= x"030";
when 1 =>
adr(11 downto 0) <= x"034";
when 2 =>
adr(11 downto 0) <= x"038";
when 3 =>
adr(11 downto 0) <= x"02c";
buf_byte_cnt <= 0;
when others =>
buf_byte_cnt <= 0;
end case;
else
mst_fsm_start <= '0';
end if;
end process p_stim_mst_fsm;
-- cmp_master : i2c_master_byte_ctrl
-- port map
-- (
-- clk => clk_20,
-- rst => rst,
-- nReset => rst_n,
-- ena => '1',
-- clk_cnt => x"0027",
-- -- input signals
-- start => mst_sta,
-- stop => mst_sto,
-- read => mst_rd,
-- write => mst_wr,
-- ack_in => mst_ack,
-- din => mst_dat_in,
-- -- output signals
-- cmd_ack => mst_cmd_ack,
-- ack_out => ack_fr_slv,
-- i2c_busy => open,
-- i2c_al => open,
-- dout => mst_dat_out,
-- -- i2c lines
-- scl_i => scl,
-- scl_o => scl_fr_mst,
-- scl_oen => scl_en_mst,
-- sda_i => sda,
-- sda_o => sda_fr_mst,
-- sda_oen => sda_en_mst
-- );
-- -- Then, the tri-state_i2c_mst buffers on the line
-- mscl(0) <= scl_fr_mst when (scl_en_mst = '0') else
-- '1';
-- msda(0) <= sda_fr_mst when (sda_en_mst = '0') else
-- '1';
-- --------------------------------------------------------------------------
-- -- Bus model instantiation and connection to master and slaves
-- --------------------------------------------------------------------------
-- cmp_i2c_bus : i2c_bus_model
-- generic map
-- (
-- g_nr_masters => c_nr_masters,
-- g_nr_slaves => c_nr_slaves
-- )
-- port map
-- (
-- mscl_i => mscl,
-- msda_i => msda,
-- sscl_i => sscl,
-- ssda_i => ssda,
-- scl_o => scl,
-- sda_o => sda
-- );
-- --------------------------------------------------------------------------
-- -- This FSM controls the signals to the master component to implement the I2C
-- -- protocol defined together with ELMA. The FSM is controlled by the
-- -- stimuli process below
-- --------------------------------------------------------------------------
-- p_mst_fsm : process (clk_20) is
-- begin
-- if rising_edge(clk_20) then
-- if (rst_n = '0') then
-- state_i2c_mst <= IDLE;
-- mst_sta <= '0';
-- mst_wr <= '0';
-- mst_sto <= '0';
-- mst_rd <= '0';
-- mst_dat_in <= (others => '0');
-- mst_ack <= '0';
-- cnt <= (others => '0');
-- once <= true;
-- byte_cnt <= (others => '0');
-- rcvd <= (others => '0');
-- send <= (others => '0');
-- else
-- case state_i2c_mst is
-- when IDLE =>
-- if (mst_fsm_start = '1') then
-- state_i2c_mst <= I2C_ADDR;
-- send <= std_logic_vector(send_val);
-- end if;
-- when I2C_ADDR =>
-- mst_sta <= '1';
-- mst_wr <= '1';
-- mst_dat_in <= slv_addr & '0';
-- if (mst_cmd_ack = '1') then
-- mst_sta <= '0';
-- mst_wr <= '0';
-- state_i2c_mst <= I2C_ADDR_ACK;
-- end if;
-- when I2C_ADDR_ACK =>
-- cnt <= cnt + 1;
-- if (cnt = 7) then
-- if (ack_fr_slv = '0') then
-- state_i2c_mst <= WB_ADDR_B0;
-- else
-- state_i2c_mst <= ERR;
-- end if;
-- end if;
-- when WB_ADDR_B0 =>
-- mst_wr <= '1';
-- mst_dat_in <= adr(15 downto 8);
-- if (mst_cmd_ack = '1') then
-- mst_wr <= '0';
-- state_i2c_mst <= WB_ADDR_B0_ACK;
-- end if;
-- when WB_ADDR_B0_ACK =>
-- cnt <= cnt + 1;
-- if (cnt = 7) then
-- if (ack_fr_slv = '0') then
-- state_i2c_mst <= WB_ADDR_B1;
-- else
-- state_i2c_mst <= ERR;
-- end if;
-- end if;
-- when WB_ADDR_B1 =>
-- mst_wr <= '1';
-- mst_dat_in <= adr(7 downto 0);
-- if (mst_cmd_ack = '1') then
-- mst_wr <= '0';
-- state_i2c_mst <= WB_ADDR_B1_ACK;
-- end if;
-- when WB_ADDR_B1_ACK =>
-- cnt <= cnt + 1;
-- if (cnt = 7) then
-- if (ack_fr_slv = '0') then
-- state_i2c_mst <= ST_OP;
-- else
-- state_i2c_mst <= ERR;
-- end if;
-- end if;
-- when ST_OP =>
-- if (mst_fsm_op = '1') then
-- state_i2c_mst <= RD_RESTART;
-- else
-- state_i2c_mst <= WR;
-- end if;
-- when RD_RESTART =>
-- mst_wr <= '1';
-- mst_dat_in <= slv_addr & '1';
-- mst_sta <= '1';
-- if (mst_cmd_ack = '1') then
-- mst_sta <= '0';
-- mst_wr <= '0';
-- state_i2c_mst <= RD_RESTART_ACK;
-- end if;
-- when RD_RESTART_ACK =>
-- cnt <= cnt + 1;
-- if (cnt = 7) then
-- if (ack_fr_slv = '0') then
-- state_i2c_mst <= RD;
-- else
-- state_i2c_mst <= ERR;
-- end if;
-- end if;
-- when RD =>
-- mst_rd <= '1';
-- mst_ack <= '0';
-- if (byte_cnt = 3) then
-- mst_ack <= '1';
-- end if;
-- if (mst_cmd_ack = '1') then
-- mst_rd <= '0';
-- byte_cnt <= byte_cnt + 1;
-- rcvd <= mst_dat_out & rcvd(31 downto 8);
-- mst_ack <= '0';
-- state_i2c_mst <= RD;
-- if (byte_cnt = 3) then
-- state_i2c_mst <= STO;
-- end if;
-- end if;
-- when RD_ACK =>
-- cnt <= cnt + 1;
-- if (cnt = 7) then
-- byte_cnt <= byte_cnt + 1;
-- rcvd <= mst_dat_out & rcvd(31 downto 8);
-- mst_ack <= '0';
-- state_i2c_mst <= RD;
-- if (byte_cnt = 3) then
-- state_i2c_mst <= STO;
-- end if;
-- end if;
-- when WR =>
-- mst_wr <= '1';
-- mst_dat_in <= send(7 downto 0);
-- if (mst_cmd_ack = '1') then
-- mst_wr <= '0';
-- state_i2c_mst <= WR_ACK;
-- end if;
-- when WR_ACK =>
-- cnt <= cnt + 1;
-- if (cnt = 7) then
-- if (ack_fr_slv = '0') then
-- byte_cnt <= byte_cnt + 1;
-- send <= x"00" & send(31 downto 8);
-- state_i2c_mst <= WR;
-- if (byte_cnt = 3) then
-- state_i2c_mst <= STO;
-- end if;
-- else
-- state_i2c_mst <= ERR;
-- end if;
-- end if;
-- when STO =>
-- mst_sto <= '1';
-- if (mst_cmd_ack = '1') then
-- mst_sto <= '0';
-- state_i2c_mst <= IDLE;
-- end if;
-- when ERR =>
-- if (once) then
-- report("Error!");
-- once <= false;
-- end if;
-- when others =>
-- state_i2c_mst <= ERR;
-- end case;
-- end if;
-- end if;
-- end process p_mst_fsm;
-- --------------------------------------------------------------------------
-- -- Process to "stimulate" the master FSM above
-- --------------------------------------------------------------------------
-- p_stim_mst_fsm : process (rst_n, inv_flag_n, state_i2c_mst)
-- begin
-- if (rst_n = '0') then
-- mst_fsm_start <= '0';
-- mst_fsm_op <= '0';
-- slv_addr <= "1011110";
-- adr <= (others => '0');
-- buf_byte_cnt <= 0;
-- elsif (not inv_flag_n) and (state_i2c_mst = IDLE) then
-- mst_fsm_start <= '1';
-- mst_fsm_op <= '1';
-- buf_byte_cnt <= buf_byte_cnt + 1;
-- case buf_byte_cnt is
-- when 0 =>
-- adr(11 downto 0) <= x"030";
-- when 1 =>
-- adr(11 downto 0) <= x"034";
-- when 2 =>
-- adr(11 downto 0) <= x"038";
-- when 3 =>
-- adr(11 downto 0) <= x"02c";
-- buf_byte_cnt <= 0;
-- when others =>
-- buf_byte_cnt <= 0;
-- end case;
-- else
-- mst_fsm_start <= '0';
-- end if;
-- end process p_stim_mst_fsm;
end architecture behav;
--==============================================================================
......
syn/Release/iseconfig/conv_ttl_blo.projectmgr
View file @ 1a34f694
......@@ -7,15 +7,16 @@
<ItemView engineview="SynthesisOnly" guiview="Source" compilemode="ManualCompile" >
<ClosedNodes>
<ClosedNodesVersion>2</ClosedNodesVersion>
<ClosedNode>/Automatic `includes</ClosedNode>
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<SelectedItem>G:\Users\d\debouhir\Documents\Projects\CONV-TTL-BlO\repo\conv-ttl-blo-gw\ip_cores\conv-common-gw\ip_cores\general-cores\modules\wishbone\wishbone_pkg.vhd (G:/Users/d/debouhir/Documents/Projects/CONV-TTL-BlO/repo/conv-ttl-blo-gw/ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd)</SelectedItem>
<SelectedItem>C:\Users\debouhir\work\CONV-TTL-BLO\conv-ttl-blo\conv-ttl-blo-gw\ip_cores\conv-common-gw\top\conv_common_gw_pkg.vhd (C:/Users/debouhir/work/CONV-TTL-BLO/conv-ttl-blo/conv-ttl-blo-gw/ip_cores/conv-common-gw/top/conv_common_gw_pkg.vhd)</SelectedItem>
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<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000004fb000000020000000000000000000000000000000064ffffffff0000008100000000000000020000048b0000000100000000000000700000000100000000</ViewHeaderState>
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<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>G:\Users\d\debouhir\Documents\Projects\CONV-TTL-BlO\repo\conv-ttl-blo-gw\ip_cores\conv-common-gw\ip_cores\general-cores\modules\wishbone\wishbone_pkg.vhd (G:/Users/d/debouhir/Documents/Projects/CONV-TTL-BlO/repo/conv-ttl-blo-gw/ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd)</CurrentItem>
<CurrentItem>C:\Users\debouhir\work\CONV-TTL-BLO\conv-ttl-blo\conv-ttl-blo-gw\ip_cores\conv-common-gw\top\conv_common_gw_pkg.vhd (C:/Users/debouhir/work/CONV-TTL-BLO/conv-ttl-blo/conv-ttl-blo-gw/ip_cores/conv-common-gw/top/conv_common_gw_pkg.vhd)</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_UCF" guiview="Process" >
<ClosedNodes>
......@@ -27,7 +28,7 @@
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000000000000000000032e000000010000000100000000000000000000000064ffffffff0000008100000000000000010000032e0000000100000000</ViewHeaderState>
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<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem/>
</ItemView>
......@@ -36,13 +37,13 @@
<ClosedNodesVersion>1</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems>
<SelectedItem>C:\Users\debouhir\work\CONV-TTL-BLO\repo\conv-ttl-blo-gw\sim\Release\burst_ctrl_tb.vhd</SelectedItem>
<SelectedItem>C:\Users\debouhir\work\CONV-TTL-BLO\conv-ttl-blo\conv-ttl-blo-gw\sim\Release\burst_ctrl_tb.vhd</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >106</ScrollbarPosition>
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<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>C:\Users\debouhir\work\CONV-TTL-BLO\repo\conv-ttl-blo-gw\sim\Release\burst_ctrl_tb.vhd</CurrentItem>
<CurrentItem>C:\Users\debouhir\work\CONV-TTL-BLO\conv-ttl-blo\conv-ttl-blo-gw\sim\Release\burst_ctrl_tb.vhd</CurrentItem>
</ItemView>
<ItemView guiview="Library" >
<ClosedNodes>
......@@ -60,7 +61,6 @@
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>Configure Target Device</ClosedNode>
<ClosedNode>Design Utilities</ClosedNode>
<ClosedNode>Implement Design</ClosedNode>
<ClosedNode>Implement Design/Map</ClosedNode>
<ClosedNode>Implement Design/Place &amp; Route</ClosedNode>
<ClosedNode>Implement Design/Translate</ClosedNode>
......@@ -71,7 +71,7 @@
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<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
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<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
</ItemView>
......@@ -140,19 +140,24 @@
<ClosedNode>/xwb_xilinx_fpga_loader - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|platform|xilinx|wb_xilinx_fpga_loader|xwb_xilinx_fpga_loader.vhd</ClosedNode>
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<SelectedItem>conv_ttl_blo - arch (C:/Users/debouhir/work/CONV-TTL-BLO/repo/conv-ttl-blo-gw/top/Release/conv_ttl_blo.vhd)</SelectedItem>
<SelectedItem>conv_ttl_blo</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
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<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>conv_ttl_blo - arch (C:/Users/debouhir/work/CONV-TTL-BLO/repo/conv-ttl-blo-gw/top/Release/conv_ttl_blo.vhd)</CurrentItem>
<CurrentItem>conv_ttl_blo</CurrentItem>
</ItemView>
<ItemView engineview="BehavioralSim" guiview="Source" compilemode="AutoCompile" >
<ClosedNodes>
<ClosedNodesVersion>2</ClosedNodesVersion>
<ClosedNode>/Automatic `includes</ClosedNode>
<ClosedNode>/conv_common_gw - arch G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|top|conv_common_gw.vhd</ClosedNode>
<ClosedNode>/conv_ttl_blo - arch C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|top|Release|conv_ttl_blo.vhd</ClosedNode>
<ClosedNode>/conv_ttl_blo - arch C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|top|Release|conv_ttl_blo.vhd/cmp_conv_common - conv_common_gw - arch/cmp_multiboot - xwb_xil_multiboot - struct</ClosedNode>
<ClosedNode>/conv_ttl_blo - arch C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|top|Release|conv_ttl_blo.vhd/cmp_conv_common - conv_common_gw - arch/cmp_pulse_timetag - conv_pulse_timetag - behav</ClosedNode>
<ClosedNode>/conv_ttl_blo - arch C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|top|Release|conv_ttl_blo.vhd/cmp_conv_common - conv_common_gw - arch/cmp_ring_buf - conv_ring_buf - behav</ClosedNode>
<ClosedNode>/conv_ttl_blo - arch C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|top|Release|conv_ttl_blo.vhd/cmp_conv_common - conv_common_gw - arch/cmp_wb_crossbar - xwb_sdb_crossbar - rtl</ClosedNode>
<ClosedNode>/conv_ttl_blo - arch C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|top|Release|conv_ttl_blo.vhd</ClosedNode>
<ClosedNode>/conv_ttl_blo - arch G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|top|Release|conv_ttl_blo.vhd</ClosedNode>
<ClosedNode>/conv_ttl_blo - arch G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|top|Release|conv_ttl_blo.vhd/cmp_conv_common - conv_common_gw - arch/cmp_i2c_bridge - wb_i2c_bridge - behav</ClosedNode>
......@@ -160,14 +165,20 @@
<ClosedNode>/conv_ttl_blo - arch G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|top|Release|conv_ttl_blo.vhd/cmp_conv_common - conv_common_gw - arch/cmp_pulse_timetag - conv_pulse_timetag - behav</ClosedNode>
<ClosedNode>/conv_ttl_blo - arch G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|top|Release|conv_ttl_blo.vhd/cmp_conv_common - conv_common_gw - arch/cmp_ring_buf - conv_ring_buf - behav</ClosedNode>
<ClosedNode>/conv_ttl_blo - arch G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|top|Release|conv_ttl_blo.vhd/cmp_conv_common - conv_common_gw - arch/cmp_wb_crossbar - xwb_sdb_crossbar - rtl</ClosedNode>
<ClosedNode>/gc_frequency_meter - behavioral C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|common|gc_frequency_meter.vhd</ClosedNode>
<ClosedNode>/gc_frequency_meter - behavioral C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|common|gc_frequency_meter.vhd</ClosedNode>
<ClosedNode>/gc_frequency_meter - behavioral G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|common|gc_frequency_meter.vhd</ClosedNode>
<ClosedNode>/gc_moving_average - rtl C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|common|gc_moving_average.vhd</ClosedNode>
<ClosedNode>/gc_moving_average - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|common|gc_moving_average.vhd</ClosedNode>
<ClosedNode>/gc_moving_average - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|common|gc_moving_average.vhd</ClosedNode>
<ClosedNode>/gc_rr_arbiter - rtl C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|common|gc_rr_arbiter.vhd</ClosedNode>
<ClosedNode>/gc_rr_arbiter - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|common|gc_rr_arbiter.vhd</ClosedNode>
<ClosedNode>/gc_rr_arbiter - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|common|gc_rr_arbiter.vhd</ClosedNode>
<ClosedNode>/generic_shiftreg_fifo - rtl C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|genrams|generic|generic_shiftreg_fifo.vhd</ClosedNode>
<ClosedNode>/generic_shiftreg_fifo - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|genrams|generic_shiftreg_fifo.vhd</ClosedNode>
<ClosedNode>/generic_shiftreg_fifo - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|genrams|generic|generic_shiftreg_fifo.vhd</ClosedNode>
<ClosedNode>/testbench - behav C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|sim|Release|testbenchv4.vhd/cmp_dut - conv_ttl_blo - arch</ClosedNode>
<ClosedNode>/testbench - behav C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|sim|Release|testbenchv4.vhd/cmp_master - i2c_master_byte_ctrl - structural</ClosedNode>
<ClosedNode>/testbench - behav G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|sim|Release|testbenchv4.vhd/cmp_dut - conv_ttl_blo - arch/cmp_conv_common - conv_common_gw - arch/cmp_i2c_bridge - wb_i2c_bridge - behav</ClosedNode>
<ClosedNode>/testbench - behav G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|sim|Release|testbenchv4.vhd/cmp_dut - conv_ttl_blo - arch/cmp_conv_common - conv_common_gw - arch/cmp_multiboot - xwb_xil_multiboot - struct</ClosedNode>
<ClosedNode>/testbench - behav G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|sim|Release|testbenchv4.vhd/cmp_dut - conv_ttl_blo - arch/cmp_conv_common - conv_common_gw - arch/cmp_onewire_master - wb_onewire_master - rtl</ClosedNode>
......@@ -175,55 +186,75 @@
<ClosedNode>/testbench - behav G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|sim|Release|testbenchv4.vhd/cmp_dut - conv_ttl_blo - arch/cmp_conv_common - conv_common_gw - arch/cmp_ring_buf - conv_ring_buf - behav</ClosedNode>
<ClosedNode>/testbench - behav G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|sim|Release|testbenchv4.vhd/cmp_dut - conv_ttl_blo - arch/cmp_conv_common - conv_common_gw - arch/cmp_wb_crossbar - xwb_sdb_crossbar - rtl</ClosedNode>
<ClosedNode>/testbench - behav G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|sim|Release|testbenchv4.vhd/cmp_master - i2c_master_byte_ctrl - structural</ClosedNode>
<ClosedNode>/wb_irq_lm32 - rtl C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_irq|wb_irq_lm32.vhd</ClosedNode>
<ClosedNode>/wb_irq_lm32 - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_irq|wb_irq_lm32.vhd</ClosedNode>
<ClosedNode>/wb_irq_lm32 - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_irq|wb_irq_lm32.vhd</ClosedNode>
<ClosedNode>/wb_irq_master - behavioral C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_irq|wb_irq_master.vhd</ClosedNode>
<ClosedNode>/wb_irq_master - behavioral C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_irq|wb_irq_master.vhd</ClosedNode>
<ClosedNode>/wb_irq_master - behavioral G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_irq|wb_irq_master.vhd</ClosedNode>
<ClosedNode>/wb_irq_timer - behavioral C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_irq|wb_irq_timer.vhd</ClosedNode>
<ClosedNode>/wb_irq_timer - behavioral C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_irq|wb_irq_timer.vhd</ClosedNode>
<ClosedNode>/wb_irq_timer - behavioral G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_irq|wb_irq_timer.vhd</ClosedNode>
<ClosedNode>/wb_serial_lcd - rtl C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_serial_lcd|wb_serial_lcd.vhd</ClosedNode>
<ClosedNode>/wb_serial_lcd - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_serial_lcd|wb_serial_lcd.vhd</ClosedNode>
<ClosedNode>/wb_serial_lcd - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_serial_lcd|wb_serial_lcd.vhd</ClosedNode>
<ClosedNode>/wb_spi_flash - rtl C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_spi_flash|wb_spi_flash.vhd</ClosedNode>
<ClosedNode>/wb_spi_flash - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_spi_flash|wb_spi_flash.vhd</ClosedNode>
<ClosedNode>/wb_spi_flash - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_spi_flash|wb_spi_flash.vhd</ClosedNode>
<ClosedNode>/wbgen2_dpssram - syn C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wbgen2|wbgen2_dpssram.vhd</ClosedNode>
<ClosedNode>/wbgen2_dpssram - syn C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wbgen2|wbgen2_dpssram.vhd</ClosedNode>
<ClosedNode>/wbgen2_dpssram - syn G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wbgen2|wbgen2_dpssram.vhd</ClosedNode>
<ClosedNode>/wbgen2_fifo_async - rtl C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wbgen2|wbgen2_fifo_async.vhd</ClosedNode>
<ClosedNode>/wbgen2_fifo_async - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wbgen2|wbgen2_fifo_async.vhd</ClosedNode>
<ClosedNode>/wbgen2_fifo_async - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wbgen2|wbgen2_fifo_async.vhd</ClosedNode>
<ClosedNode>/xwb_async_bridge - wrapper C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_async_bridge|xwb_async_bridge.vhd</ClosedNode>
<ClosedNode>/xwb_async_bridge - wrapper C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_async_bridge|xwb_async_bridge.vhd</ClosedNode>
<ClosedNode>/xwb_async_bridge - wrapper G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_async_bridge|xwb_async_bridge.vhd</ClosedNode>
<ClosedNode>/xwb_bus_fanout - rtl C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_bus_fanout|xwb_bus_fanout.vhd</ClosedNode>
<ClosedNode>/xwb_bus_fanout - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_bus_fanout|xwb_bus_fanout.vhd</ClosedNode>
<ClosedNode>/xwb_bus_fanout - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_bus_fanout|xwb_bus_fanout.vhd</ClosedNode>
<ClosedNode>/xwb_dpram - struct C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_dpram|xwb_dpram.vhd</ClosedNode>
<ClosedNode>/xwb_dpram - struct C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_dpram|xwb_dpram.vhd</ClosedNode>
<ClosedNode>/xwb_dpram - struct G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_dpram|xwb_dpram.vhd</ClosedNode>
<ClosedNode>/xwb_gpio_port - rtl C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_gpio_port|xwb_gpio_port.vhd</ClosedNode>
<ClosedNode>/xwb_gpio_port - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_gpio_port|xwb_gpio_port.vhd</ClosedNode>
<ClosedNode>/xwb_gpio_port - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_gpio_port|xwb_gpio_port.vhd</ClosedNode>
<ClosedNode>/xwb_i2c_master - rtl C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_i2c_master|xwb_i2c_master.vhd</ClosedNode>
<ClosedNode>/xwb_i2c_master - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_i2c_master|xwb_i2c_master.vhd</ClosedNode>
<ClosedNode>/xwb_i2c_master - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_i2c_master|xwb_i2c_master.vhd</ClosedNode>
<ClosedNode>/xwb_onewire_master - rtl C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_onewire_master|xwb_onewire_master.vhd</ClosedNode>
<ClosedNode>/xwb_onewire_master - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_onewire_master|xwb_onewire_master.vhd</ClosedNode>
<ClosedNode>/xwb_onewire_master - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_onewire_master|xwb_onewire_master.vhd</ClosedNode>
<ClosedNode>/xwb_simple_pwm - wrapper C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_simple_pwm|xwb_simple_pwm.vhd</ClosedNode>
<ClosedNode>/xwb_simple_pwm - wrapper C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_simple_pwm|xwb_simple_pwm.vhd</ClosedNode>
<ClosedNode>/xwb_simple_pwm - wrapper G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_simple_pwm|xwb_simple_pwm.vhd</ClosedNode>
<ClosedNode>/xwb_simple_uart - rtl C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_uart|xwb_simple_uart.vhd</ClosedNode>
<ClosedNode>/xwb_simple_uart - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_uart|xwb_simple_uart.vhd</ClosedNode>
<ClosedNode>/xwb_simple_uart - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_uart|xwb_simple_uart.vhd</ClosedNode>
<ClosedNode>/xwb_spi - rtl C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_spi|xwb_spi.vhd</ClosedNode>
<ClosedNode>/xwb_spi - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_spi|xwb_spi.vhd</ClosedNode>
<ClosedNode>/xwb_spi - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_spi|xwb_spi.vhd</ClosedNode>
<ClosedNode>/xwb_streamer - rtl C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_dma|xwb_streamer.vhd</ClosedNode>
<ClosedNode>/xwb_streamer - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_dma|xwb_streamer.vhd</ClosedNode>
<ClosedNode>/xwb_streamer - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_dma|xwb_streamer.vhd</ClosedNode>
<ClosedNode>/xwb_tics - rtl C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_simple_timer|xwb_tics.vhd</ClosedNode>
<ClosedNode>/xwb_tics - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_simple_timer|xwb_tics.vhd</ClosedNode>
<ClosedNode>/xwb_tics - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_simple_timer|xwb_tics.vhd</ClosedNode>
<ClosedNode>/xwb_vic - wrapper C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_vic|xwb_vic.vhd</ClosedNode>
<ClosedNode>/xwb_vic - wrapper C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_vic|xwb_vic.vhd</ClosedNode>
<ClosedNode>/xwb_vic - wrapper G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_vic|xwb_vic.vhd</ClosedNode>
<ClosedNode>/xwb_xilinx_fpga_loader - rtl C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|platform|xilinx|wb_xilinx_fpga_loader|xwb_xilinx_fpga_loader.vhd</ClosedNode>
<ClosedNode>/xwb_xilinx_fpga_loader - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|platform|xilinx|wb_xilinx_fpga_loader|xwb_xilinx_fpga_loader.vhd</ClosedNode>
<ClosedNode>/xwb_xilinx_fpga_loader - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|platform|xilinx|wb_xilinx_fpga_loader|xwb_xilinx_fpga_loader.vhd</ClosedNode>
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......@@ -231,39 +262,39 @@
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......
syn/Release/iseconfig/conv_ttl_blo.xreport
View file @ 1a34f694
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<report-views version="2.0" >
<header>
<DateModified>2016-11-10T12:17:10</DateModified>
<DateModified>2017-03-07T13:10:09</DateModified>
<ModuleName>conv_ttl_blo</ModuleName>
<SummaryTimeStamp>2016-10-20T09:26:48</SummaryTimeStamp>
<SavedFilePath>C:/Users/debouhir/work/CONV-TTL-BLO/repo/conv-ttl-blo-gw/syn/Release/iseconfig/conv_ttl_blo.xreport</SavedFilePath>
<ImplementationReportsDirectory>C:/Users/debouhir/work/CONV-TTL-BLO/repo/conv-ttl-blo-gw/syn/Release\</ImplementationReportsDirectory>
<DateInitialized>2016-10-20T14:06:58</DateInitialized>
<SummaryTimeStamp>2017-03-07T09:41:56</SummaryTimeStamp>
<ImplementationReportsDirectory>C:/Users/debouhir/work/CONV-TTL-BLO/conv-ttl-blo/conv-ttl-blo-gw/syn/Release\</ImplementationReportsDirectory>
<DateInitialized>2017-02-10T11:32:52</DateInitialized>
<SavedFilePath>C:/Users/debouhir/work/CONV-TTL-BLO/conv-ttl-blo/conv-ttl-blo-gw/syn/Release/iseconfig/conv_ttl_blo.xreport</SavedFilePath>
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<view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="conv_ttl_blo.ptwx" showConstraints="0" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
<view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="conv_ttl_blo_par.xrpt" showConstraints="0" label="Pinout Report" />
<view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="conv_ttl_blo_par.xrpt" showConstraints="0" label="Clock Report" />
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="conv_ttl_blo.twx" label="Static Timing" />
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="conv_ttl_blo_html/fit/report.htm" label="CPLD Fitter Report" />
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="conv_ttl_blo_html/tim/report.htm" label="CPLD Timing Report" />
</viewgroup>
<viewgroup label="XPS Errors and Warnings" >
<view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
......@@ -38,7 +38,7 @@
<view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
<view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
<view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
<view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="testbench.log" label="System Log File" />
<view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="conv_ttl_blo.log" label="System Log File" />
</viewgroup>
<viewgroup label="Errors and Warnings" >
<view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
......@@ -54,7 +54,7 @@
<view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
</viewgroup>
<viewgroup label="Detailed Reports" >
<view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="testbench.syr" label="Synthesis Report" >
<view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="conv_ttl_blo.syr" label="Synthesis Report" >
<toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
<toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " />
<toc-item title="HDL Compilation" target=" HDL Compilation " />
......@@ -80,15 +80,15 @@
<toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
<toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
</view>
<view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="testbench.srr" label="Synplify Report" />
<view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="testbench.prec_log" label="Precision Report" />
<view inputState="Synthesized" program="ngdbuild" type="Report" file="testbench.bld" label="Translation Report" >
<view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="conv_ttl_blo.srr" label="Synplify Report" />
<view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="conv_ttl_blo.prec_log" label="Precision Report" />
<view inputState="Synthesized" program="ngdbuild" type="Report" file="conv_ttl_blo.bld" label="Translation Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Command Line" target="Command Line:" />
<toc-item title="Partition Status" target="Partition Implementation Status" />
<toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
</view>
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="testbench_map.mrp" label="Map Report" >
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="conv_ttl_blo_map.mrp" label="Map Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
<toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
<toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
......@@ -104,7 +104,7 @@
<toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
<toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="testbench.par" label="Place and Route Report" >
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="conv_ttl_blo.par" label="Place and Route Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Device Utilization" target="Device Utilization Summary:" />
<toc-item title="Router Information" target="Starting Router" />
......@@ -113,7 +113,7 @@
<toc-item title="Timing Results" target="Timing Score:" />
<toc-item title="Final Summary" target="Peak Memory Usage:" />
</view>
<view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="testbench.twr" label="Post-PAR Static Timing Report" >
<view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="conv_ttl_blo.twr" label="Post-PAR Static Timing Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Timing Report Description" target="Device,package,speed:" />
<toc-item title="Informational Messages" target="INFO:" />
......@@ -124,22 +124,22 @@
<toc-item title="Timing Summary" target="Timing summary:" />
<toc-item title="Trace Settings" target="Trace Settings:" />
</view>
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="testbench.rpt" label="CPLD Fitter Report (Text)" >
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="conv_ttl_blo.rpt" label="CPLD Fitter Report (Text)" >
<toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
<toc-item title="Resources Summary" target="** Mapped Resource Summary **" />
<toc-item title="Pin Resources" target="** Pin Resources **" />
<toc-item title="Global Resources" target="** Global Control Resources **" />
</view>
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="testbench.tim" label="CPLD Timing Report (Text)" >
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="conv_ttl_blo.tim" label="CPLD Timing Report (Text)" >
<toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
<toc-item title="Performance Summary" target="Performance Summary:" />
</view>
<view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="testbench.pwr" label="Power Report" >
<view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="conv_ttl_blo.pwr" label="Power Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Power summary" target="Power summary" />
<toc-item title="Thermal summary" target="Thermal summary" />
</view>
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="testbench.bgn" label="Bitgen Report" >
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="conv_ttl_blo.bgn" label="Bitgen Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
<toc-item title="Final Summary" target="DRC detected" />
......@@ -147,20 +147,20 @@
</viewgroup>
<viewgroup label="Secondary Reports" >
<view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
<view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/testbench_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
<view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/conv_ttl_blo_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/testbench_translate.nlf" label="Post-Translate Simulation Model Report" >
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/conv_ttl_blo_translate.nlf" label="Post-Translate Simulation Model Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="testbench_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="testbench_map.map" label="Map Log File" >
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="conv_ttl_blo_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="conv_ttl_blo_map.map" label="Map Log File" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
<toc-item title="Design Information" target="Design Information" />
<toc-item title="Design Summary" target="Design Summary" />
</view>
<view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
<view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench_preroute.twr" label="Post-Map Static Timing Report" >
<view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="conv_ttl_blo_preroute.twr" label="Post-Map Static Timing Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Timing Report Description" target="Device,package,speed:" />
<toc-item title="Informational Messages" target="INFO:" />
......@@ -171,43 +171,43 @@
<toc-item title="Timing Summary" target="Timing summary:" />
<toc-item title="Trace Settings" target="Trace Settings:" />
</view>
<view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/testbench_map.nlf" label="Post-Map Simulation Model Report" />
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench_map.psr" label="Physical Synthesis Report" >
<view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/conv_ttl_blo_map.nlf" label="Post-Map Simulation Model Report" />
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="conv_ttl_blo_map.psr" label="Physical Synthesis Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="testbench_pad.txt" label="Pad Report" >
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="conv_ttl_blo_pad.txt" label="Pad Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="testbench.unroutes" label="Unroutes Report" >
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="conv_ttl_blo.unroutes" label="Unroutes Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench_preroute.tsi" label="Post-Map Constraints Interaction Report" >
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="conv_ttl_blo_preroute.tsi" label="Post-Map Constraints Interaction Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench.grf" label="Guide Results Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench.dly" label="Asynchronous Delay Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench.clk_rgn" label="Clock Region Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench.tsi" label="Post-Place and Route Constraints Interaction Report" >
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="conv_ttl_blo.grf" label="Guide Results Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="conv_ttl_blo.dly" label="Asynchronous Delay Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="conv_ttl_blo.clk_rgn" label="Clock Region Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="conv_ttl_blo.tsi" label="Post-Place and Route Constraints Interaction Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="testbench_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
<view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/testbench_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="testbench_sta.nlf" label="Primetime Netlist Report" >
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="conv_ttl_blo_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
<view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/conv_ttl_blo_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="conv_ttl_blo_sta.nlf" label="Primetime Netlist Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="testbench.ibs" label="IBIS Model" >
<view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="conv_ttl_blo.ibs" label="IBIS Model" >
<toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
<toc-item title="Component" target="Component " />
</view>
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench.lck" label="Back-annotate Pin Report" >
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="conv_ttl_blo.lck" label="Back-annotate Pin Report" >
<toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
<toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
</view>
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench.lpc" label="Locked Pin Constraints" >
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="conv_ttl_blo.lpc" label="Locked Pin Constraints" >
<toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
<toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
</view>
<view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/testbench_timesim.nlf" label="Post-Fit Simulation Model Report" />
<view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/conv_ttl_blo_timesim.nlf" label="Post-Fit Simulation Model Report" />
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
</viewgroup>
......
syn/Release/testbench_envsettings.html
View file @ 1a34f694
......@@ -22,7 +22,7 @@
</tr>
<tr>
<td>Path</td>
<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files (x86)\Skype\Phone\;<br>C:\EDA\Cadence\SPB_166\tools\pspice;<br>C:\EDA\Cadence\SPB_166\tools\capture;<br>C:\EDA\Cadence\SPB_166\tools\bin;<br>C:\EDA\Cadence\SPB_166\openaccess\bin\win32\opt;<br>C:\EDA\Cadence\SPB_166\tools\fet\bin;<br>C:\EDA\Cadence\SPB_166\tools\pcb\bin;<br>C:\EDA\Cadence\SPB_166\tools\specctra\bin;<br>C:\EDA\Cadence\SPB_166\tools\libutil\bin;<br>C:\Program Files\TortoiseGit\bin;<br>C:\Users\debouhir\Documents\MikTex\miktex\bin\;<br>C:\Program Files\wbgen2-bin.tar\bin;<br>C:\Program Files\Git\cmd;<br>C:\modeltech64_10.1c\win64</td>
<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files (x86)\Skype\Phone\;<br>C:\EDA\Cadence\SPB_166\tools\pspice;<br>C:\EDA\Cadence\SPB_166\tools\capture;<br>C:\EDA\Cadence\SPB_166\tools\bin;<br>C:\EDA\Cadence\SPB_166\openaccess\bin\win32\opt;<br>C:\EDA\Cadence\SPB_166\tools\fet\bin;<br>C:\EDA\Cadence\SPB_166\tools\pcb\bin;<br>C:\EDA\Cadence\SPB_166\tools\specctra\bin;<br>C:\EDA\Cadence\SPB_166\tools\libutil\bin;<br>C:\Program Files\TortoiseGit\bin;<br>C:\Users\debouhir\Documents\MikTex\miktex\bin\;<br>C:\Program Files\wbgen2-bin.tar\bin;<br>C:\Program Files\Git\cmd;<br>C:\VXIPNP\WinNT\Bin;<br>C:\modeltech64_10.1c\win64</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
......@@ -95,7 +95,7 @@
<tr>
<td>-p</td>
<td>&nbsp;</td>
<td>xc6slx4-3-tqg144</td>
<td>xc6slx45t-3-fgg484</td>
<td>&nbsp;</td>
</tr>
<tr>
......
syn/Release/testbench_summary.html
View file @ 1a34f694
......@@ -7,16 +7,17 @@
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>conv_ttl_blo.xise</TD>
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
<TD ALIGN=LEFT><font color='red'; face='Arial'><b>X </b></font><A HREF_DISABLED='C:/Users/debouhir/work/CONV-TTL-BLO/conv-ttl-blo/conv-ttl-blo-gw/syn/Release\_xmsgs/pn_parser.xmsgs?&DataKey=Error'>1 Error</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>conv_ttl_blo</TD>
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
<TD>New</TD>
<TD>New (Failed)</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc6slx4-3tqg144</TD>
<TD>xc6slx45t-3fgg484</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
......@@ -40,7 +41,10 @@
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
<TD>&nbsp;</TD>
<TD>
<A HREF_DISABLED='C:/Users/debouhir/work/CONV-TTL-BLO/conv-ttl-blo/conv-ttl-blo-gw/syn/Release\testbench_envsettings.html'>
System Settings</A>
</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
<TD>&nbsp;&nbsp;</TD>
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......@@ -71,8 +75,9 @@
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/debouhir/work/CONV-TTL-BLO/conv-ttl-blo/conv-ttl-blo-gw/syn/Release\isim.log'>ISIM Simulator Log</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Tue 7. Feb 16:41:32 2017</TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 11/10/2016 - 12:17:10</center>
<br><center><b>Date Generated:</b> 02/13/2017 - 18:37:49</center>
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\ No newline at end of file
syn/Release/transcript
View file @ 1a34f694
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top/Release/conv_ttl_blo.vhd
View file @ 1a34f694
......@@ -52,6 +52,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
......@@ -82,10 +83,10 @@ entity conv_ttl_blo is
vme_sysreset_n_i : in std_logic;
vme_ga_i : in std_logic_vector(4 downto 0);
vme_gap_i : in std_logic;
-- PCB version recognition
pcbrev_i : in std_logic_vector(5 downto 0);
pcbrev_i : in std_logic_vector(5 downto 0);
-- Channel enable
global_oen_o : out std_logic;
ttl_oen_o : out std_logic;
......@@ -197,9 +198,9 @@ architecture arch of conv_ttl_blo is
-- TTL & RS485 signals
signal rs485_fs : std_logic_vector(c_nr_chans-1 downto 0);
signal pulse_in : std_logic_vector(c_nr_chans-1 downto 0);
signal inv_pulse_in_n : std_logic_vector(c_nr_inv_chans-1 downto 0);
signal inv_pulse_in_n : std_logic_vector(c_nr_inv_chans-1 downto 0);
signal pulse_out : std_logic_vector(c_nr_chans-1 downto 0);
signal inv_pulse_out : std_logic_vector(c_nr_inv_chans-1 downto 0);
signal inv_pulse_out : std_logic_vector(c_nr_inv_chans-1 downto 0);
signal pulse_ttl : std_logic_vector(c_nr_chans-1 downto 0);
signal pulse_blo : std_logic_vector(c_nr_chans-1 downto 0);
signal inhibit_first_pulse : std_logic;
......@@ -207,8 +208,8 @@ architecture arch of conv_ttl_blo is
signal inhibit_cnt : unsigned(10 downto 0);
--Temperature model constantstemp_decre_step_lg
signal temp_decre_step_lg : t_temp_decre_step;
signal temp_decre_step_sh : t_temp_decre_step;
signal temp_decre_step_lg : t_temp_decre_step;
signal temp_decre_step_sh : t_temp_decre_step;
-- Line signals -- for reflection in line status register of conv_common_gw
signal line_ttl : std_logic_vector(c_nr_chans-1 downto 0);
......@@ -217,7 +218,7 @@ architecture arch of conv_ttl_blo is
-- Switch signals (for inverting switch inputs to the common g/w)
signal sw_ttl : std_logic;
signal burst_en_n : std_logic;
signal burst_en_n : std_logic;
signal sw_gp : std_logic_vector(7 downto 0);
signal pgen_duty_cycle_div_lg : natural range 8 to 300;
......@@ -228,7 +229,7 @@ architecture arch of conv_ttl_blo is
-- Channel LED signals
signal led_pulse : std_logic_vector(c_nr_chans-1 downto 0);
signal led_inv_pulse : std_logic_vector(c_nr_inv_chans-1 downto 0);
signal led_inv_pulse : std_logic_vector(c_nr_inv_chans-1 downto 0);
signal led_rear : std_logic_vector(c_nr_chans-1 downto 0);
-- I2C LEDs
......@@ -298,7 +299,7 @@ begin
inhibit_first_pulse <= '1';
elsif (inhibit_first_pulse = '1') then
inhibit_cnt <= inhibit_cnt + 1;
if (inhibit_cnt = 1999) then
if (inhibit_cnt >= 1999 and and_reduce(ttl_n_i)='1') then
inhibit_first_pulse <= '0';
end if;
end if;
......@@ -317,11 +318,7 @@ begin
end if;
end if;
end process;
-- Pulse input valid only after inhibit period is over
pulse_in <= (pulse_ttl or pulse_blo) when (inhibit_first_pulse_d0 = '0') else
(others => '0');
......@@ -335,23 +332,22 @@ begin
-- Switch inputs for reflection in status register
sw_gp <= not sw_gp_n_i;
-- Switch to determine short or long pulse mode.
-- ON switch means SHORT 250ns pulse repetition with max frequency 2MHz
-- OFF switch means LONG 1.2us pulse repetition with max freq ~104kHz
--Note that this burst mode functionality is activated only for PCB v4 or later
--The FPGA
-- Functionality enabled for versions 4 and above
-- when version is below 4 then disable burst functionality
-- burst_en_n <= '0' when pcbrev_i (5 downto 0) >= "010000" else '1';
-- burst_en_n <= '0' when pcbrev_i (5 downto 0) >= "010000" else '1';
--**************************************************************************
--This change code is only used as a hack for v3 boards, which are able to
--**************************************************************************
--This change code is only used as a hack for v3 boards, which are able to
-- support v4 functionality
burst_en_n <= '0' when sw_gp_n_i(6)= '0'
else '1';
--**************************************************************************
burst_en_n <= '0' when sw_gp_n_i(6)= '0'
else '1';
--**************************************************************************
--============================================================================
-- Instantiate common generic gateware for converter boards
--============================================================================
......@@ -360,33 +356,33 @@ begin
(
g_nr_chans => 6,
g_nr_inv_chans => 4,
g_board_id => c_board_id,
g_gwvers => c_gwvers,
g_pgen_fixed_width => true,
g_pgen_pwidth_lg => 24,
g_pgen_pwidth_sh => 5,
g_pgen_pperiod_cont=> 4800,
-- Minimum period supported for 1.2us pulse ~ max freq 104kHz
g_pgen_pperiod_lg => 191,
-- Minimum period supported for 250ns pulse ~ max freq 2MHz
g_pgen_pperiod_sh => 9,
g_pgen_gf_len => 1,
g_temp_decre_step_lg => (0,0,0,0,0,0,0,0,2500,731,220,250,40,85,50,125),
g_temp_decre_step_sh => (0,0, 769, 31, 104, 14, 82, 0 ,0, 0, 0, 0, 0, 0, 0, 0),
g_burstctrl_1_pulse_temp_rise_lg => x"17700", --96000
g_burstctrl_1_pulse_temp_rise_sh => x"01388", --5000
g_burstctrl_max_temp_lg_sh=> x"02540BE400", -- 10^10 --In final release use this value
-- g_burstctrl_max_temp_lg_sh=> x"00000F4240", --10^6 --This value is used to speed up simulation
g_with_pulse_cnt => true,
g_with_pulse_timetag => true,
g_with_man_trig => true,
g_man_trig_pwidth => 24,
g_with_thermometer => true,
g_bicolor_led_columns => c_bicolor_led_cols,
g_bicolor_led_lines => c_bicolor_led_lines
g_nr_chans => 6,
g_nr_inv_chans => 4,
g_board_id => c_board_id,
g_gwvers => c_gwvers,
g_pgen_fixed_width => true,
g_pgen_pwidth_lg => 24,
g_pgen_pwidth_sh => 5,
g_pgen_pperiod_cont => 4800,
-- Minimum period supported for 1.2us pulse ~ max freq 104kHz
g_pgen_pperiod_lg => 191,
-- Minimum period supported for 250ns pulse ~ max freq 2MHz
g_pgen_pperiod_sh => 9,
g_pgen_gf_len => 1,
g_temp_decre_step_lg => (0,0,0,0,0,0,0,0,2500,731,220,250,40,85,50,125),
g_temp_decre_step_sh => (0,0, 769, 31, 104, 14, 82, 0 ,0, 0, 0, 0, 0, 0, 0, 0),
g_burstctrl_1_pulse_temp_rise_lg => x"17700", --96000
g_burstctrl_1_pulse_temp_rise_sh => x"01388", --5000
g_burstctrl_max_temp_lg_sh=> x"02540BE400", -- 10^10 --In final release use this value
-- g_burstctrl_max_temp_lg_sh=> x"00000F4240", --10^6 --This value is used to speed up simulation
g_with_pulse_cnt => true,
g_with_pulse_timetag => true,
g_with_man_trig => true,
g_man_trig_pwidth => 24,
g_with_thermometer => true,
g_bicolor_led_columns => c_bicolor_led_cols,
g_bicolor_led_lines => c_bicolor_led_lines
)
port map
(
......@@ -400,12 +396,16 @@ begin
-- Glitch filter active-low enable signal
gf_en_n_i => sw_gp_n_i(0),
-- Burst mode enable signal. Mode disabled for all versions of board
burst_en_n_i => burst_en_n,
-- Pulse width selection, port low means 250ns, high means 1.2us.
pulse_width_sel_n_i => sw_gp_n_i(1),
-- Burst mode enable signal. Mode disabled for all versions of board
burst_en_n_i => burst_en_n,
-- Pulse width selection, port low means 250ns, high means 1.2us.
-- Switch to determine short or long pulse mode.
-- ON switch means SHORT 250ns pulse repetition with max frequency 2MHz
-- OFF switch means LONG 1.2us pulse repetition with max freq ~104kHz
pulse_width_sel_n_i => sw_gp_n_i(1),
-- Channel enable
global_ch_oen_o => global_oen_o,
......@@ -415,19 +415,19 @@ begin
-- Front panel channels
pulse_i => pulse_in,
pulse_ttl_i => pulse_ttl,
pulse_blo_i => pulse_blo,
pulse_ttl_i => pulse_ttl,
pulse_blo_i => pulse_blo,
pulse_o => pulse_out,
-- Inverted pulse I/O
inv_pulse_i_n => inv_pulse_in_n,
inv_pulse_o => inv_pulse_out,
-- Inverted pulse I/O
inv_pulse_i_n => inv_pulse_in_n,
inv_pulse_o => inv_pulse_out,
-- Channel leds
-- Channel leds
led_pulse_o => led_pulse,
-- inverted channel leds
led_inv_pulse_o => led_inv_pulse,
-- inverted channel leds
led_inv_pulse_o => led_inv_pulse,
-- I2C LED signals -- conect to a bicolor LED of choice
-- led_i2c_o pulses four times on I2C transfer
......@@ -476,7 +476,7 @@ begin
sw_other_i => (others => '0'),
-- PCB Version information
hwvers_i => pcbrev_i,
hwvers_i => pcbrev_i,
-- RTM lines
rtmm_i => rtmm_i,
rtmp_i => rtmp_i,
......
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