Skip to content

C
Conv TTL Blocking - Gateware
Commit 12d56e6a authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
Browse files
Options

Removed old hdl folder 

Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
parent def26966
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 1 addition and 47684 deletions
hdl/.gitattributes deleted 100644 → 0
View file @ def26966
#Ignore generated LaTeX files
*.aux
*.lof
*.log
*.lot
*.out
*.toc
hdl/bicolor_led_ctrl/Manifest.py deleted 100644 → 0
View file @ def26966
files = [
"bicolor_led_ctrl_pkg.vhd",
"bicolor_led_ctrl.vhd"
]
hdl/bicolor_led_ctrl/README deleted 100644 → 0
View file @ def26966
Taken from:
http://www.ohwr.org/projects/svec/repository/revisions/master/show/hdl/top/bicolor_led_test
Revision: 220c7837
hdl/bicolor_led_ctrl/bicolor_led_ctrl.vhd deleted 100644 → 0
View file @ def26966
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Bi-color LED controller
-- http://www.ohwr.org/projects/svec
--------------------------------------------------------------------------------
--
-- unit name: bicolor_led_ctrl
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 11-07-2012
--
-- version: 1.0
--
-- description: Bi-color LED controller. It controls a matrix of bi-color LED.
-- The FPGA ouputs for the columns (C) are connected to buffers
-- and serial resistances and then to the LEDs. The FPGA outputs
-- for lines (L) are connected to tri-state buffers and the to
-- the LEDs. The FPGA outputs for lines output enable (L_OEN) are
-- connected to the output enable of the tri-state buffers.
--
-- Example with three lines and two columns:
--
-- |<refresh period>|
--
-- L1/L2/L3 __|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__
--
-- L1_OEN -----|___________|-----|___________|-----|___________|-----|___________|--
--
-- L2_OEN _____|-----|___________|-----|___________|-----|___________|-----|________
--
-- L3_OEN ___________|-----|___________|-----|___________|-----|___________|-----|__
--
-- Cn __|--|__|--|__|--|_________________|-----------------|--|__|--|__|--|__|--
--
-- LED Ln/Cn OFF | color_1 | color_2 | both_colors |
--
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library work;
use work.bicolor_led_ctrl_pkg.all;
entity bicolor_led_ctrl is
generic(
g_NB_COLUMN : natural := 4;
g_NB_LINE : natural := 2;
g_CLK_FREQ : natural := 125000000; -- in Hz
g_REFRESH_RATE : natural := 250 -- in Hz
);
port
(
rst_n_i : in std_logic;
clk_i : in std_logic;
led_intensity_i : in std_logic_vector(6 downto 0);
led_state_i : in std_logic_vector((g_NB_LINE * g_NB_COLUMN * 2) - 1 downto 0);
column_o : out std_logic_vector(g_NB_COLUMN - 1 downto 0);
line_o : out std_logic_vector(g_NB_LINE - 1 downto 0);
line_oen_o : out std_logic_vector(g_NB_LINE - 1 downto 0)
);
end bicolor_led_ctrl;
architecture rtl of bicolor_led_ctrl is
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant c_REFRESH_CNT_INIT : natural := natural(g_CLK_FREQ/(2 * g_NB_LINE * g_REFRESH_RATE)) - 1;
constant c_REFRESH_CNT_NB_BITS : natural := log2_ceil(c_REFRESH_CNT_INIT);
constant c_LINE_OEN_CNT_NB_BITS : natural := log2_ceil(g_NB_LINE);
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
signal refresh_rate_cnt : unsigned(c_REFRESH_CNT_NB_BITS - 1 downto 0);
signal refresh_rate : std_logic;
signal line_ctrl : std_logic;
signal intensity_ctrl_cnt : unsigned(c_REFRESH_CNT_NB_BITS - 1 downto 0);
signal intensity_ctrl : std_logic;
signal line_oen_cnt : unsigned(c_LINE_OEN_CNT_NB_BITS - 1 downto 0);
signal line_oen : std_logic_vector(2**c_LINE_OEN_CNT_NB_BITS - 1 downto 0);
signal led_state : std_logic_vector((g_NB_LINE * g_NB_COLUMN) -1 downto 0);
begin
------------------------------------------------------------------------------
-- Refresh rate counter
------------------------------------------------------------------------------
p_refresh_rate_cnt : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
refresh_rate_cnt <= (others => '0');
refresh_rate <= '0';
elsif refresh_rate_cnt = 0 then
refresh_rate_cnt <= to_unsigned(c_REFRESH_CNT_INIT, c_REFRESH_CNT_NB_BITS);
refresh_rate <= '1';
else
refresh_rate_cnt <= refresh_rate_cnt - 1;
refresh_rate <= '0';
end if;
end if;
end process p_refresh_rate_cnt;
------------------------------------------------------------------------------
-- Intensity control
------------------------------------------------------------------------------
p_intensity_ctrl_cnt : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
intensity_ctrl_cnt <= (others => '0');
elsif refresh_rate = '1' then
intensity_ctrl_cnt <= to_unsigned(natural(c_REFRESH_CNT_INIT/100) * to_integer(unsigned(led_intensity_i)), c_REFRESH_CNT_NB_BITS);
else
intensity_ctrl_cnt <= intensity_ctrl_cnt - 1;
end if;
end if;
end process p_intensity_ctrl_cnt;
p_intensity_ctrl : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
intensity_ctrl <= '0';
elsif refresh_rate = '1' then
intensity_ctrl <= '1';
elsif intensity_ctrl_cnt = 0 then
intensity_ctrl <= '0';
end if;
end if;
end process p_intensity_ctrl;
------------------------------------------------------------------------------
-- Lines ouput
------------------------------------------------------------------------------
p_line_ctrl : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
line_ctrl <= '0';
elsif refresh_rate = '1' then
line_ctrl <= not(line_ctrl);
end if;
end if;
end process p_line_ctrl;
f_line_o : for I in 0 to g_NB_LINE - 1 generate
line_o(I) <= line_ctrl and intensity_ctrl;
end generate f_line_o;
------------------------------------------------------------------------------
-- Lines output enable
------------------------------------------------------------------------------
p_line_oen_cnt : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
line_oen_cnt <= (others => '0');
elsif line_ctrl = '1' and refresh_rate = '1' then
if line_oen_cnt = 0 then
line_oen_cnt <= to_unsigned(g_NB_LINE - 1, c_LINE_OEN_CNT_NB_BITS);
else
line_oen_cnt <= line_oen_cnt - 1;
end if;
end if;
end if;
end process p_line_oen_cnt;
p_line_oen_decode : process(line_oen_cnt)
variable v_onehot : std_logic_vector((2**line_oen_cnt'length)-1 downto 0);
variable v_index : integer range 0 to (2**line_oen_cnt'length)-1;
begin
v_onehot := (others => '0');
v_index := 0;
for i in line_oen_cnt'range loop
if (line_oen_cnt(i) = '1') then
v_index := 2*v_index+1;
else
v_index := 2*v_index;
end if;
end loop;
v_onehot(v_index) := '1';
line_oen <= v_onehot;
end process p_line_oen_decode;
line_oen_o <= line_oen(line_oen_o'left downto 0);
------------------------------------------------------------------------------
-- Columns output
------------------------------------------------------------------------------
f_led_state : for I in 0 to (g_NB_COLUMN * g_NB_LINE) - 1 generate
led_state(I) <= '0' when led_state_i(2 * I + 1 downto 2 * I) = c_LED_RED else
'1' when led_state_i(2 * I + 1 downto 2 * I) = c_LED_GREEN else
not(line_ctrl and intensity_ctrl) when led_state_i(2 * I + 1 downto 2 * I) = c_LED_RED_GREEN else
(line_ctrl and intensity_ctrl);-- when led_state_i(2 * I + 1 downto 2 * I) = c_LED_OFF else
end generate f_led_state;
f_column_o : for C in 0 to g_NB_COLUMN - 1 generate
column_o(C) <= led_state(g_NB_COLUMN * to_integer(line_oen_cnt) + C);
end generate f_column_o;
end rtl;
hdl/bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd deleted 100644 → 0
View file @ def26966
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Bi-color LED controller package
-- http://www.ohwr.org/projects/svec
--------------------------------------------------------------------------------
--
-- unit name: bicolor_led_ctrl_pkg
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 11-07-2012
--
-- version: 1.0
--
-- description: Package for Bi-color LED controller.
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
package bicolor_led_ctrl_pkg is
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant c_LED_RED : std_logic_vector(1 downto 0) := "10";
constant c_LED_GREEN : std_logic_vector(1 downto 0) := "01";
constant c_LED_RED_GREEN : std_logic_vector(1 downto 0) := "11";
constant c_LED_OFF : std_logic_vector(1 downto 0) := "00";
------------------------------------------------------------------------------
-- Functions declaration
------------------------------------------------------------------------------
function log2_ceil(N : natural) return positive;
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component bicolor_led_ctrl
generic(
g_NB_COLUMN : natural := 4;
g_NB_LINE : natural := 2;
g_CLK_FREQ : natural := 125000000; -- in Hz
g_REFRESH_RATE : natural := 250 -- in Hz
);
port
(
rst_n_i : in std_logic;
clk_i : in std_logic;
led_intensity_i : in std_logic_vector(6 downto 0);
led_state_i : in std_logic_vector((g_NB_LINE * g_NB_COLUMN * 2) - 1 downto 0);
column_o : out std_logic_vector(g_NB_COLUMN - 1 downto 0);
line_o : out std_logic_vector(g_NB_LINE - 1 downto 0);
line_oen_o : out std_logic_vector(g_NB_LINE - 1 downto 0)
);
end component;
end bicolor_led_ctrl_pkg;
package body bicolor_led_ctrl_pkg is
------------------------------------------------------------------------------
-- Function : Returns log of 2 of a natural number
------------------------------------------------------------------------------
function log2_ceil(N : natural) return positive is
begin
if N <= 2 then
return 1;
elsif N mod 2 = 0 then
return 1 + log2_ceil(N/2);
else
return 1 + log2_ceil((N+1)/2);
end if;
end;
end bicolor_led_ctrl_pkg;
hdl/ctb_pulse_gen/Manifest.py deleted 100644 → 0
View file @ def26966
modules = {
"local" : "rtl"
}
hdl/ctb_pulse_gen/rtl/Manifest.py deleted 100644 → 0
View file @ def26966
files = "ctb_pulse_gen.vhd"
modules = {
"local" : [ "../../glitch_filt" ]
}
hdl/ctb_pulse_gen/rtl/ctb_pulse_gen.vhd deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/ctb_pulse_gen/sim/run.do deleted 100644 → 0
View file @ def26966
vlib work
# vcom -explicit -93 "../../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
# vcom -explicit -93 "../../../../ip_cores/general-cores/modules/common/genram_pkg.vhd"
vcom -explicit -93 "../../pulse_gen_gp/rtl/pulse_gen_gp.vhd"
vcom -explicit -93 "../../glitch_filt/rtl/glitch_filt.vhd"
vcom -explicit -93 "../rtl/ctb_pulse_gen.vhd"
vcom -explicit -93 "testbench.vhd"
vsim -t 1ps -voptargs="+acc" -lib work work.testbench
radix -hexadecimal
# add wave *
do wave.do
run 100 us
wave zoomfull
hdl/ctb_pulse_gen/sim/testbench.vhd deleted 100644 → 0
View file @ def26966
--==============================================================================
-- CERN (BE-CO-HT)
-- Testbench for old repeater design
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-02-28
--
-- version: 1.0
--
-- description:
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-02-28 Theodor Stana t.stana@cern.ch File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity testbench is
end entity testbench;
architecture behav of testbench is
--============================================================================
-- Type declarations
--============================================================================
--============================================================================
-- Constant declarations
--============================================================================
constant c_clk_per : time := 8 ns;
constant c_reset_width : time := 31 ns;
--============================================================================
-- Component declarations
--============================================================================
component ctb_pulse_gen is
generic
(
-- Pulse width, in number of clk_i cycles
g_pulse_width : natural := 15;
-- Glitch filter length:
-- g_glitch_filt_len=1 => trigger width should be > 1 clk_i cycle
-- g_glitch_filt_len=2 => trigger width should be > 2 clk_i cycles
-- etc.
g_glitch_filt_len : natural := 4
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Glitch filter enable input
-- '1' - Glitch filter disabled (glitch-sensitive, no output jitter)
-- '0' - Glitch filter enabled (glitch-insensitive, with output jitter)
glitch_filt_en_n_i : in std_logic;
-- Enable input, pulse generation is enabled when '1'
en_i : in std_logic;
-- Trigger input, has to be '1' to assure pulse output with delay no greater
-- than internal gate delays.
trig_i : in std_logic;
-- Pulse output, active-high
-- latency:
-- glitch filter disabled: none
-- glitch filter enabled: g_glitch_filt_len+3 clk_i cycles
pulse_o : out std_logic
);
end component ctb_pulse_gen;
component pulse_gen_gp is
generic
(
g_pwidth : natural := 200;
g_freq : natural := 400;
g_delay : natural := 0
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
en_i : in std_logic;
pulse_o : out std_logic
);
end component pulse_gen_gp;
--============================================================================
-- Signal declarations
--============================================================================
signal clk, clk2, rst_n, pulse, trig, lvl, lvl_n : std_logic := '0';
signal actual_trig : std_logic := '0';
signal actual_pulse : std_logic := '0';
signal gf_en : std_logic;
signal gf_en_n : std_logic;
--==============================================================================
-- architecture begin
--==============================================================================
begin
-- DUT INSTANTIATION
DUT: ctb_pulse_gen
generic map
(
g_pulse_width => 150,
g_glitch_filt_len => 4
)
port map
(
clk_i => clk,
rst_n_i => rst_n,
glitch_filt_en_n_i => gf_en_n,
en_i => '1',
trig_i => actual_trig,
pulse_o => pulse
);
-- CLOCK GENERATION
p_clk: process
begin
clk <= not clk;
wait for c_clk_per/2;
end process p_clk;
-- SECOND CLOCK GENERATION
p_clk2: process
begin
clk2 <= not clk2;
wait for 2 ns;
end process p_clk2;
-- RESET GENERATION
p_rst_n: process
begin
rst_n <= '0';
wait for c_reset_width;
rst_n <= '1';
wait;
end process p_rst_n;
-- PULSE GENERATOR FOR TRIGGER
cmp_pulse_gen: pulse_gen_gp
generic map
(
g_pwidth => 5,
g_freq => 751
)
port map
(
clk_i => clk,
rst_n_i => rst_n,
en_i => '1',
pulse_o => trig
);
actual_trig <= trig;
actual_pulse <= pulse;
cmp_pulse_gen_gp: pulse_gen_gp
generic map
(
g_pwidth => 1033,
g_freq => 2066
)
port map
(
clk_i => clk,
rst_n_i => rst_n,
en_i => '1',
pulse_o => gf_en
);
gf_en_n <= '1'; --not gf_en;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
hdl/ctb_pulse_gen/sim/wave.do deleted 100644 → 0
View file @ def26966
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /testbench/clk
add wave -noupdate /testbench/pulse
add wave -noupdate /testbench/trig
add wave -noupdate /testbench/actual_trig
add wave -noupdate /testbench/actual_pulse
add wave -noupdate /testbench/gf_en
add wave -noupdate /testbench/gf_en_n
add wave -noupdate -divider ctb_pulse_gen
add wave -noupdate /testbench/DUT/trig_i
add wave -noupdate /testbench/DUT/pulse_o
add wave -noupdate /testbench/DUT/trig_degl
add wave -noupdate /testbench/DUT/trig_degl_d0
add wave -noupdate /testbench/DUT/state
add wave -noupdate /testbench/DUT/pulse_cnt
add wave -noupdate /testbench/DUT/pulse_gf_off
add wave -noupdate /testbench/DUT/pulse_gf_off_d0
add wave -noupdate /testbench/DUT/pulse_gf_off_d1
add wave -noupdate /testbench/DUT/pulse_gf_off_d2
add wave -noupdate /testbench/DUT/pulse_rst
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {16056000 ps} 0}
configure wave -namecolwidth 182
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {9493496 ps} {22618504 ps}
hdl/glitch_filt/Manifest.py deleted 100644 → 0
View file @ def26966
modules = {"local" : "rtl"}
hdl/glitch_filt/rtl/glitch_filt.vhd deleted 100644 → 0
View file @ def26966
--==============================================================================
-- CERN (BE-CO-HT)
-- Glitch filter with selectable length
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-03-12
--
-- version: 1.0
--
-- description:
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-03-12 Theodor Stana t.stana@cern.ch File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
entity glitch_filt is
generic
(
-- Length of glitch filter:
-- g_len = 1 => data width should be > 1 clk_i cycle
-- g_len = 2 => data width should be > 2 clk_i cycle
-- etc.
g_len : natural := 4
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Data input
dat_i : in std_logic;
-- Data output
-- latency: g_len+1 clk_i cycles
dat_o : out std_logic
);
end entity glitch_filt;
architecture behav of glitch_filt is
--============================================================================
-- Component declarations
--============================================================================
component gc_sync_ffs is
generic(
g_sync_edge : string := "positive"
);
port(
clk_i : in std_logic; -- clock from the destination clock domain
rst_n_i : in std_logic; -- reset
data_i : in std_logic; -- async input
synced_o : out std_logic; -- synchronized output
npulse_o : out std_logic; -- negative edge detect output (single-clock
-- pulse)
ppulse_o : out std_logic -- positive edge detect output (single-clock
-- pulse)
);
end component gc_sync_ffs;
--============================================================================
-- Signal declarations
--============================================================================
signal glitch_filt : std_logic_vector(g_len downto 0);
signal dat_synced : std_logic;
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Glitch filtration logic
--============================================================================
-- First, synchronize the data input in the clk_i domain
cmp_sync : gc_sync_ffs
port map
(
clk_i => clk_i,
rst_n_i => rst_n_i,
data_i => dat_i,
synced_o => dat_synced,
npulse_o => open,
ppulse_o => open
);
-- Then, assign the current sample of the glitch filter
glitch_filt(0) <= dat_synced;
-- Generate glitch filter FFs when the filter length is > 0
gen_glitch_filt: if (g_len > 0) generate
p_glitch_filt: process (clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
glitch_filt(g_len downto 1) <= (others => '0');
else
glitch_filt(g_len downto 1) <= glitch_filt(g_len-1 downto 0);
end if;
end if;
end process p_glitch_filt;
end generate gen_glitch_filt;
-- and set the data output based on the state of the glitch filter
p_output: process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
dat_o <= '0';
elsif (glitch_filt = (glitch_filt'range => '1')) then
dat_o <= '1';
elsif (glitch_filt = (glitch_filt'range => '0')) then
dat_o <= '0';
end if;
end if;
end process p_output;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
hdl/glitch_filt/sim/run.do deleted 100644 → 0
View file @ def26966
vlib work
vcom -explicit -93 "../../old_rep_test/rtl/pulse_gen.vhd"
vcom -explicit -93 "../rtl/glitch_filt.vhd"
vcom -explicit -93 "testbench.vhd"
vsim -t 1ps -voptargs="+acc" -lib work work.testbench
radix -hexadecimal
# add wave *
do wave.do
run 100 us
wave zoomfull
hdl/glitch_filt/sim/testbench.vhd deleted 100644 → 0
View file @ def26966
--==============================================================================
-- CERN (BE-CO-HT)
-- Testbench for glitch filter
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-03-12
--
-- version: 1.0
--
-- description:
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-03-12 Theodor Stana t.stana@cern.ch File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity testbench is
end entity testbench;
architecture behav of testbench is
--============================================================================
-- Type declarations
--============================================================================
--============================================================================
-- Constant declarations
--============================================================================
constant c_clk_per : time := 8 ns;
constant c_reset_width : time := 31 ns;
--============================================================================
-- Component declarations
--============================================================================
component glitch_filt is
generic
(
g_glitch_filt_len : natural := 4
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
dat_i : in std_logic;
dat_o : out std_logic
);
end component glitch_filt;
component pulse_gen is
generic
(
g_pwidth : natural := 200;
g_freq : natural := 400
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
pulse_o : out std_logic
);
end component pulse_gen;
--============================================================================
-- Signal declarations
--============================================================================
signal clk, rst_n, pulse, degl_out : std_logic := '0';
--==============================================================================
-- architecture begin
--==============================================================================
begin
-- DUT INSTANTIATION
cmp_dut: glitch_filt
generic map
(
g_glitch_filt_len => 4
)
port map
(
clk_i => clk,
rst_n_i => rst_n,
dat_i => pulse,
dat_o => degl_out
);
-- PULSE GENERATOR FOR TRIGGER
cmp_pulse_gen: pulse_gen
generic map
(
g_pwidth => 6,
g_freq => 2000
)
port map
(
clk_i => clk,
rst_n_i => rst_n,
pulse_o => pulse
);
-- CLOCK GENERATION
p_clk: process
begin
clk <= not clk;
wait for c_clk_per/2;
end process p_clk;
-- RESET GENERATION
p_rst_n: process
begin
rst_n <= '0';
wait for c_reset_width;
rst_n <= '1';
wait;
end process p_rst_n;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
hdl/glitch_filt/sim/wave.do deleted 100644 → 0
View file @ def26966
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /testbench/clk
add wave -noupdate /testbench/rst_n
add wave -noupdate /testbench/pulse
add wave -noupdate /testbench/degl_out
add wave -noupdate -divider internal
add wave -noupdate -radix binary /testbench/cmp_dut/glitch_filt
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 2} {96049638 ps} 0} {{Cursor 3} {14565308 ps} 0}
configure wave -namecolwidth 195
configure wave -valuecolwidth 68
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {95866190 ps} {96233086 ps}
hdl/multiboot/Manifest.py deleted 100644 → 0
View file @ def26966
modules = {"local" : "rtl"}
hdl/multiboot/rtl/Manifest.py deleted 100644 → 0
View file @ def26966
files = [
"multiboot_regs.vhd",
"multiboot_fsm.vhd",
"spi_master.vhd",
"xil_multiboot.vhd"
]
hdl/multiboot/rtl/m25p_flash-with-write.vhd deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/multiboot/rtl/m25p_flash.vhd deleted 100644 → 0
View file @ def26966
-----------------------------------------------------------------------------
-- Title : M25Pxxx Flash Controller
-- Project : Simple VME64x FMC Carrier (SVEC)
-------------------------------------------------------------------------------
-- File : m25p_flash.vhd
-- Author : Tomasz Wlostowski
-- Theodor-Adrian Stana
-- Company : CERN
-- Created : 2013-01-24
-- Last update: 2013-09-03
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Simple controller for M25Pxxx series of SPI flash memories.
-- Provides two interfaces: host interface (accessible via FAR register), which
-- can execute any kind of operations, and a simple memory bus which can only read
-- blocks of bytes starting at a given address.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity m25p_flash is
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone registers (FAR register access)
far_data_load_i : in std_logic;
far_data_i : in std_logic_vector(7 downto 0);
far_data_o : out std_logic_vector(7 downto 0);
far_xfer_i : in std_logic;
far_ready_o : out std_logic;
far_cs_i : in std_logic;
-- Data readout interface.
-- 1: sets flash read address to addr_i
set_addr_i : in std_logic;
-- start address for read operations
addr_i : in std_logic_vector(23 downto 0);
-- data request: when 1, the controller reads subsequent bytes from
-- the flash, starting from addr_i address.
read_i : in std_logic;
-- read data output
data_o : out std_logic_vector(7 downto 0);
-- when 1, data_o contains a valid byte and the controller is ready to accept
-- another command
ready_o : out std_logic;
-- SPI bus, connect to the flash memory.
spi_cs_n_o : out std_logic;
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic
);
end m25p_flash;
architecture behavioral of m25p_flash is
component spi_master
generic (
g_div_ratio_log2 : integer;
g_num_data_bits : integer);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
cs_i : in std_logic;
start_i : in std_logic;
cpol_i : in std_logic;
data_i : in std_logic_vector(g_num_data_bits - 1 downto 0);
ready_o : out std_logic;
data_o : out std_logic_vector(g_num_data_bits - 1 downto 0);
spi_cs_n_o : out std_logic;
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic);
end component;
signal spi_cs, spi_cs_muxed : std_logic;
signal spi_start, spi_start_host, spi_start_muxed : std_logic;
signal spi_wdata, spi_wdata_host, spi_wdata_muxed : std_logic_vector(7 downto 0);
signal spi_rdata : std_logic_vector(7 downto 0);
signal spi_ready : std_logic;
type t_read_state is (IDLE, CSEL, COMMAND, ADDR0, ADDR1, ADDR2, DUMMY_XFER, DATA);
signal state : t_read_state;
signal ready_int : std_logic;
begin -- rtl
-- Host flash data register (bidirectional), updated by writing to FAR.DATA
p_host_spi_registers : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
spi_start_host <= '0';
spi_wdata_host <= (others => '0');
elsif (far_data_load_i = '1') then
spi_wdata_host <= far_data_i;
spi_start_host <= far_xfer_i;
else
spi_start_host <= '0';
end if;
end if;
end process;
-- Multplexes the access between to the flash SPI controller between
-- the bootloader host (through FAR register) and the flash readout
-- FSM.
p_mux_spi_access : process(spi_cs, spi_start, spi_wdata,
spi_start_host, spi_wdata, spi_ready,
far_cs_i, far_data_i, far_xfer_i)
begin
spi_cs_muxed <= far_cs_i or spi_cs;
spi_wdata_muxed <= spi_wdata_host or spi_wdata;
spi_start_muxed <= spi_start_host or spi_start;
end process;
far_ready_o <= spi_ready;
far_data_o <= spi_rdata;
-- SPI Master: executes SPI read/write transactions.
U_SPI_Master : spi_master
generic map (
g_div_ratio_log2 => 0,
g_num_data_bits => 8)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
cs_i => spi_cs_muxed,
start_i => spi_start_muxed,
cpol_i => '0',
data_i => spi_wdata_muxed,
ready_o => spi_ready,
data_o => spi_rdata,
spi_cs_n_o => spi_cs_n_o,
spi_sclk_o => spi_sclk_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i);
-- Main State machine
p_main_fsm : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
state <= IDLE;
spi_start <= '0';
spi_cs <= '0';
spi_wdata <= (others => '0');
ready_int <= '1';
-- any access to FAR register stops internal bus request
elsif(far_data_load_i = '1') then
spi_start <= '0';
spi_cs <= '0';
spi_wdata <= (others => '0');
state <= IDLE;
else
case state is
-- Idle: wait for "Set Address" or "Read" commands
when IDLE =>
if set_addr_i = '1' then
spi_cs <= '0';
spi_start <= '1';
ready_int <= '0';
state <= CSEL;
elsif read_i = '1' then
spi_start <= '1';
ready_int <= '0';
state <= DATA;
else
spi_start <= '0';
ready_int <= '1';
end if;
-- executes a dummy SPI cycle with the SPI chip disabled (CS = 0), to
-- make sure it will correctly interpret the next transfer as a READ
-- command
when CSEL =>
if(spi_ready = '1') then
state <= COMMAND;
spi_wdata <= x"0b";
spi_cs <= '1';
spi_start <= '1';
else
spi_start <= '0';
end if;
-- Send command 0x3 (FAST READ DATA)
when COMMAND =>
if(spi_ready = '1') then
state <= ADDR0;
spi_wdata <= addr_i(23 downto 16);
spi_start <= '1';
else
spi_start <= '0';
end if;
-- Send 1st byte of read address
when ADDR0 =>
if(spi_ready = '1') then
state <= ADDR1;
spi_wdata <= addr_i(15 downto 8);
spi_start <= '1';
else
spi_start <= '0';
end if;
-- Send 2nd byte of read address
when ADDR1 =>
if(spi_ready = '1') then
state <= ADDR2;
spi_wdata <= addr_i(7 downto 0);
spi_start <= '1';
else
spi_start <= '0';
end if;
-- Send 3nd byte of read address
when ADDR2 =>
if(spi_ready = '1') then
state <= DUMMY_XFER;
spi_wdata <= "XXXXXXXX";
spi_start <= '1';
else
spi_start <= '0';
end if;
-- dummy transfer (necessary for fast read mode)
when DUMMY_XFER =>
spi_start <= '0';
if(spi_ready = '1') then
state <= IDLE;
end if;
-- Data readout: waits for completion of read transaction initiated
-- upon assertion of read_i and returns the byte read data_o.
when DATA =>
spi_start <= '0';
if(spi_ready = '1')then
data_o <= spi_rdata;
ready_int <= '1';
state <= IDLE;
else
ready_int <= '0';
end if;
end case;
end if;
end if;
end process;
-- De-assert ready flag early
ready_o <= ready_int and not (set_addr_i or read_i);
end behavioral;
hdl/multiboot/rtl/multiboot_fsm.vhd deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/multiboot/rtl/multiboot_regs.vhd deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/multiboot/rtl/spi_master.vhd deleted 100644 → 0
View file @ def26966
-----------------------------------------------------------------------------
-- Title : SPI Bus Master
-- Project : Simple VME64x FMC Carrier (SVEC)
-------------------------------------------------------------------------------
-- File : spi_master.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2013-01-25
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Just a simple SPI master (bus-less).
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011-2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity spi_master is
generic(
-- clock division ratio (SCLK = clk_sys_i / (2 ** g_div_ratio_log2).
g_div_ratio_log2 : integer := 2;
-- number of data bits per transfer
g_num_data_bits : integer := 2);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-- state of the Chip select line (1 = CS active). External control
-- allows for multi-transfer commands (SPI master itself does not
-- control the state of spi_cs_n_o)
cs_i : in std_logic;
-- 1: start next transfer (using CPOL, DATA and SEL from the inputs below)
start_i : in std_logic;
-- Clock polarity: 1: slave clocks in the data on rising SCLK edge, 0: ...
-- on falling SCLK edge
cpol_i : in std_logic;
-- TX Data input
data_i : in std_logic_vector(g_num_data_bits - 1 downto 0);
-- 1: data_o contains the result of last read operation. Core is ready to initiate
-- another transfer.
ready_o : out std_logic;
-- data read from selected slave, valid when ready_o == 1.
data_o : out std_logic_vector(g_num_data_bits - 1 downto 0);
-- these are obvious
spi_cs_n_o : out std_logic;
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic
);
end spi_master;
architecture behavioral of spi_master is
signal divider : unsigned(11 downto 0);
signal tick : std_logic;
signal sreg : std_logic_vector(g_num_data_bits-1 downto 0);
signal rx_sreg : std_logic_vector(g_num_data_bits-1 downto 0);
type t_state is (IDLE, TX_CS, TX_DAT1, TX_DAT2, TX_SCK1, TX_SCK2, TX_CS2, TX_GAP);
signal state : t_state;
signal sclk : std_logic;
signal counter : unsigned(4 downto 0);
begin -- rtl
-- Simple clock divder. Produces a 'tick' signal which defines the timing for
-- the main state machine transitions.
p_divide_spi_clock: process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
divider <= (others => '0');
else
if(start_i = '1' or tick = '1') then
divider <= (others => '0');
else
divider <= divider + 1;
end if;
end if;
end if;
end process;
tick <= divider(g_div_ratio_log2);
-- Main state machine. Executes SPI transfers
p_main_fsm: process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
state <= IDLE;
sclk <= '0';
sreg <= (others => '0');
rx_sreg <= (others => '0');
spi_mosi_o <= '0';
data_o <= (others => '0');
counter <= (others => '0');
else
case state is
-- Waits for start of transfer command
when IDLE =>
sclk <= '0';
counter <= (others => '0');
if(start_i = '1') then
sreg <= data_i;
state <= TX_CS;
spi_mosi_o <= data_i(sreg'high);
end if;
-- Generates a gap between the externally asserted Chip Select and
-- the beginning of data transfer
when TX_CS =>
if tick = '1' then
state <= TX_DAT1;
end if;
-- Outputs subsequent bits to MOSI line.
when TX_DAT1 =>
if(tick = '1') then
spi_mosi_o <= sreg(sreg'high);
sreg <= sreg(sreg'high-1 downto 0) & '0';
state <= TX_SCK1;
end if;
-- Flips the SCLK (active edge)
when TX_SCK1 =>
if(tick = '1') then
sclk <= not sclk;
counter <= counter + 1;
state <= TX_DAT2;
end if;
-- Shifts in bits read from the slave
when TX_DAT2 =>
if(tick = '1') then
rx_sreg <= rx_sreg(rx_sreg'high-1 downto 0) & spi_miso_i;
state <= TX_SCK2;
end if;
-- Flips the SCLK (inactive edge). Checks if all bits have been
-- transferred.
when TX_SCK2 =>
if(tick = '1') then
sclk <= not sclk;
if(counter = g_num_data_bits) then
state <= TX_CS2;
else
state <= TX_DAT1;
end if;
end if;
-- Generates a gap for de-assertoin of CS line
when TX_CS2 =>
if(tick = '1') then
state <= TX_GAP;
data_o <= rx_sreg;
end if;
when TX_GAP =>
if (tick = '1') then
state <= IDLE;
end if;
end case;
end if;
end if;
end process;
ready_o <= '1' when (state = IDLE and start_i = '0') else '0';
-- SCLK polarity control
spi_sclk_o <= sclk xor cpol_i;
spi_cs_n_o <= not cs_i;
end behavioral;
hdl/multiboot/rtl/xil_multiboot.vhd deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/multiboot/sim/conv.txt deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/multiboot/sim/dump.txt deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/multiboot/sim/run.do deleted 100644 → 0
View file @ def26966
vlib work
vcom -explicit -93 "~/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
vcom -explicit -93 "~/Projects/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"
vcom -explicit -93 "~/Projects/M25P64_VHDL_1.0/code/ACDC_check.vhd"
vcom -explicit -93 "~/Projects/M25P64_VHDL_1.0/code/mem_util_pkg.vhd"
vcom -explicit -93 "~/Projects/M25P64_VHDL_1.0/code/Memory_Access.vhd"
vcom -explicit -93 "~/Projects/M25P64_VHDL_1.0/code/Internal_Logic.vhd"
vcom -explicit -93 "~/Projects/M25P64_VHDL_1.0/code/M25P64.vhd"
vcom -explicit -93 "../rtl/spi_master.vhd"
vcom -explicit -93 "../rtl/m25p_flash.vhd"
vcom -explicit -93 "../rtl/multiboot_regs.vhd"
vcom -explicit -93 "../rtl/multiboot_fsm.vhd"
vcom -explicit -93 "../rtl/xil_multiboot.vhd"
vcom -explicit -93 "testbench.vhd"
vsim -voptargs="+acc" -lib work work.testbench
#log -r /*
# add wave *
do wave.do
run 300 us
hdl/multiboot/sim/testbench.vhd deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/multiboot/sim/transcript deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/multiboot/sim/vsim_stacktrace.vstf deleted 100644 → 0
View file @ def26966
# Current time Mon Sep 2 14:33:01 2013
# ModelSim Stack Trace
# Program = vsim
# Id = "10.1"
# Version = "2011.12"
# Date = "Dec 5 2011"
# Platform = linux
# 0 0xb7715424: '<unknown (@0xb7715424)>'
# 1 0x089f10ca: '<unknown (@0x89f10ca)>'
# 2 0x089acb6b: '<unknown (@0x89acb6b)>'
# 3 0x089ffb2d: '<unknown (@0x89ffb2d)>'
# 4 0x0891484b: '<unknown (@0x891484b)>'
# 5 0x085d8725: '<unknown (@0x85d8725)>'
# 6 0x085d8980: '<unknown (@0x85d8980)>'
# 7 0x085d963d: '<unknown (@0x85d963d)>'
# 8 0x089a6f27: '<unknown (@0x89a6f27)>'
# 9 0x089a86d9: '<unknown (@0x89a86d9)>'
# 10 0x089a9b6d: '<unknown (@0x89a9b6d)>'
# 11 0x089a9fb0: '<unknown (@0x89a9fb0)>'
# 12 0x089aa99a: '<unknown (@0x89aa99a)>'
# 13 0x0875facb: '<unknown (@0x875facb)>'
# 14 0x089e0d0b: '<unknown (@0x89e0d0b)>'
# 15 0x08a0c882: '<unknown (@0x8a0c882)>'
# 16 0x089eeb90: '<unknown (@0x89eeb90)>'
# 17 0x089eee8e: '<unknown (@0x89eee8e)>'
# 18 0x08914d60: '<unknown (@0x8914d60)>'
# 19 0x0845c1f3: '<unknown (@0x845c1f3)>'
# 20 0x0838d719: '<unknown (@0x838d719)>'
# 21 0x08062b46: '<unknown (@0x8062b46)>'
# End of Stack Trace
# Current time Mon Sep 2 14:34:26 2013
# ModelSim Stack Trace
# Program = vsim
# Id = "10.1"
# Version = "2011.12"
# Date = "Dec 5 2011"
# Platform = linux
# 0 0xb77c0424: '<unknown (@0xb77c0424)>'
# 1 0x089f10ca: '<unknown (@0x89f10ca)>'
# 2 0x089acb6b: '<unknown (@0x89acb6b)>'
# 3 0x089ffb2d: '<unknown (@0x89ffb2d)>'
# 4 0x0891484b: '<unknown (@0x891484b)>'
# 5 0x085d8725: '<unknown (@0x85d8725)>'
# 6 0x085d8980: '<unknown (@0x85d8980)>'
# 7 0x085d963d: '<unknown (@0x85d963d)>'
# 8 0x089a6f27: '<unknown (@0x89a6f27)>'
# 9 0x089a86d9: '<unknown (@0x89a86d9)>'
# 10 0x089a9b6d: '<unknown (@0x89a9b6d)>'
# 11 0x089a9fb0: '<unknown (@0x89a9fb0)>'
# 12 0x089aa99a: '<unknown (@0x89aa99a)>'
# 13 0x0875facb: '<unknown (@0x875facb)>'
# 14 0x089e0d0b: '<unknown (@0x89e0d0b)>'
# 15 0x08a0c882: '<unknown (@0x8a0c882)>'
# 16 0x089eeb90: '<unknown (@0x89eeb90)>'
# 17 0x089eee8e: '<unknown (@0x89eee8e)>'
# 18 0x08914d60: '<unknown (@0x8914d60)>'
# 19 0x0845c1f3: '<unknown (@0x845c1f3)>'
# 20 0x0838d719: '<unknown (@0x838d719)>'
# 21 0x08062b46: '<unknown (@0x8062b46)>'
# End of Stack Trace
# Current time Mon Sep 2 14:38:02 2013
# ModelSim Stack Trace
# Program = vsim
# Id = "10.1"
# Version = "2011.12"
# Date = "Dec 5 2011"
# Platform = linux
# 0 0xb779c424: '<unknown (@0xb779c424)>'
# 1 0x089f10ca: '<unknown (@0x89f10ca)>'
# 2 0x089acb6b: '<unknown (@0x89acb6b)>'
# 3 0x089ffb2d: '<unknown (@0x89ffb2d)>'
# 4 0x0891484b: '<unknown (@0x891484b)>'
# 5 0x085d8725: '<unknown (@0x85d8725)>'
# 6 0x085d8980: '<unknown (@0x85d8980)>'
# 7 0x085d963d: '<unknown (@0x85d963d)>'
# 8 0x089a6f27: '<unknown (@0x89a6f27)>'
# 9 0x089a86d9: '<unknown (@0x89a86d9)>'
# 10 0x089a9b6d: '<unknown (@0x89a9b6d)>'
# 11 0x089a9fb0: '<unknown (@0x89a9fb0)>'
# 12 0x089aa99a: '<unknown (@0x89aa99a)>'
# 13 0x0875facb: '<unknown (@0x875facb)>'
# 14 0x089e0d0b: '<unknown (@0x89e0d0b)>'
# 15 0x08a0c882: '<unknown (@0x8a0c882)>'
# 16 0x089eeb90: '<unknown (@0x89eeb90)>'
# 17 0x089eee8e: '<unknown (@0x89eee8e)>'
# 18 0x08914d60: '<unknown (@0x8914d60)>'
# 19 0x0845c1f3: '<unknown (@0x845c1f3)>'
# 20 0x0838d719: '<unknown (@0x838d719)>'
# 21 0x08062b46: '<unknown (@0x8062b46)>'
# End of Stack Trace
# Current time Mon Sep 2 14:41:22 2013
# ModelSim Stack Trace
# Program = vsim
# Id = "10.1"
# Version = "2011.12"
# Date = "Dec 5 2011"
# Platform = linux
# 0 0xb778f424: '<unknown (@0xb778f424)>'
# 1 0x089f10ca: '<unknown (@0x89f10ca)>'
# 2 0x089acb6b: '<unknown (@0x89acb6b)>'
# 3 0x089ffb2d: '<unknown (@0x89ffb2d)>'
# 4 0x0891484b: '<unknown (@0x891484b)>'
# 5 0x085d8725: '<unknown (@0x85d8725)>'
# 6 0x085d8980: '<unknown (@0x85d8980)>'
# 7 0x085d8f39: '<unknown (@0x85d8f39)>'
# 8 0x085dd61b: '<unknown (@0x85dd61b)>'
# 9 0x089a6f27: '<unknown (@0x89a6f27)>'
# 10 0x089a86d9: '<unknown (@0x89a86d9)>'
# 11 0x089a9b6d: '<unknown (@0x89a9b6d)>'
# 12 0x089a9fb0: '<unknown (@0x89a9fb0)>'
# 13 0x089aa99a: '<unknown (@0x89aa99a)>'
# 14 0x0875facb: '<unknown (@0x875facb)>'
# 15 0x089e0d0b: '<unknown (@0x89e0d0b)>'
# 16 0x08a0c882: '<unknown (@0x8a0c882)>'
# 17 0x089eeb90: '<unknown (@0x89eeb90)>'
# 18 0x089eee8e: '<unknown (@0x89eee8e)>'
# 19 0x08914d60: '<unknown (@0x8914d60)>'
# 20 0x0845c1f3: '<unknown (@0x845c1f3)>'
# 21 0x0838d719: '<unknown (@0x838d719)>'
# 22 0x08062b46: '<unknown (@0x8062b46)>'
# End of Stack Trace
hdl/multiboot/sim/wave.do deleted 100644 → 0
View file @ def26966
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /testbench/rst_n
add wave -noupdate /testbench/clk
add wave -noupdate /testbench/transfer
add wave -noupdate /testbench/write
add wave -noupdate /testbench/str
add wave -noupdate -radix hexadecimal /testbench/wb_adr
add wave -noupdate -radix hexadecimal -childformat {{/testbench/wb_dat_in(31) -radix hexadecimal} {/testbench/wb_dat_in(30) -radix hexadecimal} {/testbench/wb_dat_in(29) -radix hexadecimal} {/testbench/wb_dat_in(28) -radix hexadecimal} {/testbench/wb_dat_in(27) -radix hexadecimal} {/testbench/wb_dat_in(26) -radix hexadecimal} {/testbench/wb_dat_in(25) -radix hexadecimal} {/testbench/wb_dat_in(24) -radix hexadecimal} {/testbench/wb_dat_in(23) -radix hexadecimal} {/testbench/wb_dat_in(22) -radix hexadecimal} {/testbench/wb_dat_in(21) -radix hexadecimal} {/testbench/wb_dat_in(20) -radix hexadecimal} {/testbench/wb_dat_in(19) -radix hexadecimal} {/testbench/wb_dat_in(18) -radix hexadecimal} {/testbench/wb_dat_in(17) -radix hexadecimal} {/testbench/wb_dat_in(16) -radix hexadecimal} {/testbench/wb_dat_in(15) -radix hexadecimal} {/testbench/wb_dat_in(14) -radix hexadecimal} {/testbench/wb_dat_in(13) -radix hexadecimal} {/testbench/wb_dat_in(12) -radix hexadecimal} {/testbench/wb_dat_in(11) -radix hexadecimal} {/testbench/wb_dat_in(10) -radix hexadecimal} {/testbench/wb_dat_in(9) -radix hexadecimal} {/testbench/wb_dat_in(8) -radix hexadecimal} {/testbench/wb_dat_in(7) -radix hexadecimal} {/testbench/wb_dat_in(6) -radix hexadecimal} {/testbench/wb_dat_in(5) -radix hexadecimal} {/testbench/wb_dat_in(4) -radix hexadecimal} {/testbench/wb_dat_in(3) -radix hexadecimal} {/testbench/wb_dat_in(2) -radix hexadecimal} {/testbench/wb_dat_in(1) -radix hexadecimal} {/testbench/wb_dat_in(0) -radix hexadecimal}} -subitemconfig {/testbench/wb_dat_in(31) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(30) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(29) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(28) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(27) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(26) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(25) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(24) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(23) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(22) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(21) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(20) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(19) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(18) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(17) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(16) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(15) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(14) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(13) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(12) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(11) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(10) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(9) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(8) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(7) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(6) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(5) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(4) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(3) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(2) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(1) {-height 16 -radix hexadecimal} /testbench/wb_dat_in(0) {-height 16 -radix hexadecimal}} /testbench/wb_dat_in
add wave -noupdate -radix hexadecimal /testbench/wb_dat_out
add wave -noupdate /testbench/wb_cyc
add wave -noupdate /testbench/wb_stb
add wave -noupdate /testbench/wb_we
add wave -noupdate /testbench/wb_ack
add wave -noupdate /testbench/wb_stall
add wave -noupdate /testbench/ready
add wave -noupdate -radix hexadecimal /testbench/fldat
add wave -noupdate -divider regs
add wave -noupdate /testbench/UUT/cmp_regs/multiboot_far_data_load_int
add wave -noupdate /testbench/UUT/cmp_regs/multiboot_far_xfer_int
add wave -noupdate /testbench/UUT/cmp_regs/multiboot_far_ready_int
add wave -noupdate /testbench/UUT/cmp_regs/multiboot_far_cs_int
add wave -noupdate -divider FSM
add wave -noupdate /testbench/UUT/cmp_fsm/state
add wave -noupdate /testbench/UUT/cmp_fsm/fsm_cmd
add wave -noupdate /testbench/UUT/cmp_fsm/fsm_cmd_reg
add wave -noupdate -divider fsm-spi
add wave -noupdate -radix hexadecimal /testbench/UUT/cmp_fsm/reg_far_data_i
add wave -noupdate -radix hexadecimal /testbench/UUT/cmp_fsm/reg_far_data_o
add wave -noupdate /testbench/UUT/cmp_fsm/reg_far_nbytes_i
add wave -noupdate /testbench/UUT/cmp_fsm/reg_far_xfer_i
add wave -noupdate /testbench/UUT/cmp_fsm/reg_far_cs_i
add wave -noupdate /testbench/UUT/cmp_fsm/reg_far_ready_o
add wave -noupdate /testbench/UUT/cmp_fsm/spi_xfer_o
add wave -noupdate /testbench/UUT/cmp_fsm/spi_cs_o
add wave -noupdate -radix hexadecimal /testbench/UUT/cmp_fsm/spi_data_i
add wave -noupdate -radix hexadecimal /testbench/UUT/cmp_fsm/spi_data_o
add wave -noupdate /testbench/UUT/cmp_fsm/spi_ready_i
add wave -noupdate -radix hexadecimal /testbench/UUT/cmp_fsm/spi_data_int
add wave -noupdate /testbench/UUT/cmp_fsm/spi_cnt
add wave -noupdate -divider {spi pins}
add wave -noupdate /testbench/UUT/spi_cs_n_o
add wave -noupdate /testbench/UUT/spi_sclk_o
add wave -noupdate /testbench/UUT/spi_mosi_o
add wave -noupdate /testbench/UUT/spi_miso_i
add wave -noupdate -divider spi
add wave -noupdate -radix hexadecimal /testbench/UUT/cmp_spi_master/data_i
add wave -noupdate -radix hexadecimal /testbench/UUT/cmp_spi_master/data_o
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {63727 ns} 0}
configure wave -namecolwidth 335
configure wave -valuecolwidth 99
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {61939 ns} {66867 ns}
hdl/multiboot/syn/Makefile deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/multiboot/syn/Manifest.py deleted 100644 → 0
View file @ def26966
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "conv_ttl_blo"
syn_project = "conv_ttl_blo.xise"
modules = {
"local" : [
"../top"
]
}
hdl/multiboot/syn/conv_ttl_blo.xise deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/multiboot/top/Manifest.py deleted 100644 → 0
View file @ def26966
files = [
"conv_regs.vhd",
"conv_ttl_blo.ucf",
"conv_ttl_blo.vhd"
]
modules = {
"local" : [
"../../rtm_detector",
"../../reset_gen",
"../../bicolor_led_ctrl",
"../../vbcp_wb",
"../rtl"
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git"
]
}
fetchto = "../../../../../ip_cores"
hdl/multiboot/top/conv_regs.vhd deleted 100644 → 0
View file @ def26966
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Converter board registers
---------------------------------------------------------------------------------------
-- File : conv_regs.vhd
-- Author : auto-generated by wbgen2 from conv_regs.wb
-- Created : Fri Aug 2 16:02:13 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE conv_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity conv_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'bits' in reg: 'Board ID register'
conv_regs_id_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'fwvers' in reg: 'Status register'
conv_regs_sr_fwvers_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'switches' in reg: 'Status register'
conv_regs_sr_switches_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'RTM detection' in reg: 'Status register'
conv_regs_sr_rtm_i : in std_logic_vector(5 downto 0);
-- Port for BIT field: 'Reset unlock bit' in reg: 'Control register'
conv_regs_cr_rst_unlock_o : out std_logic;
-- Port for BIT field: 'Reset bit' in reg: 'Control register'
conv_regs_cr_rst_o : out std_logic
);
end conv_regs;
architecture syn of conv_regs is
signal conv_regs_id_bits_int : std_logic_vector(31 downto 0);
signal conv_regs_cr_rst_unlock_int : std_logic ;
signal conv_regs_cr_rst_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
conv_regs_id_bits_int <= x"424c4f32";
conv_regs_cr_rst_unlock_int <= '0';
conv_regs_cr_rst_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
conv_regs_id_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= conv_regs_id_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
if (wb_we_i = '1') then
end if;
rddata_reg(15 downto 0) <= conv_regs_sr_fwvers_i;
rddata_reg(23 downto 16) <= conv_regs_sr_switches_i;
rddata_reg(29 downto 24) <= conv_regs_sr_rtm_i;
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
if (wb_we_i = '1') then
conv_regs_cr_rst_unlock_int <= wrdata_reg(0);
conv_regs_cr_rst_int <= wrdata_reg(31);
end if;
rddata_reg(0) <= conv_regs_cr_rst_unlock_int;
rddata_reg(31) <= conv_regs_cr_rst_int;
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- bits
conv_regs_id_bits_o <= conv_regs_id_bits_int;
-- fwvers
-- switches
-- RTM detection
-- Reset unlock bit
conv_regs_cr_rst_unlock_o <= conv_regs_cr_rst_unlock_int;
-- Reset bit
conv_regs_cr_rst_o <= conv_regs_cr_rst_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
hdl/multiboot/top/conv_ttl_blo.ucf deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/multiboot/top/conv_ttl_blo.vhd deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/pulse_gen_gp/Manifest.py deleted 100644 → 0
View file @ def26966
modules = {"local" : "rtl"}
hdl/pulse_gen_gp/rtl/Manifest.py deleted 100644 → 0
View file @ def26966
files = [
"pulse_gen_gp.vhd"
]
hdl/pulse_gen_gp/rtl/pulse_gen_gp.vhd deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/pulse_gen_gp/sim/run.do deleted 100644 → 0
View file @ def26966
vlib work
vcom -explicit -93 "../rtl/pulse_gen_gp.vhd"
vcom -explicit -93 "testbench.vhd"
vsim -t 1ps -voptargs="+acc" -lib work work.testbench
radix -hexadecimal
#add wave *
do wave.do
run 2 ms
wave zoomfull
hdl/pulse_gen_gp/sim/testbench.vhd deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/pulse_gen_gp/sim/transcript deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/pulse_gen_gp/sim/wave.do deleted 100644 → 0
View file @ def26966
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /testbench/clk
add wave -noupdate /testbench/rst_n
add wave -noupdate /testbench/en
add wave -noupdate /testbench/del
add wave -noupdate /testbench/pw
add wave -noupdate /testbench/f
add wave -noupdate /testbench/pulse
add wave -noupdate /testbench/pulse1
add wave -noupdate -divider UUT
add wave -noupdate /testbench/UUT/freq_cnt
add wave -noupdate /testbench/UUT/delay_cnt
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {1999669826 ps} 0} {{Cursor 2} {300152000 ps} 0}
configure wave -namecolwidth 194
configure wave -valuecolwidth 72
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ps} {2100 us}
hdl/release/rtl/Manifest.py deleted 100644 → 0
View file @ def26966
files = [
"conv_regs.vhd"
];
hdl/release/rtl/conv_regs.vhd deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/release/rtl/conv_regs.wb deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/release/syn/Makefile deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/release/syn/Manifest.py deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/release/syn/conv_ttl_blo.xise deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/release/top/Manifest.py deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/release/top/conv_ttl_blo.ucf deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/release/top/conv_ttl_blo.vhd deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/reset_gen/Manifest.py deleted 100644 → 0
View file @ def26966
modules = {"local" : "rtl"}
hdl/reset_gen/rtl/reset_gen.vhd deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/reset_gen/sim/run.do deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/reset_gen/sim/testbench.vhd deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/reset_gen/syn/Makefile deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/reset_gen/syn/Manifest.py deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/reset_gen/syn/conv_ttl_blo_v2.xise deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/reset_gen/syn/run.tcl deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/reset_gen/top/Manifest.py deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/reset_gen/top/conv_ttl_blo_v2.ucf deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/reset_gen/top/conv_ttl_blo_v2.vhd deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/rtm_detector/Manifest.py deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/rtm_detector/rtl/Manifest.py deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/rtm_detector/rtl/rtm_detector.vhd deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/test_pulse/rtl/Manifest.py deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/test_pulse/rtl/conv_regs.vhd deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/test_pulse/rtl/pgen_ctrl_regs.vhd deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/test_pulse/rtl/pgen_ctrl_regs.wb deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/test_pulse/rtl/pulse_cnt_regs.vhd deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/test_pulse/rtl/pulse_cnt_regs.wb deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/test_pulse/syn/Makefile deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/test_pulse/syn/Manifest.py deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/test_pulse/syn/conv_ttl_blo.xise deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/test_pulse/syn/regtest.ppr deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/test_pulse/top/Manifest.py deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/test_pulse/top/conv_ttl_blo.ucf deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/test_pulse/top/conv_ttl_blo.vhd deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/test_regs/syn/Makefile deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/test_regs/syn/Manifest.py deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/test_regs/syn/conv_ttl_blo.xise deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/test_regs/syn/regtest.ppr deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/test_regs/top/Manifest.py deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/test_regs/top/conv_ttl_blo.ucf deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/test_regs/top/conv_ttl_blo.vhd deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/vbcp_wb/Manifest.py deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/vbcp_wb/rtl/Manifest.py deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/vbcp_wb/rtl/i2c_slave.vhd deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/vbcp_wb/rtl/i2c_slave_pkg.vhd deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/vbcp_wb/rtl/vbcp_wb.vhd deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/vbcp_wb/sim/i2c_master_bit_ctrl.vhd deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/vbcp_wb/sim/i2c_master_byte_ctrl.vhd deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/vbcp_wb/sim/run.do deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/vbcp_wb/sim/tb_i2c_slave.vhd deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/vbcp_wb/sim/tb_vme64x_i2c.vhd deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/vbcp_wb/sim/transcript deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/vbcp_wb/sim/wave.do deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/vbcp_wb/sim/wave_i2c_slave.do deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/vbcp_wb/syn/Makefile deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/vbcp_wb/syn/Manifest.py deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/vbcp_wb/syn/conv_ttl_blo_v2.ppr deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/vbcp_wb/syn/conv_ttl_blo_v2.xise deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/vbcp_wb/syn/run.tcl deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/vbcp_wb/top/Manifest.py deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/vbcp_wb/top/conv_ttl_blo_v2.ucf deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/vbcp_wb/top/conv_ttl_blo_v2.vhd deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/vbcp_wb/top/test_regs.vhd deleted 100644 → 0
View file @ def26966
This diff is collapsed.
hdl/vbcp_wb/top/test_regs.wb deleted 100644 → 0
View file @ def26966
This diff is collapsed.
syn/regtest/regtest.xise
View file @ 12d56e6a
This diff is collapsed.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment