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Conv TTL Blocking - Gateware
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Conv TTL Blocking - Gateware
Commits
0c3e9fc3
Commit
0c3e9fc3
authored
Jan 30, 2014
by
Theodor-Adrian Stana
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hdl: moved modules/conv_pulse_gen.vhd to modules/Release/
Signed-off-by:
Theodor Stana
<
t.stana@cern.ch
>
parent
83b87d10
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3 changed files
with
8 additions
and
8 deletions
+8
-8
Manifest.py
modules/Manifest.py
+0
-1
Manifest.py
modules/Release/Manifest.py
+1
-0
conv_pulse_gen.vhd
modules/Release/conv_pulse_gen.vhd
+7
-7
No files found.
modules/Manifest.py
View file @
0c3e9fc3
...
...
@@ -7,7 +7,6 @@ modules = {
}
files
=
[
"conv_pulse_gen.vhd"
,
"reset_gen.vhd"
,
"rtm_detector.vhd"
]
modules/Release/Manifest.py
View file @
0c3e9fc3
files
=
[
"conv_regs.vhd"
,
"conv_pulse_gen.vhd"
,
"conv_man_trig.vhd"
];
modules/conv_pulse_gen.vhd
→
modules/
Release/
conv_pulse_gen.vhd
View file @
0c3e9fc3
...
...
@@ -93,8 +93,8 @@ entity conv_pulse_gen is
-- Pulse output, active-high
-- latency:
-- glitch filter disabled: none
-- glitch filter enabled
: g_gf_len+5
clk_i cycles
-- glitch filter disabled
: none
-- glitch filter enabled
: g_gf_len+6
clk_i cycles
pulse_o
:
out
std_logic
);
end
entity
conv_pulse_gen
;
...
...
@@ -151,7 +151,7 @@ architecture behav of conv_pulse_gen is
signal
pulse_gf_off_d0
:
std_logic
;
signal
pulse_gf_off_d1
:
std_logic
;
signal
pulse_gf_off_d2
:
std_logic
;
signal
pulse_rst
:
std_logic
;
signal
pulse_rst
:
std_logic
;
signal
pulse_gf_on
:
std_logic
;
...
...
@@ -178,7 +178,7 @@ begin
if
(
pulse_rst
=
'1'
)
then
pulse_gf_off
<=
'0'
;
elsif
rising_edge
(
trig_a_i
)
then
if
(
en_i
=
'1'
)
then
if
(
en_i
=
'1'
)
and
(
gf_en_n_i
=
'1'
)
then
pulse_gf_off
<=
'1'
;
end
if
;
end
if
;
...
...
@@ -192,7 +192,7 @@ begin
pulse_gf_off_d0
<=
'0'
;
pulse_gf_off_d1
<=
'0'
;
pulse_gf_off_d2
<=
'0'
;
elsif
(
en_i
=
'1'
)
then
elsif
(
en_i
=
'1'
)
and
(
gf_en_n_i
=
'1'
)
then
pulse_gf_off_d0
<=
pulse_gf_off
;
pulse_gf_off_d1
<=
pulse_gf_off_d0
;
pulse_gf_off_d2
<=
pulse_gf_off_d1
;
...
...
@@ -269,7 +269,7 @@ begin
when
GEN_GF_OFF
=>
pulse_cnt
<=
pulse_cnt
+
1
;
if
(
pulse_cnt
=
c_max_gen_gf_off
)
then
state
<=
REJ_GF_OFF
;
state
<=
REJ_GF_OFF
;
end
if
;
---------------------------------------------------------------------
...
...
@@ -298,7 +298,7 @@ begin
pulse_cnt
<=
pulse_cnt
+
1
;
pulse_gf_on
<=
'1'
;
if
(
pulse_cnt
=
c_max_gen_gf_on
)
then
state
<=
REJ_GF_ON
;
state
<=
REJ_GF_ON
;
end
if
;
---------------------------------------------------------------------
...
...
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