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Conv TTL Blocking - Gateware
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Conv TTL Blocking - Gateware
Commits
03f3fdcb
Commit
03f3fdcb
authored
Dec 19, 2013
by
Theodor-Adrian Stana
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Updates to general-cores submodule
Signed-off-by:
Theodor Stana
<
t.stana@cern.ch
>
parent
b1a5fa52
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general-cores
ip_cores/general-cores
+1
-1
regtest.xise
syn/regtest/regtest.xise
+3
-3
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general-cores
@
4ec72cb6
Subproject commit
66e9242e4a0b0db318bca985bf067219df0da083
Subproject commit
4ec72cb65766fbbddc30b51d3c4094cf00b61509
syn/regtest/regtest.xise
View file @
03f3fdcb
...
...
@@ -175,7 +175,7 @@
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<property
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xil_pn:value=
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<property
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xil_pn:value=
""
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xil_pn:value=
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<property
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xil_pn:value=
""
xil_pn:valueState=
"default"
/>
...
...
@@ -243,7 +243,7 @@
<property
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"Reset On Configuration Pulse Width"
xil_pn:value=
"100"
xil_pn:valueState=
"default"
/>
<property
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"Resource Sharing"
xil_pn:value=
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xil_pn:value=
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xil_pn:value=
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xil_pn:valueState=
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...
...
@@ -313,7 +313,7 @@
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xil_pn:name=
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xil_pn:value=
""
xil_pn:valueState=
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xil_pn:value=
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xil_pn:value=
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<!-- -->
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