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Conv TTL Blocking - Gateware
Commit 02f3c449 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Changes in ctb_pulse_gen 

- made max value constant names clearer
- constrained g_pwidth generic as per blocking pulse specification,
considering a 20 MHz input clock
Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
parent 147bf9c2
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Showing with 62 additions and 54 deletions
modules/ctb_pulse_gen.vhd
View file @ 02f3c449
......@@ -10,7 +10,7 @@
-- version: 1.0
--
-- description:
-- This module generates a variable-width pulse. The width is set using the
-- This module generates a constant-width pulse. The width is set using the
-- g_pwidth generic, given in number of clk_i cycles. With a clk_i
-- period of 8ns, the output pulse width is by default 8*16=128ns.
--
......@@ -46,9 +46,8 @@
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 01-03-2013 Theodor Stana t.stana@cern.ch File created
-- 02-08-2013 Theodor Stana t.stana@cern.ch Implemented rejection
-- phase
-- 01-03-2013 Theodor Stana File created
-- 02-08-2013 Theodor Stana Implemented rejection phase
--==============================================================================
-- TODO: -
--==============================================================================
......@@ -63,16 +62,20 @@ entity ctb_pulse_gen is
generic
(
-- Pulse width, in number of clk_i cycles
g_pwidth : natural := 15;
-- Default pulse width (20 MHz clock): 1.2 us
-- Minimum allowable pulse width (20 MHz clock): 1 us
-- Maximum allowable pulse width (20 MHz clock): 2 us
g_pwidth : natural range 20 to 40 := 24;
-- Glitch filter length:
-- g_gf_len=1 => trigger width should be > 1 clk_i cycle
-- g_gf_len=2 => trigger width should be > 2 clk_i cycles
-- etc.
g_gf_len : natural := 4
g_gf_len : natural := 1
);
port
(
-- Clock and active-low reset inputs
clk_i : in std_logic;
rst_n_i : in std_logic;
......@@ -86,12 +89,12 @@ entity ctb_pulse_gen is
-- Trigger input, has to be '1' to assure pulse output with delay no greater
-- than internal gate delays.
trig_i : in std_logic;
trig_a_i : in std_logic;
-- Pulse output, active-high
-- latency:
-- glitch filter disabled: none
-- glitch filter enabled: g_gf_len+3 clk_i cycles
-- glitch filter enabled: g_gf_len+5 clk_i cycles
pulse_o : out std_logic
);
end entity ctb_pulse_gen;
......@@ -102,18 +105,23 @@ architecture behav of ctb_pulse_gen is
--============================================================================
-- Type declarations
--============================================================================
type t_state is ( ST_IDLE, ST_GEN_GF_OFF, ST_REJ_GF_OFF,
ST_GEN_GF_ON, ST_REJ_GF_ON );
type t_state is (
IDLE, -- idle state, wait for pulse
GEN_GF_OFF, -- pulse generation, glitch filter off
REJ_GF_OFF, -- pulse rejection, glitch filter off
GEN_GF_ON, -- pulse generation, glitch filter on
REJ_GF_ON -- pulse rejection, glitch filter on
);
--============================================================================
-- Constant declarations
--============================================================================
-- Max value of pulse counter for pulse width and pulse rejection width; see
-- below for explanation for their values
constant c_pulse_width_gf_off : natural := g_pwidth-5;
constant c_pulse_rej_gf_off : natural := 5*g_pwidth-5;
constant c_pulse_width_gf_on : natural := g_pwidth-1;
constant c_pulse_rej_gf_on : natural := 5*g_pwidth-1;
constant c_max_gen_gf_off : natural := g_pwidth-5;
constant c_max_rej_gf_off : natural := 5*g_pwidth-5;
constant c_max_gen_gf_on : natural := g_pwidth-1;
constant c_max_rej_gf_on : natural := 5*g_pwidth-1;
--============================================================================
-- Function and procedure declarations
......@@ -164,12 +172,12 @@ begin
--============================================================================
-- Pulse generation logic
--============================================================================
-- Generate the pulse on rising edge of trig_i
p_pulse_gf_off: process(pulse_rst, trig_i)
-- Generate the pulse on rising edge of trig_a_i
p_pulse_gf_off: process(pulse_rst, trig_a_i)
begin
if (pulse_rst = '1') then
pulse_gf_off <= '0';
elsif rising_edge(trig_i) then
elsif rising_edge(trig_a_i) then
if (en_i = '1') then
pulse_gf_off <= '1';
end if;
......@@ -204,7 +212,7 @@ begin
(
clk_i => clk_i,
rst_n_i => rst_n_i,
dat_i => trig_i,
dat_i => trig_a_i,
dat_o => trig_degl
);
......@@ -215,7 +223,7 @@ begin
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
state <= ST_IDLE;
state <= IDLE;
pulse_rst <= '1';
pulse_gf_on <= '0';
pulse_cnt <= (others => '0');
......@@ -227,26 +235,26 @@ begin
-- State machine
case state is
---------------------------------------------------------------------
-- ST_IDLE
-- IDLE
---------------------------------------------------------------------
-- Clear all values and go to pulse generation state when the
-- appropriate input arrives
---------------------------------------------------------------------
when ST_IDLE =>
when IDLE =>
pulse_cnt <= (others => '0');
pulse_rst <= '0';
if (gf_en_n_i = '1') then
if (pulse_gf_off_d1 = '1') and (pulse_gf_off_d2 = '0') then
state <= ST_GEN_GF_OFF;
state <= GEN_GF_OFF;
end if;
else
if (trig_degl = '1') and (trig_degl_d0 = '0') then
state <= ST_GEN_GF_ON;
state <= GEN_GF_ON;
end if;
end if;
---------------------------------------------------------------------
-- ST_GEN_GF_OFF
-- GEN_GF_OFF
---------------------------------------------------------------------
-- Increment pulse counter to pulse width value.
--
......@@ -255,61 +263,61 @@ begin
-- 2. three cycle delay in clock sync FFs
-- 3. one cycle delay due to reset in next state
--
-- No clock cycle delay for switching from ST_IDLE to ST_GEN_GF_ON,
-- since pulse is already generated on rising edge of trig_i
-- No clock cycle delay for switching from IDLE to GEN_GF_ON,
-- since pulse is already generated on rising edge of trig_a_i
---------------------------------------------------------------------
when ST_GEN_GF_OFF =>
when GEN_GF_OFF =>
pulse_cnt <= pulse_cnt + 1;
if (pulse_cnt = c_pulse_width_gf_off) then
state <= ST_REJ_GF_OFF;
if (pulse_cnt = c_max_gen_gf_off) then
state <= REJ_GF_OFF;
end if;
---------------------------------------------------------------------
-- ST_REJ_GF_OFF
-- REJ_GF_OFF
---------------------------------------------------------------------
-- Increment pulse counter to pulse rejection value, while keeping
-- the pulse_rst high. Max pulse rejection value is 5x that of
-- pulse width value, to enable 1/5 duty cycle.
---------------------------------------------------------------------
when ST_REJ_GF_OFF =>
when REJ_GF_OFF =>
pulse_rst <= '1';
pulse_cnt <= pulse_cnt + 1;
if (pulse_cnt = c_pulse_rej_gf_off) then
state <= ST_IDLE;
if (pulse_cnt = c_max_rej_gf_off) then
state <= IDLE;
end if;
---------------------------------------------------------------------
-- ST_GEN_GF_ON
-- GEN_GF_ON
---------------------------------------------------------------------
-- Increment counter to pulse width value and generate glitch-filtered
-- pulse while incrementing.
--
-- Max value: g_pwidth-1, since pulse_cnt starts from 0
---------------------------------------------------------------------
when ST_GEN_GF_ON =>
when GEN_GF_ON =>
pulse_cnt <= pulse_cnt + 1;
pulse_gf_on <= '1';
if (pulse_cnt = c_pulse_width_gf_on) then
state <= ST_REJ_GF_ON;
if (pulse_cnt = c_max_gen_gf_on) then
state <= REJ_GF_ON;
end if;
---------------------------------------------------------------------
-- ST_REJ_GF_ON
-- REJ_GF_ON
---------------------------------------------------------------------
-- Increment pulse counter to pulse rejection value, while keeping
-- the pulse_rst high. Max pulse rejection value is 5x that of
-- pulse width value, to enable 1/5 duty cycle.
---------------------------------------------------------------------
when ST_REJ_GF_ON =>
when REJ_GF_ON =>
pulse_gf_on <= '0';
pulse_rst <= '1';
pulse_cnt <= pulse_cnt + 1;
if (pulse_cnt = c_pulse_rej_gf_on) then
state <= ST_IDLE;
if (pulse_cnt = c_max_rej_gf_on) then
state <= IDLE;
end if;
when others =>
state <= ST_IDLE;
state <= IDLE;
end case;
end if;
......
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