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Commit 00356b8c authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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vbcp_wb doc additions and small changes 

- added access commands subsection to VBCP protocol section
- added synthesis results section
- changed state machine naming (removed "ST_")
Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
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doc/vbcp_wb/vbcp_wb.pdf
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doc/vbcp_wb/vbcp_wb.tex
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......@@ -325,7 +325,7 @@ word 0 is sent first, followed by word 1 and so forth, until word 7.
\label{sec:implem}
In order to perform low-level I$^2$C transfers, the \textit{i2c\_slave} module
\textcolor{red}{REFERENCE?} is instantiated and used within the \textit{vbcp\_wb}
is instantiated and used within the \textit{vbcp\_wb}
module. The outputs of the \textit{i2c\_slave} module are used as controls
for an eight-state finite state machine (FSM), a simplified version of which
is shown in Figure~\ref{fig:fsm}. Table~\ref{tbl:fsm} also lists the states of
......@@ -346,27 +346,27 @@ the state machine.
\hline
\multicolumn{1}{c}{\textbf{State}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
ST\_IDLE & Wait for the \textit{i2c\_slave} module to receive the VBCP
address and go to \textit{ST\_WB\_ADR}. The starting value at the
IDLE & Wait for the \textit{i2c\_slave} module to receive the VBCP
address and go to \textit{WB\_ADR}. The starting value at the
\textit{op\_o} output of the \textit{i2c\_slave} module is stored
for checking in \textit{ST\_OP} \\
ST\_WB\_ADR & Shift in the two address bytes sent via VBCP and go to
\textit{ST\_SIM\_WB\_TRANSF} \\
ST\_SIM\_WB\_TRANSF & Start a Wishbone read transfer from address received in previous
state and go to \textit{ST\_OP} if Wishbone address exists (Wishbone
\textit{ack} received), or \textit{ST\_IDLE} otherwise (Wishbone \textit{err}
for checking in \textit{OP} \\
WB\_ADR & Shift in the two address bytes sent via VBCP and go to
\textit{SIM\_WB\_TRANSF} \\
SIM\_WB\_TRANSF & Start a Wishbone read transfer from address received in previous
state and go to \textit{OP} if Wishbone address exists (Wishbone
\textit{ack} received), or \textit{IDLE} otherwise (Wishbone \textit{err}
received) \\
ST\_OP & Check the \textit{op\_o} output of the \textit{i2c\_slave} module.
If different from the value at the start, go to \textit{ST\_SYSMON\_RD\_WB} state
OP & Check the \textit{op\_o} output of the \textit{i2c\_slave} module.
If different from the value at the start, go to \textit{SYSMON\_RD\_WB} state
(SysMon is reading from \textit{vbcp\_wb}), otherwise continue shifting
in bytes (SysMon writing to \textit{vbcp\_wb}) \\
ST\_SYSMON\_WR & Continue reading up to four bytes sent by the SysMon and go to
\textit{ST\_SYSMON\_WR\_WB}\\
ST\_SYSMON\_WR\_WB & Perform a Wishbone write transfer to the register with the address obtained in
\textit{ST\_WB\_ADR} \\
ST\_SYSMON\_RD\_WB & Perform a Wishbone read transfer from the address obtained in
\textit{ST\_WB\_ADR} and go to \textit{ST\_SYSMON\_RD} \\
ST\_SYSMON\_RD & Shift out the four bytes of the Wishbone register when the \textit{i2c\_slave}
SYSMON\_WR & Continue reading up to four bytes sent by the SysMon and go to
\textit{SYSMON\_WR\_WB}\\
SYSMON\_WR\_WB & Perform a Wishbone write transfer to the register with the address obtained in
\textit{WB\_ADR} \\
SYSMON\_RD\_WB & Perform a Wishbone read transfer from the address obtained in
\textit{WB\_ADR} and go to \textit{SYSMON\_RD} \\
SYSMON\_RD & Shift out the four bytes of the Wishbone register when the \textit{i2c\_slave}
module successfully finishes a write \\
\hline
\end{tabular}
......@@ -374,47 +374,70 @@ the state machine.
\end{table}
When the \textit{i2c\_slave} module finishes a transfer (signaled by a \textit{done\_p\_o} pulse),
the status is checked and if it is as expected (e.g., a \textit{address good} in the
\textit{ST\_IDLE} state), the FSM advances to the next state. It should be noted that where the
SysMon appears in the state names, it indicates what the SysMon action is. For example, if the state
of the FSM is \textit{ST\_SYSMON\_WR}, this means the SysMon is writing and the \textit{vbcp\_wb}
is reading.
the status is checked and if it is as expected (e.g., \textit{address good} while in the
\textit{IDLE} state), the FSM advances to the next state. Where the SysMon appears in the state
names, it indicates what the SysMon action is. For example, if the state of the FSM is
\textit{SYSMON\_WR}, this means the SysMon is writing and the \textit{vbcp\_wb} is reading.
To better understand how the FSM operates, Figures \ref{fig:sysmon-wr-fsm} and
\ref{fig:sysmon-rd-fsm} can be consulted, where the state of the FSM is shown
during reads and writes from the SysMon.
When the SysMon writes (Figure~\ref{fig:sysmon-wr-fsm}), the
\textit{vbcp\_wb} module waits in the \textit{ST\_IDLE} state until
the I$^2$C address is received, then, while in the \textit{ST\_WB\_ADR} state,
\textit{vbcp\_wb} module waits in the \textit{IDLE} state until
the I$^2$C address is received, then, while in the \textit{WB\_ADR} state,
it shifts in the Wishbone address. A Wishbone transfer is then simulated with
the received the address and if this address exists (a Wishbone \textit{ack}
is received), the first byte is shifted in while in the \textit{ST\_OP} state,
followed by the next three bytes while in the \textit{ST\_SYSMON\_WR} state.
Finally, the register is written to in the \textit{ST\_SYSMON\_WR\_WB} state.
is received), the first byte is shifted in while in the \textit{OP} state,
followed by the next three bytes while in the \textit{SYSMON\_WR} state.
Finally, the register is written to in the \textit{SYSMON\_WR\_WB} state.
When the SysMon reads (Figure~\ref{fig:sysmon-rd-fsm}), the first few
steps are the same as for a read. The address is shifted in and
checked in the Wishbone transfer simulation state. In the case of a SysMon
reading from a board, however, the I$^2$C transfer is restarted and the order
is reversed (SysMon starts reading). Thus, while in \textit{ST\_OP}, the FSM
is reversed (SysMon starts reading). Thus, while in \textit{OP}, the FSM
detects a different value of \textit{op\_o} and goes into the
\textit{ST\_SYSMON\_RD\_WB} state. The value of the register is read here and
sent via VBCP in the \textit{ST\_SYSMON\_RD} state.
\textit{SYSMON\_RD\_WB} state. The value of the register is read while in this
state, and sent via VBCP in the \textit{SYSMON\_RD} state.
\pagebreak
\begin{figure}[h]
\centerline{\includegraphics[width=.9\textwidth]{fig/sysmon-wr-fsm}}
\centerline{\includegraphics[width=\textwidth]{fig/sysmon-wr-fsm}}
\caption{FSM states when the SysMon writes to the \textit{vbcp\_wb}}
\label{fig:sysmon-wr-fsm}
\end{figure}
\begin{figure}[h]
\centerline{\includegraphics[width=.9\textwidth]{fig/sysmon-rd-fsm}}
\centerline{\includegraphics[width=\textwidth]{fig/sysmon-rd-fsm}}
\caption{FSM states when the SysMon reads from the \textit{vbcp\_wb}}
\label{fig:sysmon-rd-fsm}
\end{figure}
%==============================================================================
% SEC: Synthesis results
%==============================================================================
\section{Synthesis results}
\label{sec:synth-res}
The synthesis results for the \textit{vbcp\_wb} design using \textit{xst}
on the Spartan-6 XC6SLX45T are shown in Table~\ref{tbl:synth-res}.
\begin{table}[h]
\caption{Synthesis results}
\label{tbl:synth-res}
\centerline{
\begin{tabular}{l c c c}
\hline
\multicolumn{1}{c}{\textbf{Resource}} & \textbf{Used} & \textbf{Available} & \textbf{\%} \\
\hline
Slices & 76 & 6822 & 1.1 \\
Slice registers & 172 & 54576 & 0.3 \\
LUTs & 151 & 27288 & 0.6 \\
\hline
\end{tabular}
}
\end{table}
%==============================================================================
% Bibliography
%==============================================================================
......
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