sim/conv_pulse_gen/testbench.vhd · 80e35812ae9387dd73948e5a78f20d5eda51abe2 · Projects / Conv TTL Blocking - Gateware · Open Hardware Repository

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hdl: Added simulation files and projects · 80e35812
Theodor-Adrian Stana authored Jan 30, 2014
```
- conv_pulse_gen
- conv_man_trig
Signed-off-by: Theodor Stana <t.stana@cern.ch>
```
80e35812

testbench.vhd 6.39 KB