testbench_burst_ctrl.vhd 7.36 KB
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 --==============================================================================
-- CERN (BE-CO-HT)
-- Testbench for CONV-BURST_CTRL design
--==============================================================================
--
-- author: Denia Bouhired (denia.bouhired@cern.ch)
--
-- date of creation: 20-09-2016
--
-- version: 1.0
--
-- description:
--    Simulation testbench for the new burst mode module to run in as part of the
--    CONV-TTL-BLO common gateware.
--      
--
-- dependencies:
--    None.
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
--    20-09-2016   Denia Bouhired     File created

--==============================================================================
-- TODO: -
--==============================================================================

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use std.textio.all;


--use work.gencores_pkg.all;
--use work.wishbone_pkg.all;

-- use work.conv_common_gw_pkg.all;

entity testbench is
end entity testbench;

architecture behav of testbench is


  -- Clock periods
  constant c_clk_20_per   : time := 50 ns;
  constant random_intervals : boolean := false;
  component conv_burst_ctrl is
  generic
  (
  
  g_pwidth : natural range 1 to 10 		:= 5; 
  g_duty_cycle_div : natural 			:= 200;
  g_max_burst_len : natural				:= 1000;
  g_burst_timeout : natural 			:= 60000
  
  );
  port
  (
  
    clk_i        : in  std_logic;
    rst_n_i      : in  std_logic;
	
	en_i         	 	: in  std_logic;
	pulse_burst_i 		: in std_logic;
	pulse_burst_o		: out std_logic;
	
	burst_err_p_o : out std_logic	
  
  );
  end component conv_burst_ctrl;
  
  
  
  component conv_dyn_burst_ctrl is
	generic
	(
		g_pwidth : natural range 2 to 40 	:= 5; 
		-- Duty cycle divider: D = 1/g_duty_cycle_div
		g_duty_cycle_div : natural 			:= 18;
		g_1_pulse_energ			:in integer := 10;
		g_max_temp_rise			:in integer := 1000
	);
	port
	(
    -- Clock and active-low reset inputs
    clk_i        	: in  std_logic;
    rst_n_i      	: in  std_logic;
	
	-- Enable input, pulse generation is enabled when '1'
    en_i         	 	: in  std_logic;
	pulse_burst_i 		: in std_logic;
	
	temp_rise_c			: out integer;
	pulse_burst_o		: out std_logic;
	
	-- Burst error output, pulses high for one clock cycle when a pulse arrives
    -- within a burst rejection phase
    burst_err_p_o : out std_logic	
	
	);
  end component conv_dyn_burst_ctrl;
  
  
  -- Signal declarations
  
  signal clk_20			: std_logic;
  signal rst			: std_logic;
  
  signal en				: std_logic;
  signal burst_train	: std_logic;
  --signal burst_train_dyn	: std_logic;
  signal burst_train_regulated : std_logic;
  signal burst_train_regulated_dyn : std_logic;
  signal temp_rise_counter : integer;
  signal rand_num 		: integer := 0;
  --==============================================================================
--  architecture begin
--==============================================================================

  begin
  

  
 -- ============================================================================
  --Instantiate the DUT: Burst controller averaged over 1000 pulses
  --============================================================================
  -- cmp_dut_1 : conv_burst_ctrl
  -- generic map
  -- (
  -- g_pwidth => 5, 
  -- g_duty_cycle_div => 100,
  -- g_max_burst_len => 3,
  -- g_burst_timeout => 50000
  -- )
  -- port map(
  -- clk_i			=> clk_20,
  -- rst_n_i		=> not rst,
  
  -- en_i				=> en,
  -- pulse_burst_i		=> burst_train,
  
  -- pulse_burst_o		=> burst_train_regulated,
  -- burst_err_p_o		=> open
  
  -- );
  
   -- burst_train_dyn <= burst_train;
    --============================================================================
  -- Instantiate the DUT: Dynamic
  --============================================================================
  cmp_dut_2 : conv_dyn_burst_ctrl
  generic map
  (
  g_pwidth 					=> 5, 
  g_duty_cycle_div			=> 20,
  g_1_pulse_energ			=> 20,
  g_max_temp_rise			=> 60
  )
  port map(
  clk_i			=> clk_20,
  rst_n_i		=> not rst,
  
  en_i				=> en,
  pulse_burst_i		=> burst_train,
  
  pulse_burst_o		=> burst_train_regulated,
  temp_rise_c		=> temp_rise_counter,
  burst_err_p_o		=> open
  
  );
  
  
   --============================================================================
-- Generate clock signals
--============================================================================
  p_clk_20 : process
  begin
    clk_20 <= '0';
    wait for c_clk_20_per/2;
    clk_20 <= '1';
    wait for c_clk_20_per/2;
  end process p_clk_20;
  --============================================================================ 
  -- Random number generator
   --============================================================================
 p_ran_gen : process 
    variable seed1, seed2: positive := 1;               -- seed values for random generator
    variable rand: real;   -- random real-number value in range 0 to 1.0  
    variable range_of_rand : real := 10000.0;    -- the range of random values created will be 0 to +1000.
begin

    uniform(seed1, seed2, rand);   -- generate random number
    rand_num <= integer(rand*range_of_rand);  -- rescale to 0..1000, convert integer part 
    wait for 1000 ns;
end process p_ran_gen;


  
  process 
  begin
 
	rst <= '0';
	wait for 2500 ns;
	rst <= '1';
	wait for 2000 ns;
	rst <= '0';
	wait;
  end process;  
  
  process 
  begin
	en <= '0';
	wait for 1500 ns;
	en <= '1';
	wait;
  end process; 
  
  
  --============================================================================
  -- Pulse stimuli
  --============================================================================
  
  p_stim_burst : process
    variable interval	: time;-- := 1000 ns;
  begin
  while true loop
	if random_intervals then
		interval := rand_num * 1 ns;
	else	
		interval := 500 ns;
	end if;
	burst_train <= '0';
	wait for interval;
	burst_train <= '1';
	wait for 250 ns;
	burst_train <= '0';
  end loop;  
   
  end process p_stim_burst;
  
  
  p_write_output : process (temp_rise_counter)
  file F 	 : text open write_mode is "\\cern.ch\dfs\Users\d\debouhir\Documents\Projects\CONV-TTL-BlO\repo\conv-ttl-blo-gw\sim\Release\temp_rise_counter.txt";
  variable L : line;
  begin
	write (L, NOW, left, 10);
	write (L, temp_rise_counter, left, 6);
	writeline (F, L);
  end process p_write_output;
  
  end architecture behav;
--==============================================================================
--  architecture end
--==============================================================================