--==============================================================================
-- CERN (BE-CO-HT)
-- Wishbone registers for xil_multiboot design
--==============================================================================
--
-- author: auto-generated by wbgen2 from conv_regs.wb and modified by
--         Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-08-19
--
-- version: 1.0
--
-- description:
--    Implements the registers and Wishbone interface for the MultiBoot design.
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
--    2013-08-19   Theodor Stana     t.stana@cern.ch     File created
--==============================================================================
-- TODO: - 
--==============================================================================

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity multiboot_regs is
  port (
    -- Clock and reset inputs
    rst_n_i            : in     std_logic;
    clk_sys_i          : in     std_logic;

    -- Wishbone ports
    wb_adr_i           : in     std_logic_vector(2 downto 0);
    wb_dat_i           : in     std_logic_vector(31 downto 0);
    wb_dat_o           : out    std_logic_vector(31 downto 0);
    wb_cyc_i           : in     std_logic;
    wb_sel_i           : in     std_logic_vector(3 downto 0);
    wb_stb_i           : in     std_logic;
    wb_we_i            : in     std_logic;
    wb_ack_o           : out    std_logic;
    wb_stall_o         : out    std_logic;

    -- Fields of control register
    multiboot_cr_rdcfgreg_o   : out    std_logic;
    multiboot_cr_cfgregadr_o  : out    std_logic_vector(5 downto 0);
    multiboot_cr_iprog_o      : out    std_logic;

    -- Fields of status register
    multiboot_sr_cfgreg_img_i : in std_logic_vector(15 downto 0);
    multiboot_sr_valid_i      : in std_logic;

    -- Fields of bitstream address registers
    multiboot_gbbar_o      : out std_logic_vector(31 downto 0);
    multiboot_mbbar_o      : out std_logic_vector(31 downto 0);

    -- Fields of FAR register
    multiboot_far_data_i   : in  std_logic_vector(23 downto 0);
    multiboot_far_data_o   : out std_logic_vector(23 downto 0);
    multiboot_far_nbytes_o : out std_logic_vector(1 downto 0);
    multiboot_far_xfer_o   : out std_logic;
    multiboot_far_cs_o     : out std_logic;
    multiboot_far_ready_i  : in  std_logic
  );
end multiboot_regs;

architecture behav of multiboot_regs is

signal multiboot_cr_rdcfgreg_int    : std_logic;
signal multiboot_cr_cfgregadr_int   : std_logic_vector(5 downto 0);
signal multiboot_cr_iprog_int       : std_logic;
signal multiboot_cr_iprog_unl_int   : std_logic;
signal multiboot_cr_flr_int         : std_logic;
signal multiboot_cr_flw_int         : std_logic;
signal multiboot_sr_cfgreg_img_int  : std_logic_vector(15 downto 0);
signal multiboot_sr_valid_int       : std_logic;
signal multiboot_sr_flrrdy_int      : std_logic;
signal multiboot_sr_flwrdy_int      : std_logic;
signal multiboot_gbbar_int          : std_logic_vector(31 downto 0);
signal multiboot_mbbar_int          : std_logic_vector(31 downto 0);
signal multiboot_flrdr_int          : std_logic_vector(31 downto 0);
signal multiboot_flwdr_int          : std_logic_vector(31 downto 0);
signal multiboot_far_data_load_int  : std_logic;
signal multiboot_far_data_int       : std_logic_vector(23 downto 0);
signal multiboot_far_nbytes_int     : std_logic_vector(1 downto 0);
signal multiboot_far_xfer_int       : std_logic;
signal multiboot_far_cs_int         : std_logic;
signal multiboot_far_ready_int      : std_logic;
signal ack_sreg                     : std_logic_vector(1 downto 0);
signal rddata_reg                   : std_logic_vector(31 downto 0);
signal wrdata_reg                   : std_logic_vector(31 downto 0);
signal rwaddr_reg                   : std_logic_vector(2 downto 0);
signal ack_in_progress              : std_logic;

begin

-- Some internal signals assignments.
  wrdata_reg <= wb_dat_i;
  rwaddr_reg <= wb_adr_i;

  multiboot_sr_cfgreg_img_int <= multiboot_sr_cfgreg_img_i;
  multiboot_sr_valid_int      <= multiboot_sr_valid_i;

  multiboot_far_ready_int     <= multiboot_far_ready_i;

-- Main register bank access process.
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      ack_sreg                    <= (others => '0');
      ack_in_progress             <= '0';
      rddata_reg                  <= (others => '0');
      multiboot_cr_rdcfgreg_int   <= '0';
      multiboot_cr_cfgregadr_int  <= (others => '0');
      multiboot_cr_iprog_int      <= '0';
      multiboot_cr_iprog_unl_int  <= '0';
      multiboot_gbbar_int         <= (others => '0');
      multiboot_mbbar_int         <= (others => '0');
      multiboot_far_nbytes_int    <= "00";
      multiboot_far_data_int      <= (others => '0');
      multiboot_far_cs_int        <= '0';
      multiboot_far_xfer_int      <= '0';
    elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
      ack_sreg(0) <= ack_sreg(1);
      ack_sreg(1) <= '0';
      if (ack_in_progress = '1') then
        multiboot_cr_rdcfgreg_int  <= '0';
        multiboot_far_xfer_int      <= '0';
        if (ack_sreg(0) = '1') then
          ack_in_progress <= '0';
        else
        end if;
      else
        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
          case rwaddr_reg is
          when "000" => 
            if (wb_we_i = '1') then
              multiboot_cr_cfgregadr_int <= wrdata_reg(5 downto 0);
              multiboot_cr_rdcfgreg_int  <= wrdata_reg(6);
              multiboot_cr_iprog_unl_int <= wrdata_reg(16);
              if (multiboot_cr_iprog_unl_int = '1') then
                multiboot_cr_iprog_int <= wrdata_reg(17);
              end if;
            end if;
            rddata_reg(5 downto 0) <= multiboot_cr_cfgregadr_int;
            rddata_reg(6) <= multiboot_cr_rdcfgreg_int;
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= multiboot_cr_iprog_unl_int;
            rddata_reg(17) <= multiboot_cr_iprog_int;
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "001" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(15 downto 0) <= multiboot_sr_cfgreg_img_int;
            rddata_reg(16) <= multiboot_sr_valid_int;
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "010" =>
            if (wb_we_i = '1') then
              multiboot_gbbar_int <= wrdata_reg;
            end if;
            rddata_reg <= multiboot_gbbar_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "011" =>
            if (wb_we_i = '1') then
              multiboot_mbbar_int <= wrdata_reg;
            end if;
            rddata_reg <= multiboot_mbbar_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "100" =>
            if (wb_we_i = '1') then
              multiboot_far_data_int   <= wrdata_reg(23 downto 0);
              multiboot_far_nbytes_int <= wrdata_reg(25 downto 24);
              multiboot_far_xfer_int   <= wrdata_reg(26);
              multiboot_far_cs_int     <= wrdata_reg(27);
            end if;
            rddata_reg(23 downto 0) <= multiboot_far_data_i;
            rddata_reg(25 downto 24) <= multiboot_far_nbytes_int;
            rddata_reg(26) <= multiboot_far_xfer_int;
            rddata_reg(27) <= multiboot_far_cs_int;
            rddata_reg(28) <= multiboot_far_ready_int;
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when others =>
-- prevent the slave from hanging the bus on invalid address
            ack_in_progress <= '1';
            ack_sreg(0) <= '1';
          end case;
        end if;
      end if;
    end if;
  end process;
  
  
-- Drive the data output bus
  wb_dat_o <= rddata_reg;

-- Drive the stall line
  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);

-- Configuration register address
  multiboot_cr_cfgregadr_o <= multiboot_cr_cfgregadr_int;

-- Read configuration register
  multiboot_cr_rdcfgreg_o <= multiboot_cr_rdcfgreg_int;

-- IPROG
  multiboot_cr_iprog_o <= multiboot_cr_iprog_int;

-- GBBAR
  multiboot_gbbar_o <= multiboot_gbbar_int;

-- MBBAR
  multiboot_mbbar_o <= multiboot_mbbar_int;

-- FAR outputs
  multiboot_far_data_o      <= multiboot_far_data_int; --wrdata_reg(23 downto 0);
  multiboot_far_nbytes_o    <= multiboot_far_nbytes_int;
  multiboot_far_xfer_o      <= multiboot_far_xfer_int;
  multiboot_far_cs_o        <= multiboot_far_cs_int;

  -- ACK signal generation. Just pass the LSB of ACK counter.
  wb_ack_o <= ack_sreg(0);

end behav;
