conv_regs.wb
============

If you change the FIFO width in the top-level conv_ttl_blo.vhd, you need to
also change the width of the USEDW field.


conv_regs.vhd
=============

You need to make some changes to this file after EVERY RUN of wbgen2:

1. Add the following output port declaration after the reg_tbmr_wrtag_i port:

-- Tag buffer read request, asserted when reading from TBMR
    reg_tb_rd_req_p_o                        : out    std_logic;

2. Assign the port FOUR TIMES in the register bank process:

    -- Main register bank access process.
      process (clk_sys_i, rst_n_i)
      begin
        if (rst_n_i = '0') then 
          -- [...]
          reg_tb_rd_req_p_o <= '0';
        elsif rising_edge(clk_sys_i) then
    -- advance the ACK generator shift register
          ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
          ack_sreg(9) <= '0';
          if (ack_in_progress = '1') then
            if (ack_sreg(0) = '1') then
              -- [...]
              reg_tb_rd_req_p_o <= '0';
              ack_in_progress <= '0';
            else
              -- [...]
              reg_tb_rd_req_p_o <= '0';
            end if;
          else
            if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
              case rwaddr_reg(3 downto 0) is
              [...]
              when "1011" => 
                if (wb_we_i = '1') then
                end if;
                reg_tb_rd_req_p_o <= '1';
                rddata_reg(5 downto 0) <= reg_tbmr_chan_i;
                rddata_reg(31) <= reg_tbmr_wrtag_i;
              [...]

