pax_global_header 0000666 0000000 0000000 00000000064 12314554267 0014523 g ustar 00root root 0000000 0000000 52 comment=cc71e6a067afafcef42a5be4a3f837fad8777f7c
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/ 0000775 0000000 0000000 00000000000 12314554267 0022135 5 ustar 00root root 0000000 0000000 conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/.gitignore 0000664 0000000 0000000 00000000024 12314554267 0024121 0 ustar 00root root 0000000 0000000 captures/
sw/
*.bak
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/.gitmodules 0000664 0000000 0000000 00000000171 12314554267 0024311 0 ustar 00root root 0000000 0000000 [submodule "ip_cores/general-cores"]
path = ip_cores/general-cores
url = git://ohwr.org/hdl-core-lib/general-cores.git
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/doc/ 0000775 0000000 0000000 00000000000 12314554267 0022702 5 ustar 00root root 0000000 0000000 conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/doc/hdlguide/ 0000775 0000000 0000000 00000000000 12314554267 0024467 5 ustar 00root root 0000000 0000000 conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/doc/hdlguide/Makefile 0000664 0000000 0000000 00000000611 12314554267 0026125 0 ustar 00root root 0000000 0000000 FILE=hdlguide-conv-ttl-blo
all:
$(MAKE) -C fig
pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
bibtex $(FILE).aux
pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
evince $(FILE).pdf &
clean:
$(MAKE) -C fig clean
rm -rf *.aux *.dvi *.log $(FILE).pdf *.lof *.lot *.out *.toc *.bbl *.blg *.gz
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/doc/hdlguide/README.txt 0000664 0000000 0000000 00000000205 12314554267 0026162 0 ustar 00root root 0000000 0000000 Type 'make' to create your .pdf documentation file.
You need Inkscape to make the documentation files:
sudo apt-get install inkscape conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/doc/hdlguide/cern-title.tex 0000664 0000000 0000000 00000001314 12314554267 0027256 0 ustar 00root root 0000000 0000000 \begin{titlepage}
\vspace*{3cm}
%---------------------------------------------------------------
% name
%---------------------------------------------------------------
\noindent{\LARGE \textbf{CONV-TTL-BLO HDL Guide}}
\noindent \rule{\textwidth}{.1cm}
\hfill Gateware v2.0
\hfill February 14, 2014
\vspace*{3cm}
\begin{figure}[h]
\includegraphics[height=3cm]{fig/cern-logo}
\hfill
\includegraphics[height=3cm]{fig/ohwr-logo}
\end{figure}
\vfill
%---------------------------------------------------------------
% name
%---------------------------------------------------------------
\noindent {\Large \textbf{Theodor-Adrian Stana (CERN/BE-CO-HT)}}
\noindent \rule{\textwidth}{.05cm}
\end{titlepage}
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/doc/hdlguide/conv-regs.tex 0000664 0000000 0000000 00000054571 12314554267 0027130 0 ustar 00root root 0000000 0000000 \subsection{Converter board registers}
\label{app:conv-regs}
Base address: 0x000
{
\rowcolors{2}{white}{gray!25}
\begin{longtable}{l l l p{.45\textwidth}}
\hline
\textbf{Offset} & \textbf{Default} & \textbf{Name}
& \textbf{Description} \\
\hline
\endfirsthead
\hline
\hline
\endhead
\hline
\endfoot
0x0 & 0x54424c4f & BIDR & Board ID Register\\
0x4 & Undefined (1) & SR & Status Register\\
0x8 & 0x00000000 & CR & Control Register\\
0xc & 0x00000000 & CH1PCR & Channel 1 Pulse Counter Register\\
0x10 & 0x00000000 & CH2PCR & Channel 2 Pulse Counter Register\\
0x14 & 0x00000000 & CH3PCR & Channel 3 Pulse Counter Register\\
0x18 & 0x00000000 & CH4PCR & Channel 4 Pulse Counter Register\\
0x1c & 0x00000000 & CH5PCR & Channel 5 Pulse Counter Register\\
0x20 & 0x00000000 & CH6PCR & Channel 6 Pulse Counter Register\\
0x24 & 0x00000000 & TVLR & Time Value Low Register\\
0x28 & 0x00000000 & TVHR & Time Value High Register\\
0x2c & 0x00000000 & TFMR & Tag FIFO Meta Register\\
0x30 & 0x00000000 & TFCYR & Tag FIFO Cycles Register \\
0x34 & 0x00000000 & TFTLR & Tag FIFO TAI Low Register \\
0x38 & 0x00000000 & TFTHR & Tag FIFO TAI High Register \\
0x3c & 0x00020000 & TFCSR & Tag FIFO Control and Status Register \\
\end{longtable}
}
\noindent Note 1: The SR is undefined on startup due to the fact that the
gateware version, switches and RTM fields may have different values.
\vspace{11pt}
\subsubsection{BIDR -- Board ID Register}
\label{app:conv-regs-bidr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
BITS
} [\emph{read-only}]: ID register bits
\\
Reset value: 0x54424c4f
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{SR -- Status Register}
\label{app:conv-regs-sr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c|}{\cellcolor{gray!25}WRPRES} & \multicolumn{1}{|c|}{\cellcolor{gray!25}I2C\_WDTO} & \multicolumn{6}{|c|}{\cellcolor{gray!25}RTM[5:0]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}SWITCHES[7:0]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}GWVERS[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
GWVERS
} [\emph{read-only}]: Gateware version
\\
Leftmost nibble hex value is major release decimal value \\ Rightmost nibble hex value is minor release decimal value \\ e.g. \\ 0x11 -- v1.1 \\ 0x1e -- v1.14 \\ 0x20 -- v2.0
\end{small}
\item \begin{small}
{\bf
SWITCHES
} [\emph{read-only}]: Status of on-board switches
\\
0 -- switch is ON \\ 1 -- switch is OFF \\ bit 0 -- SW1.1 \\ bit 1 -- SW1.2 \\ ... \\ bit 4 -- SW2.1 \\ ... \\ bit 7 -- SW2.4
\end{small}
\item \begin{small}
{\bf
RTM
} [\emph{read-only}]: RTM detection lines~\cite{rtm-det}
\\
0 -- line active \\ 1 -- line inactive
\end{small}
\item \begin{small}
{\bf
I2C\_WDTO
} [\emph{read/write}]: Communication watchdog timer status
\\
1 -- timeout occured \\ 0 -- no timeout \\ This bit can be cleared by writing a '1' to it
\end{small}
\item \begin{small}
{\bf
WRPRES
} [\emph{read-only}]: White Rabbit present
\\
1 -- White Rabbit present \\ 0 -- White Rabbit not present
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CR -- Control Register}
\label{app:conv-regs-cr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & \multicolumn{2}{|c|}{\cellcolor{gray!25}MPT[7:6]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{6}{|c|}{\cellcolor{gray!25}MPT[5:0]} & \multicolumn{1}{|c|}{\cellcolor{gray!25}RST} & \multicolumn{1}{|c|}{\cellcolor{gray!25}RST\_UNLOCK}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
RST\_UNLOCK
} [\emph{read/write}]: Reset unlock bit
\\
1 - Reset bit unlocked \\ 0 - Reset bit locked
\end{small}
\item \begin{small}
{\bf
RST
} [\emph{read/write}]: Reset bit
\\
1 - initiate logic reset \\ 0 - no reset
\end{small}
\item \begin{small}
{\bf
MPT
} [\emph{write-only}]: Manual Pulse Trigger
\\
Write the following sequence to trigger a pulse: \\ 0xde -- Byte 1 of magic sequence \\ 0xad -- Byte 2 of magic sequence \\ 0xbe -- Byte 3 of magic sequence \\ 0xef -- Byte 4 of magic sequence \\ Number in range 1..6 -- trigger a pulse
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH1PCR -- Channel 1 Pulse Counter Register}
\label{app:conv-regs-ch1pcr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1PCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1PCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1PCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1PCR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH1PCR
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH2PCR -- Channel 2 Pulse Counter Register}
\label{app:conv-regs-ch2pcr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2PCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2PCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2PCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2PCR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH2PCR
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH3PCR -- Channel 3 Pulse Counter Register}
\label{app:conv-regs-ch3pcr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3PCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3PCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3PCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3PCR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH3PCR
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH4PCR -- Channel 4 Pulse Counter Register}
\label{app:conv-regs-ch4pcr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4PCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4PCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4PCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4PCR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH4PCR
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH5PCR -- Channel 5 Pulse Counter Register}
\label{app:conv-regs-ch5pcr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5PCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5PCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5PCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5PCR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH5PCR
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH6PCR -- Channel 6 Pulse Counter Register}
\label{app:conv-regs-ch6pcr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6PCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6PCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6PCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6PCR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH6PCR
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{TVLR -- Time Value Low Register}
\label{app:conv-regs-tvlr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TVLR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TVLR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TVLR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TVLR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TVLR
} [\emph{read/write}]: TAI seconds counter bits 31..0
\\
Writing this field resets the internal cycles counter.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{TVHR -- Time Value High Register}
\label{app:conv-regs-tvhr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TVHR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TVHR
} [\emph{read/write}]: TAI seconds counter bits 39..32
\\
Writing this field resets the internal cycles counter.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\subsubsection{TFMR -- Tag FIFO Meta Register}
\label{app:conv-regs-tfmr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c|}{\cellcolor{gray!25}WRTAG} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{1}{|c}{-} & - & \multicolumn{6}{|c|}{\cellcolor{gray!25}CHAN[5:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CHAN
} [\emph{read-only}]: Channel mask
\\
Mask for the channel(s) that triggered time-tag storage: \\ bit 0 -- channel 1 \\ bit 1 -- channel 2 \\ ... \\ bit 5 -- channel 6
\end{small}
\item \begin{small}
{\bf
WRTAG
} [\emph{read-only}]: White Rabbit present
\\
1 - Current time tag generated with White Rabbit \\ 0 - Current time tag generated with internal counter
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\subsubsection{TFCYR -- Tag FIFO Cycles Register}
\label{app:conv-regs-tfcyr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{gray!25}CYC[27:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CYC[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CYC[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CYC[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CYC
} [\emph{read-only}]: Cycles counter
\\
Value of the 8-ns cycles counter when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\subsubsection{TFTLR -- Tag FIFO TAI Low Register }
\label{app:conv-regs-tftlr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI\_L[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI\_L[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI\_L[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI\_L[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TAI\_L
} [\emph{read-only}]: Lower part of TAI seconds counter
\\
Value of the TAI seconds counter bits 31..0 when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\subsubsection{TFTHR -- Tag FIFO TAI High Register}
\label{app:conv-regs-tfthr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI\_H[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TAI\_H
} [\emph{read-only}]: Upper part of TAI seconds counter
\\
Value of the TAI seconds counter bits 39..32 when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\subsubsection{TFCSR -- Tag FIFO Control and Status Register }
\label{app:conv-regs-tfcsr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}CLEAR\_BUS} & \multicolumn{1}{|c|}{\cellcolor{gray!25}EMPTY} & \multicolumn{1}{|c|}{\cellcolor{gray!25}FULL}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{1}{|c}{-} & \multicolumn{7}{|c|}{\cellcolor{gray!25}USEDW[6:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
FULL
} [\emph{read-only}]: FIFO full flag
\\
1: FIFO is full\\0: FIFO is not full
\end{small}
\item \begin{small}
{\bf
EMPTY
} [\emph{read-only}]: FIFO empty flag
\\
1: FIFO is empty\\0: FIFO is not empty
\end{small}
\item \begin{small}
{\bf
CLEAR\_BUS
} [\emph{write-only}]: FIFO clear
\\
write 1: clears FIFO \\write 0: no effect\\
Note that a clear will not delete the data in the FIFO, just bring the
read and write pointers at the same position.\\
\end{small}
\item \begin{small}
{\bf
USEDW
} [\emph{read-only}]: FIFO counter
\\
Number of data records currently being stored in FIFO.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
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author = {Simon Srot},
title = {{SPI Master Core Specification}},
year = 2004,
note = {\url{http://opencores.org/websvn,filedetails?repname=spi&path=%2Fspi%2Ftrunk%2Fdoc%2Fspi.pdf}}
}
@misc{i2c-master,
author = {Richard Herveille},
title = {{I$2$C Master Core Specification}},
year = 2003,
note = {\url{http://opencores.org/websvn,filedetails?repname=i2c&path=%2Fi2c%2Ftrunk%2Fdoc%2Fi2c_specs.pdf}}
}
@misc{coding-guidelines,
author = "Patrick Loschmidt and Nata{\v s}a Simani\'c and C\'esar Prados and Pablo Alvarez and Javier Serrano",
title = {{Guidelines for VHDL Coding}},
month = 04,
year = 2011,
note = {\url{http://www.ohwr.org/documents/24}}
}
@misc{ctb-ug,
author = "Theodor-Adrian Stana",
title = {{CONV-TTL-BLO User Guide}},
month = 06,
year = 2013,
howpublished = {\url{http://www.ohwr.org/documents/263}}
}
@misc{ctb-hwguide,
author = "Theodor-Adrian Stana",
title = {{CONV-TTL-BLO Hardware Guide}},
month = 07,
year = 2013,
howpublished = {\url{http://www.ohwr.org/documents/282}}
}
@misc{sysmon-i2c,
author = "{ELMA}",
title = {{Access to board data using SNMP and I2C}},
howpublished = {\url{www.ohwr.org/attachments/download/2324/ELMA_SNMP_specification.pdf}}
}
@misc{rtm-det,
title = {{Rear Transition Module detection}},
howpublished = {\url{http://www.ohwr.org/projects/conv-ttl-blo/wiki/RTM_board_detection}}
}
@misc{ug380,
title = {{UG380 - Spartan-6 Configuration Guide}},
author = {Xilinx},
month = jan,
year = {2013},
note = {v2.5},
howpublished = {\url{http://www.xilinx.com/support/documentation/user_guides/ug380.pdf}}
}
@misc{wbgen2,
title = {{Wishbone Slave Generator}},
howpublished = {\url{http://www.ohwr.org/projects/wishbone-gen/wiki}}
}
@misc{onewire-core,
author = {Iztok Jeras},
title = {{sockit\_owm, 1-wire (onewire) master}},
year = 2011,
note = {\url{http://opencores.org/websvn,filedetails?repname=sockit_owm&path=%2Fsockit_owm%2Ftrunk%2Fdoc%2Fsockit_owr.pdf}}
}
@misc{ds18b20,
author = {{Maxim Integrated}},
title = {{DS18B20 -- Programmable Resolution 1-Wire Digital Thermometer}},
note = {\url{http://datasheets.maximintegrated.com/en/ds/DS18B20.pdf}}
}
@misc{gencores-ohwr,
title = {{Platform-independent Core Collection webage on Open Hardware Repository}},
howpublished = {\url{http://www.ohwr.org/projects/general-cores/wiki}}
}
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/doc/hdlguide/hdlguide-conv-ttl-blo.tex 0000664 0000000 0000000 00000140106 12314554267 0031316 0 ustar 00root root 0000000 0000000 %==============================================================================
% Document header
%==============================================================================
\documentclass[a4paper,11pt]{article}
% Color package
\usepackage[usenames,dvipsnames,table]{xcolor}
% Hyperrefs
\usepackage[
colorlinks = true,
linkcolor = Mahogany,
citecolor = Mahogany,
urlcolor = blue,
]{hyperref}
% Longtable
\usepackage{longtable}
% Graphics, multirow
\usepackage{graphicx}
\usepackage{multirow}
% Appendix package
\usepackage[toc,page]{appendix}
\usepackage{fancyhdr}
\setlength{\headheight}{15.2pt}
\pagestyle{fancy}
\fancyhead[L]{\nouppercase{\leftmark}}
\fancyhead[R]{}
\renewcommand{\footrulewidth}{0.4pt}
% Row number command
\newcounter{rownr}
\newcommand{\rownumber}{\stepcounter{rownr}\arabic{rownr}}
%==============================================================================
% Start of document
%==============================================================================
\begin{document}
%------------------------------------------------------------------------------
% Title
%------------------------------------------------------------------------------
\include{cern-title}
%------------------------------------------------------------------------------
% Revision history
%------------------------------------------------------------------------------
\thispagestyle{empty}
\section*{Revision history}
\centerline
{
\rowcolors{2}{white}{gray!25}
\begin{tabular}{l c p{.6\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Date}} & \multicolumn{1}{c}{\textbf{Version}} & \multicolumn{1}{c}{\textbf{Change}} \\
\hline
04-07-2013 & 0.1 & First draft \\
26-07-2013 & 0.2 & Second draft \\
07-08-2013 & 1.02 & Added pulse rejection to \textit{conv\_pulse\_gen} \\
14-08-2013 & 1.02 & Changed name of \textit{elma\_i2c} to \textit{vbcp\_wb} \\
20-11-2013 & 1.04 & Added MultiBoot module, gateware release v1.0 \\
14-02-2014 & 2.00 & Version 2.0 of gateware, with diagnostics support including: unique board ID
and temperature readout, input pulse counters, pulse time-tagging and
manual pulse triggering. \\
\hline
\end{tabular}
}
\pagebreak
\pagenumbering{roman}
\setcounter{page}{1}
\tableofcontents
%------------------------------------------------------------------------------
% List of figs, tables, abbrevs
%------------------------------------------------------------------------------
\listoffigures
\listoftables
\section*{List of Abbreviations}
\begin{tabular}{l l}
DAC & Digital-to-Analog Converter \\
FPGA & Field-Programmable Gate Array \\
FF & Flip-Flop \\
FSM & Finite-State Machine \\
IC & Integrated Circuit \\
I$^2$C & Inter-Integrated Circuit (bus) \\
PLL & Phase-Locked Loop \\
RTM & Rear-Transition Module \\
SPI & Serial Peripheral Interface \\
SysMon & (ELMA) System Montior \\
VCXO & Voltage-controlled oscillator \\
WRPC & White-Rabbit PTP Core \\
\end{tabular}
\pagebreak
\pagenumbering{arabic}
\setcounter{page}{1}
%==============================================================================
% SEC: Intro
%==============================================================================
\section{Introduction}
\label{sec:intro}
This document details the HDL implemented on the Spartan-6 FPGA on the CONV-TTL-BLO
board. The HDL (mostly implemented in VHDL) handles the following aspects of
the CONV-TTL-BLO capabilities:
\begin{itemize}
\item pulse detection (on pulse rising edge)
\item fixed-width pulse generation with pulse rejection
\item diagnostics via I$^2$C
\begin{itemize}
\item converter board ID
\item gateware version
\item unique board ID and temperature readout
\item state of on-board switches and RTM detection lines
\item input pulse counters
\item input pulse time-tagging
\item manual pulse triggering
\end{itemize}
\item remote reprogramming via I$^2$C
\end{itemize}
Figure~\ref{fig:hdl-bd} shows a simplified block diagram of the HDL gateware. The
blocks in this figure implemented as part of the CONV-TTL-BLO gateware are presented
in the sections that follow.
\begin{figure}[h]
\centerline{\includegraphics[width=.9\textwidth]{fig/hdl-bd}}
\caption{Block diagram of FPGA gateware}
\label{fig:hdl-bd}
\end{figure}
%------------------------------------------------------------------------------
% SUBSEC: Additional doc
%------------------------------------------------------------------------------
\subsection*{Additional documentation}
\begin{itemize}
\item CONV-TTL-BLO User Guide \cite{ctb-ug}
\item CONV-TTL-BLO Hardware Guide \cite{ctb-hwguide}
\end{itemize}
%==============================================================================
% SEC: Clocks
%==============================================================================
\pagebreak
\section{FPGA clocks}
\label{sec:clocks}
There are two clock signals input to the FPGA (Figure~\ref{fig:clocks}).
The first is a 20~MHz signal from a VCXO. The second clock signal with a frequency
of 125~MHz is generated on-board via a Texas Instruments PLL IC from a 25~MHz VCXO.
Two DACs are provided on-board for controlling the two VCXOs. The DACs can be
controlled via SPI, and if White Rabbit is available, the White Rabbit PTP Core (WRPC)
can control these DACs to discipline these clocks.
Table~\ref{tbl:clocks} lists the clock domains used in the gateware.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/clocks}}
\caption{FPGA clock inputs}
\label{fig:clocks}
\end{figure}
\begin{table}[h]
\caption{Clock domains}
\label{tbl:clocks}
\centerline
{
\begin{tabular}{c c p{.6\textwidth}}
\hline
\textbf{Clock domain} & \textbf{Frequency} & \multicolumn{1}{c}{\textbf{Comments}} \\
\hline
\textit{clk\_20\_vcxo\_i} & 20~MHz & Global clock input to all sequential logic. \\
\textit{clk\_125} & 125~MHz & Time-tagging logic and WR reference clock. \\
\hline
\end{tabular}
}
\end{table}
%==============================================================================
% SEC: Mem-mapped periphs
%==============================================================================
\pagebreak
\section{Memory-mapped peripherals}
\label{sec:periphs}
This section details the various peripherals mapped on the internal
Wishbone bus. Access to these peripherals is made through the two serial lines
on the VME P1 connector (SERCLK, SERDAT). A protocol based on I$^2$C is used to
access these peripherals. The protocol, as well as the bridge component
translating I$^2$C accesses into Wishbone accesses, are defined in the bridge
component's documentation.
The complete memory map of the gateware can be found in Appendix~\ref{app:memmap}.
%------------------------------------------------------------------------------
% SUBSEC: Bridge
%------------------------------------------------------------------------------
\subsection{I$^2$C to Wishbone bridge}
\label{sec:i2c-bridge}
The \textit{wb\_i2c\_bridge} module implements a bridge to translate I$^2$C accesses
on the VME P1 connector into Wishbone accesses on the FPGA. The module provides
one I$^2$C slave interface for connecting to an ELMA SysMon and one Wishbone
master interface.
Details about the module's implementation can be found in its documentation.
%------------------------------------------------------------------------------
% SUBSEC: conv_regs
%------------------------------------------------------------------------------
\subsection{Converter board registers}
\label{sec:periphs-conv-regs}
A set of registers are implemented as general-purpose registers for converter boards.
These are status and control registers implemented utilizing \textit{wbgen2}~\cite{wbgen2}.
Appendix~\ref{app:conv-regs} presents the converter board registers.
On the status registers side, there is one general status register (SR -- see
Appendix~\ref{app:conv-regs-sr}) that contains details about the gateware version,
the state of the on-board switches and RTM detection lines, as well as the state
of the communication watchdog timer. Then, there are six pulse counter registers
(CHxPCR -- see Appendix~\ref{app:conv-regs}), one per each channel, which are updated
with the current values of the input pulse counters. These are followed by the
time-tagging logic (Section~\ref{sec:timetag}) registers.
The logic also contains one control register (CR -- see Appendix~\ref{app:conv-regs-cr}),
which contains two bits for remotely resetting the FPGA logic and six bits used by the
manual pulse triggering (Section~\ref{sec:man-trig}).
%------------------------------------------------------------------------------
% SUBSEC: MultiBoot
%------------------------------------------------------------------------------
\subsection{MultiBoot control}
\label{sec:periphs-multiboot}
The MultiBoot module offers the remote reprogramming capabilities for the
CONV-TTL-BLO board. It offers a set of registers for controlling writing a bitstream
to the M25P32 flash chip and for issuing the remote reprogramming command.
For information on the module, refer to its documentation. The memory map of the
module is also present in this manual, for quick reference (see
Appendix~\ref{app:multiboot-regs}).
%------------------------------------------------------------------------------
% SUBSEC: Onewire
%------------------------------------------------------------------------------
\subsection{One-wire master}
\label{sec:periphs-onewire}
The one-wire master provides access to the DS18B20 thermometer chip~\cite{ds18b20}
on the CONV-TTL-BLO. It provides two registers for software control of the module.
Note that the FPGA does not control the one-wire thermometer line in any way.
Accessing the thermometer is done through software only.
More details about how to access the one-wire master module can be found in its
documentation~\cite{onewire-core}.
%==============================================================================
% SEC: Reset gen
%==============================================================================
\pagebreak
\section{Reset generator}
\label{sec:reset-gen}
\centerline
{
\begin{tabular}{l l l}
\hline
\textbf{Entity} & \textit{reset\_gen} & \\
\textbf{Generics} & \textit{g\_reset\_time} & Reset time in \textit{clk\_i} cycles \\
\textbf{Ports} & \textit{clk\_i} & Clock signal \\
& \textit{rst\_i} & Active-high reset input \\
& \textit{rst\_n\_o} & Active-low reset output \\
\textbf{Usage} & Global reset generation & 100~$ms$ reset \\
\hline
\end{tabular}
}
\vspace*{11pt}
The reset generator module (\textit{reset\_gen}) implemented inside the FPGA
generates a predefined-width reset signal when power is applied to the FPGA, or
when an external reset is triggered via the \textit{rst\_i} pin.
When a power-on reset occurs on the Xilinx FPGA, a counter inside the \textit{reset\_gen}
module starts counting up. While this counter is counting up, the active-low reset signal
is kept low, resetting synchronous logic inside the FPGA. When the counter reaches the
value of the reset width (specified via the \textit{g\_reset\_time} generic), the reset
signal is de-asserted, the counter is disabled and the \textit{reset\_gen}
module remains inactive.
The module reactivates on the power-on reset, or when a reset is triggered externally, via
the \textit{rst\_i} pin. The \textit{rst\_i} pin is tied in the design to the second bit
in the control register (CR -- see Appendix~\ref{app:conv-regs-cr}), which has to be first
unlocked by writing the RST\_UNLOCK bit. Both these registers are implemented in the
top-level file of the design.
Note that the VHDL of this module is Xilinx and XST-specific and porting to a different
FPGA architecture is not guaranteed to provide the same results. The \textit{reset\_gen}
module has an initial value set for the counter signal after power-up, which is guaranteed
by XST to be set after the FPGA's GSR signal is de-asserted.
By default, the reset time is set to 100~$ms$.
%==============================================================================
% SEC: RTM detection
%==============================================================================
\pagebreak
\section{RTM detection}
\label{sec:rtm-detect}
\centerline
{
\begin{tabular}{l l l}
\hline
\textbf{Entity} & \textit{rtm\_detector} & \\
\textbf{Ports} & \textit{rtmm\_i(2..0)} & RTM mainboard detection lines \\
& \textit{rtmp\_i(2..0)} & RTM piggyback detection lines \\
& \textit{rtmm\_ok\_o} & RTM mainboard present \\
& \textit{rtmp\_ok\_o} & RTM piggyback present \\
\textbf{Usage} & Light ERR status LED & \\
\hline
\end{tabular}
}
\vspace*{11pt}
RTM detection is described in \cite{rtm-det}. Since an RTMM/P missing would mean
all \textit{rtmm\_i}/\textit{rtmp\_i} lines are all-ones, the \textit{rtm\_detector}
module sets the \textit{rtmm\_ok} and \textit{rtmp\_ok} signals low if the
\textit{rtmm\_i} and \textit{rtmp\_i} input signals are respectively all-ones.
The \textit{rtmm\_ok} and \textit{rtmp\_ok} signals are NANDed together to light
the ERR status LED on the CONV-TTL-BLO. The status of the RTM detection lines
can also be read via their respective fields in the converter board status register
(SR -- see Appendix~\ref{app:conv-regs-sr}).
\begin{figure}[h]
\centerline{\includegraphics[width=.76\textwidth]{fig/rtm-detect}}
\caption{\textit{rtm\_detector} block in CONV-TTL-BLO gateware}
\label{fig:rtm-detect}
\end{figure}
%==============================================================================
% SEC: Bicolor LEDs
%==============================================================================
\pagebreak
\section{Bicolor LED controller}
\label{sec:bicolor-led}
\centerline
{
\begin{tabular}{l l l}
\hline
\textbf{Entity} & \textit{bicolor\_led\_ctrl} & \\
\textbf{Generics} & \textit{g\_NB\_COLUMN} & Number of columns \\
& \textit{g\_NB\_LINE} & Number of lines \\
& \textit{g\_CLK\_FREQ} & Frequency (in Hz) of \textit{clk\_i} signal \\
& \textit{g\_REFRESH\_RATE} & LED refresh rate (in Hz)\\
\textbf{Ports} & \textit{rst\_n\_i} & Active-low reset input \\
& \textit{clk\_i} & Clock signal input \\
& \textit{led\_intensity\_i(6..0)} & 7-bit LED intensity vector \\
& \textit{led\_state\_i(..)} & LED state vector, two bits per LED \\
& \textit{column\_o(..)} & LED column vector, one bit per column \\
& \textit{line\_o(..)} & LED line vector, one bit per line \\
& \textit{line\_oen\_o(..)} & LED line enable vector, one bit per line\\
\textbf{Usage} & Light bicolor LEDS & \\
\hline
\end{tabular}
}
\vspace*{11pt}
The \textit{bicolor\_led\_ctrl} block controls the lighting of a bicolor
LED matrix. Based on the refresh rate given via the \textit{g\_REFRESH\_RATE}
generic, the clock frequency (\textit{g\_CLK\_FREQ} generic) and the number of
lines and columns, the module lights each LED in the LED matrix sequentially at
the refresh rate given by the user.
Figure~\ref{fig:bicolor-led} shows an example of controlling a three-line,
two-column red-and-green LED matrix. The FPGA ouputs for the columns~(C) are connected
to buffers and serial resistors and then to the LEDs. The FPGA outputs for lines~(L)
are connected to tri-state buffers and then to the LEDs. The FPGA outputs for line
output enables~(L\_OEN) are connected to the output enable of the tri-state buffers.
\begin{figure}[hbtp]
\centerline{\includegraphics[width=\textwidth]{fig/bicolor-led}}
\caption{3x2 bicolor LED matrix control}
\label{fig:bicolor-led}
\end{figure}
The two-bit \textit{led\_state\_i} vector can be used to control the color of each
LED. Table~\ref{tbl:bicolor-led-state} lists the values that should be input on
\textit{led\_state\_i} to get the needed color, as well as constant definitions
provided in the \textit{bicolor\_led\_ctrl\_pkg.vhd} file for setting the color of the LED
via \textit{led\_state\_i}.
\begin{table}[h]
\caption{LED state input}
\label{tbl:bicolor-led-state}
\centerline
{
\rowcolors{2}{white}{gray!25}
\begin{tabular}{l l c}
\hline
\multicolumn{1}{c}{\textbf{State}} & \multicolumn{1}{c}{\textbf{Constant}} & \textbf{Value} \\
\hline
Off & c\_LED\_OFF & 00 \\
Green & c\_LED\_GREEN & 01 \\
Red & c\_LED\_RED & 10 \\
Orange & c\_LED\_RED\_ORANGE & 11 \\
\hline
\end{tabular}
}
\end{table}
Each LED's two-bit state is connected to \textit{led\_state\_i} on a column-first,
line-second basis.
%------------------------------------------------------------------------------
% SUBSEC: Board-level
%------------------------------------------------------------------------------
\subsection{Board-level view}
\label{sec:bicolor-led-brdlvl}
There are twelve bicolor LEDs on the CONV-TTL-BLO; they are connected in a two-line,
six-column pattern controlled by a \textit{bicolor\_led\_ctrl} block.
Table~\ref{tbl:bicolor-led-state-conn} shows the \textit{led\_state\_i} connections
for the bicolor status LEDs in the CONV-TTL-BLO gateware.
\begin{table}[h]
\caption{LED state vector connections in the gateware}
\label{tbl:bicolor-led-state-conn}
\centerline
{
\rowcolors{2}{white}{gray!25}
\begin{tabular}{l c l c}
\hline
\textbf{Line} & \textbf{Column} & \multicolumn{1}{c}{\textbf{LED}} & \textbf{LED state bits} \\
\hline
1 & 1 & WHITE\_RABBIT\_ADDR & \textit{1..0} \\
1 & 2 & WHITE\_RABBIT\_GMT & \textit{3..2} \\
1 & 3 & WHITE\_RABBIT\_LINK & \textit{5..4} \\
1 & 4 & WHITE\_RABBIT\_OK & \textit{7..6} \\
1 & 5 & MULTICAST\_ADDR\_1 & \textit{9..8} \\
1 & 6 & MULTICAST\_ADDR\_2 & \textit{11..10} \\
2 & 1 & I2C & \textit{13..12} \\
2 & 2 & TTL & \textit{15..14} \\
2 & 3 & ERR & \textit{17..16} \\
2 & 4 & PW & \textit{19..18} \\
2 & 5 & MULTICAST\_ADDR\_4 & \textit{21..20} \\
2 & 6 & MULTICAST\_ADDR\_8 & \textit{23..22} \\
\hline
\end{tabular}
}
\end{table}
The states of the used LEDs can be found in Table 1 of the CONV-TTL-BLO User
Guide~\cite{ctb-ug}. They are controlled by combinatorial multiplexers. The
selection signals to these multiplexers are set throughout the logic.
%==============================================================================
% SEC: Pulse gen
%==============================================================================
\pagebreak
\section{Pulse generator}
\label{sec:pulse-gen}
\centerline
{
\begin{tabular}{l l l}
\hline
\textbf{Entity} & \textit{conv\_pulse\_gen} & \\
\textbf{Generics} & \textit{g\_pwidth} & Width of the output pulse in \textit{clk\_i} cycles \\
\textbf{Ports} & \textit{clk\_i} & Clock signal \\
& \textit{rst\_n\_i} & Active-low reset signal \\
& \textit{en\_i} & Pulse generator enable \\
& \textit{gf\_en\_n\_i} & Active-low glitch filter enable \\
& \textit{trig\_a\_i} & Pulse trigger \\
& \textit{pulse\_o} & Pulse output \\
\textbf{Usage} & Output pulse & 1.2~$\mu$s pulses with min. period of 6~$\mu$s \\
& & and one-cycle wide glitch filter \\
\hline
\end{tabular}
}
\vspace*{11pt}
The \textit{conv\_pulse\_gen} block generates pulses on the rising edge of the
\textit{trig\_a\_i} input. The pulse width is configurable via the \textit{g\_pwidth}
generic. The block also incorporates a glitch filter with a configurable length
(\textit{g\_gf\_len}) that can be used to avoid pulses generated because of
glitches at the \textit{trig\_a\_i} input.
Pulse widths at the output are limited internally to 1/5 duty cycle, to safeguard
the blocking output transformers.
Six \textit{conv\_pulse\_gen} blocks (one per channel) are used for generating blocking and TTL
pulses at the outputs, based on trigger inputs arriving on the channels. The \textit{conv\_pulse\_gen} blocks
are configured for 1.2~${\mu}$s pulses (\textit{g\_pwidth~=~24}, considering the 50~ns clock input).
%------------------------------------------------------------------------------
% SUBSEC: Implem
%------------------------------------------------------------------------------
\subsection{Implementation}
\label{sec:pulse-gen-implem}
Figure~\ref{fig:pulse-gen} shows the implementation of the \textit{conv\_pulse\_gen}
block. It employs a finite-state machine (FSM) that is used to generate
a fixed-width pulse at the output.
An external glitch filter (\textit{gc\_glitch\_filt} from the OHWR general-cores library)
can be enabled by the user by flipping SW1.1. Enabling this external glitch filter will mean
the input trigger is sampled with the 20~MHz clock prior to it being input to the glitch filter
(see Figure~\ref{fig:hdl-bd}).
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/pulse-gen}}
\caption{Pulse generator block}
\label{fig:pulse-gen}
\end{figure}
Regardless of whether the glitch filter is enabled or not, the FSM reacts to the
rising edge of one of its two start inputs. A rising edge on an input starts
the internal counter, which counts up to a maximum value in order to assure a
pulse with the length \textit{g\_pwidth}. However, since the glitch filter adds a
delay to the input pules, the behavior of the outputs is different depending on whether
the filter is enabled or not.
With the glitch filter disabled, the input pulse enables the input flip-flop, which starts
pulse generation. The generated pulse signal is then synchronized in the \textit{clk\_20\_vcxo\_i}
domain and input to the synchronous FSM, which extends the pulse to the appropriate pulse width.
The rising edge on \textit{SGF0} triggers the counter, and when the counter reaches the value
corresponding to the selected pulse width, it sets the \textit{OGF0} output, which will reset
the input flip-flop, thus ending the pulse.
The output of the pulse-triggered flip-flop is fed into the synchronizer since this is guaranteed
to be a signal which is longer than two clock cycles, thus being detected by the FSM. Had the
trigger input been fed directly to the synchronization FFs, a shorter-than-one-cycle glitch would
trigger a pulse but not the synchronization FFs, and an output signal can potentially be extended
to a pulse length which is unsafe for the controlling MOSFET on the CONV-TTL-BLO board.
With the glitch filter enabled, the rising edge on \textit{SGF1} sets \textit{OGF1},
and this will be kept high until the counter reaches the value corresponding to the
pulse width. The input trigger signal is synchronized into the 20~MHz clock domain outside
the \textit{conv\_pulse\_gen} block, and is fed directly to the input of the FSM.
Before being fed to the FSM, however, the glitch-filtered signal is passed through a \textit{pulse
inhibit circuit}, which inhibits the first pulse when the board is in TTL-BAR repetition mode.
In this mode, an unconnected channel is always HIGH and until the
\textit{no signal detect} block outside the \textit{conv\_pulse\_gen} block (see the next
subsection) triggers, the continuous HIGH signal will trigger a pulse, due to the reset
state of the rising-edge detector on the FSM input.
After the pulse generation period, the FSM goes into a pulse rejection state,
where the pulse reset is kept high. If any pulses arrive on the input while the FSM
is in this rejection state, they are not replicated at the output. The pulse rejection
phase lasts for 4*\textit{g\_pwidth}, yielding a maximum duty cycle of 1/5 for input pulses.
Note that due to the fact that the counter starts counting up from zero and delays
in the glitch filter when it is enabled, the maximum value of the internal counter is not
\textit{g\_pwidth}. Instead, the counter counts up to a pair of VHDL constants defined
in the code. These constants assure the pulse at the output is kept high for a number of
\textit{g\_pwidth} cycles of the \textit{clk\_i} signal.
%------------------------------------------------------------------------------
% SUBSEC: Board-level
%------------------------------------------------------------------------------
\subsection{Board-level view}
\label{sec:pulse-gen-brdlvl}
Figure~\ref{fig:pulse-brd} shows the pulse replication mechanism on the
CONV-TTL-BLO. Here, the \textit{PG} block is the \textit{conv\_pulse\_gen} block
with the necessary settings. This block can either be triggered via a pulse arriving
on the TTL or blocking channel, or by a manual trigger pulse arriving from the
\textit{conv\_man\_trig} component (see Section~\ref{sec:man-trig}).
\begin{figure}[h]
\centerline{\includegraphics[width=.9\textwidth]{fig/pulse-rep}}
\caption{Board-level view of pulse replication mechanism}
\label{fig:pulse-brd}
\end{figure}
Since the \textit{conv\_pulse\_gen} block expects a rising edge at its \textit{trig\_a\_i}
input in order to generate a pulse at the output, logic external to the block
caters for the different types of signals that arrive on CONV-TTL-BLO inputs.
Most of this external logic is on the TTL pulse side, where both TTL and TTL-BAR
pulses may arrive. As described in Section 4.3 of the CONV-TTL-BLO User Guide~\cite{ctb-ug},
if a wire is not plugged in when TTL-BAR pulses are input, a continuous logic high level
on the line would inhibit pulses arriving on the blocking side from triggering a pulse
generation. This is why the \textit{no signal detect} block has been implemented.
The block's implementation is shown in Figure~\ref{fig:no-sig-detect}. It is implemented as
a counter which keeps the \textit{en\_o} signal high as long as it does not reach its maximum value.
The counter counts up when the \textit{cnt} input is high. By setting the maximum value
of the counter to 1999, it disables the line to the multiplexer if this stays high
for 100~${\mu}s$, thus allowing for blocking pulses at the input of the OR gate. The line
is re-enabled as soon as it goes back low, i.e., when a wire has been plugged into the
channel.
\begin{figure}[h]
\centerline{\includegraphics[width=.65\textwidth]{fig/no-sig-detect}}
\caption{No signal detect block}
\label{fig:no-sig-detect}
\end{figure}
Both the \textit{no signal detect} block and the glitch filter are generated
for each channel in the top-level VHDL file of the design.
%==============================================================================
% SEC: Pulse counters
%==============================================================================
\pagebreak
\section{Pulse counters}
\label{sec:pulse-cnt}
There are a total of six pulse counters implemented in the logic. Their
implementation is achieved via a single process -- \textit{p\_pulse\_cnt}.
Figure~\ref{fig:pulse-cnt} presents the implementation of the pulse counters.
When a pulse arrives on either the TTL or blocking side, it is resynchronized
in the 20~MHz clock domain and passed through a rising edge detector. When
a rising edge occurs on the pulse, the counter is incremented by one and stored
to the channel pulse counter register (CHxPCR -- see Appendix~\ref{app:conv-regs})
register.
Note that this register is implemented outside of the \textit{conv\_regs} component,
since it is a read-write register. When the register is written by the \textit{conv\_regs}
component, the \textit{load} output is asserted and the register is loaded with
the value received via I$^2$C.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/pulse-cnt}}
\caption{Pulse counter implementation}
\label{fig:pulse-cnt}
\end{figure}
%==============================================================================
% SEC: Manual trigger
%==============================================================================
\pagebreak
\section{Manual pulse trigger}
\label{sec:man-trig}
\centerline
{
\begin{tabular}{l l l}
\hline
\textbf{Entity} & \textit{conv\_man\_trig} & \\
\textbf{Generics} & \textit{g\_nr\_chan} & Pulse repeater number of channels \\
& \textit{g\_gf\_len} & Pulse generator glitch filter length \\
\textbf{Ports} & \textit{clk\_i} & Clock signal \\
& \textit{rst\_n\_i} & Active-low reset signal \\
& \textit{reg\_ld\_i} & MPT in the CR written \\
& \textit{reg\_i} & Value of MPT field in the CR \\
& \textit{trig\_o} & Trigger output \\
\textbf{Usage} & Trigger pulse generator & Two clock-cycle pulse output \\
\hline
\end{tabular}
}
\vspace*{11pt}
The manual pulse triggering mechanism is achieved via the \textit{conv\_man\_trig}
module. This module generates a pulse that is input to the \textit{conv\_pulse\_gen}
module and that triggers a 1.2~$\mu$s pulse on the TTL and blocking outputs.
Since manual pulse generation is a delicate feature which is only used when a debug
pulse is generated on a channel, a "password" is needed in order to manually trigger
a pulse. This "password" is obtained from the MPT field in the control register
(CR -- see Appendix~\ref{app:conv-regs-cr}), where a magic sequence of
numbers should be written. Once this magic sequence has been input, the next write to
the register should be the channel number. If a valid channel number is written,
a pulse is generated on this channel.
\begin{figure}[h]
\centerline{\includegraphics[width=.6\textwidth]{fig/man-trig-fsm}}
\caption{FSM of the \textit{conv\_man\_trig} component}
\label{fig:man-trig-fsm}
\end{figure}
The \textit{conv\_man\_trig} takes the value of the MPT field in the control register
as an input and via the state-machine shown in Figure~\ref{fig:man-trig-fsm}, it checks
that the values written to the MPT field correspond to the magic sequence (Table~\ref{tbl:man-trig-magic}).
The FSM advances on writes to the MPT field of the CR. Once the magic sequence has been received,
the next write to the MPT field sets the \textit{trig\_o} output, which is input to the \textit{trig\_a\_i}
input of \textit{conv\_pulse\_gen} (see Section~\ref{sec:pulse-gen}) after it is ORed together with the
TTL and blocking inputs as shown in Figure~\ref{fig:pulse-brd}. Should an invalid channel number be
input, no error is reported and no pulse is generated.
\begin{table}[h]
\caption{Magic sequence to initiate manual pulse triggering}
\label{tbl:man-trig-magic}
\centerline
{
\begin{tabular}{c c c c}
\hline
\textbf{Byte 0} & \textbf{Byte 1} & \textbf{Byte 2} & \textbf{Byte 3} \\
\hline
0xde & 0xad & 0xbe & 0xef \\
\hline
\end{tabular}
}
\end{table}
To generate a long enough pulse to be detected by the \textit{conv\_pulse\_gen} component
when its glitch filter is enabled, the \textit{conv\_man\_trig} should have knowledge
of the length of the pulse generator's glitch filter, which can be supplied via the
\textit{g\_gf\_len} generic. With the value of this generic, the \textit{conv\_man\_trig}
component extends the \textit{trig\_o} pulse to the necessary number of cycles for the
\textit{conv\_pulse\_gen} to detect a pulse. This extension is done in the \textit{GEN}
state (Figure~\ref{fig:man-trig-fsm}).
%======================================================================================
% SEC: Pulse timetag
%======================================================================================
\pagebreak
\section{Pulse time-tagging}
\label{sec:timetag}
\centerline
{
\begin{tabular}{l l p{.5\textwidth}}
\hline
\textbf{Entity} & \textit{pulse\_timetag} & \\
\textbf{Generics} & \textit{g\_clk\_rate} & Frequency in Hz of \textit{clk\_i} signal \\
& \textit{g\_nr\_chan} & Pulse repeater number of channels \\
\textbf{Ports} & \textit{clk\_i} & Clock signal \\
& \textit{rst\_n\_i} & Active-low reset signal \\
& \textit{pulse\_a\_i} & Asynchronouse pulse input \\
& \textit{wr\_tm\_cycles\_i} & Cycles counter from WRPC \\
& \textit{wr\_tm\_tai\_i} & TAI seconds counter from WRPC \\
& \textit{wr\_tm\_valid\_i} & Time from WRPC is valid \\
& \textit{wb\_tm\_tai\_l\_i} & Lower bits of TAI time counter from register \\
& \textit{wb\_tm\_tai\_l\_ld\_i} & Lower bits register write \\
& \textit{wb\_tm\_tai\_h\_i} & Upper bits of TAI time counter from register \\
& \textit{wb\_tm\_tai\_h\_ld\_i} & Upper bits register write \\
& \textit{tm\_cycles\_o} & Cycles counter to FIFO \\
& \textit{tm\_tai\_o} & TAI seconds counter to FIFO \\
& \textit{tm\_wpres\_o} & Time from WRPC is valid \\
& \textit{chan\_o} & Trigger channel to FIFO \\
& \textit{fifo\_full\_i} & FIFO status input \\
& \textit{fifo\_wr\_req\_o} & FIFO write request output, max. four clock cycles
delay after pulse rising edge \\
\hline
\end{tabular}
}
\vspace*{11pt}
A simplified view of the time-tagging architecture is shown in Figure~\ref{fig:timetag-arch}.
There are two clock domains in the design. The time-tag controller and the time from the
WRPC are both in the 125~MHz clock domain, while the \textit{conv\_regs} component is in the
20~MHz clock domain. The FIFO is asynchronous and clocked by both the 125 and 20~MHz clocks.
\begin{figure}[h]
\centerline{\includegraphics[width=.9\textwidth]{fig/timetag-arch}}
\caption{Time-tag architecture}
\label{fig:timetag-arch}
\end{figure}
The time-tag controller in the figure is the \textit{pulse\_timetag} VHDL component.
It is designed to be connected directly to the FIFO as shown above.As opposed to what the
simplified architecture above shows, the time-tag controller also implements the local time counters.
The block's design is presented in Figure~\ref{fig:timetag-core}. This figure shows the functioning
when the \textit{pulse\_timetag} component is clocked from the 125~MHz clock, as is the case in the
converter board designs. Note however that the component can work with any clock rate by changing
the \textit{g\_clk\_rate} generic.
\begin{figure}[h]
\centerline{\includegraphics[width=.9\textwidth]{fig/timetag-core}}
\caption{Time-tag controller logic}
\label{fig:timetag-core}
\end{figure}
A free-running counter inside the block counts the ticks of the \textit{clk\_i} signal
to count the seconds. When it reaches the value \textit{g\_clk\_rate-1} (125~mega in
the figure), it resets and sends a "tick" to the TAI seconds counter, which then increments.
As seen in Figure~\ref{fig:hdl-bd}, the pulse inputs are derived from the OR gate which
ORs together the TTL and blocking inputs. Since these pulses can be asynchronous, they
are synchronized in the 125~MHz domain and passed through rising edge detectors. If the
FIFO is not full, a rising edge on any channel then triggers the
\textit{fifo\_wr\_req\_p\_o} output. As the port's name suggests, this signal is a one-cycle
pulse that triggers a write to the FIFO.
Note that due to the synchronization logic, rising edge detector and the latching of the
ORed pulse rising edge detection signal, the \textit{fifo\_wr\_req\_p\_o} signal is
set between three and four cycles after the pulse signal actually arrives on the input.
All the output ports are connected externally directly to the FIFO, therefore when the
\textit{fifo\_wr\_req\_p\_o} output pulses, they are written to the FIFO. As shown in
Figure~\ref{fig:timetag-arch}, the \textit{tm\_wpres\_o} signal is also reflected in the
board status register (SR -- see Appendix~\ref{app:conv-regs-sr}).
The FIFO itself is generated using \textit{wbgen2}~\cite{wbgen2} and connected
on the top-level to the \textit{pulse\_timetag} component.
Due to the two clock domains in the design, some synchronization logic is needed. This is
achieved via \textit{gc\_sync\_ffs} components from the \textit{general-cores}
library~\cite{gencores-ohwr} in the case of the WR time valid signals storage to the SR
and in the case of the TAI time value load pulses from the \textit{conv\_regs} to the
\textit{pulse\_timetag} components.
The TAI time signal is not synchronized before being connected to the \textit{conv\_regs}
component, since its rate of change of once per second is considered too slow to present
any problem of synchronization when read by the user.
%======================================================================================
% SEC: Folder structure
%======================================================================================
\pagebreak
\section{Folder structure}
\label{sec:fold-struct}
Gateware files are organized on a per type-of-project basis. There are two different types of
projects for CONV-TTL-BLO gateware: the \textit{release project} and \textit{test projects}.
The release project is the latest production gateware version, that goes on the CONV-TTL-BLO
board used in the field. Test projects are meant to be downloaded to a CONV-TTL-BLO for
testing the CONV-TTL-BLO system under long-term test conditions. The projects present in the
repository at the time of writing of this document are presented in Table~\ref{tbl:fold-struct-proj}.
\begin{table}[h]
\caption{Gateware projects in the repository}
\label{tbl:fold-struct-proj}
\centerline
{
\rowcolors{2}{white}{gray!25}
\begin{tabular}{l p{.6\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Project}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
\textit{conv\_ttl\_blo} & Design-wide release project to be used in the field \\
\textit{regtest} & Long-term test for testing the I$^2$C communication by writing
to a RAM on the FPGA \\
\textit{pulsetest} & Long-term test for testing pulse repetition on the CONV-TTL-BLO \\
\hline
\end{tabular}
}
\end{table}
The folder structure for the project is presented below.
\let \oldlabelitemi=\labelitemi
\let \oldlabelitemii=\labelitemii
\let \oldlabelitemiii=\labelitemiii
\let \oldlabelitemiv=\labelitemiv
\renewcommand{\labelitemi}{$\rightarrow$}
\renewcommand{\labelitemii}{$\rightarrow$}
\renewcommand{\labelitemiii}{$\rightarrow$}
\renewcommand{\labelitemiv}{$\rightarrow$}
\begin{itemize}
\item conv-ttl-blo-gw/
\begin{itemize}
\item doc/
\begin{itemize}
\item hdlguide/
\end{itemize}
\item ip\_cores/
\begin{itemize}
\item general-cores/
\end{itemize}
\item modules/
\begin{itemize}
\item Release/
\begin{itemize}
\item conv\_man\_trig.vhd
\item conv\_pulse\_gen.vhd
\item conv\_regs.vhd
\item conv\_regs.wb
\item pulse\_timetag.vhd
\end{itemize}
\item pulsetest/
\begin{itemize}
\item pulse\_gen\_gp.vhd
\item {[}...{]}
\end{itemize}
\item conv\_pulse\_gen.vhd
\item reset\_gen.vhd
\item rtm\_detector.vhd
\end{itemize}
\item sim/
\item syn/
\begin{itemize}
\item Release/
\item pulsetest/
\item regtest/
\end{itemize}
\item top/
\begin{itemize}
\item Release/
\begin{itemize}
\item conv\_ttl\_blo.ucf
\item conv\_ttl\_blo.vhd
\end{itemize}
\item pulsetest/
\begin{itemize}
\item pulsetest.ucf
\item pulsetest.vhd
\end{itemize}
\item regtest/
\begin{itemize}
\item regtest.ucf
\item regtest.vhd
\end{itemize}
\end{itemize}
\end{itemize}
\end{itemize}
\renewcommand{\labelitemi}{\oldlabelitemi}
\renewcommand{\labelitemii}{\oldlabelitemii}
\renewcommand{\labelitemiii}{\oldlabelitemiii}
\renewcommand{\labelitemiv}{\oldlabelitemiv}
\begin{table}[h]
\caption{Folder structure}
\label{tbl:fold-struct}
\centerline
{
\rowcolors{2}{white}{gray!25}
\begin{tabular}{l p{.7\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Folder}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
doc/ & Documentation files \\
ip\_cores/ & IP cores used in the design \\
modules/ & Project-specific modules instantiated in the top-level design \newline
Organized on a project type basis \\
sim/ & Module simulation files \\
syn/ & ISE project file and synthesis output files, including binaries to
download to the FPGA \newline
Organized on a project type basis \\
top/ & Top-level .vhd and .ucf files \newline
Organized on a project type basis \\
\hline
\end{tabular}
}
\end{table}
As can be seen from the folder structure above, gateware files are organized in the
\textit{modules/}, \textit{syn/} and \textit{top/} folders following this project convention.
Files in these folders (where relevant) are organized in the \textit{Release/}, \textit{pulsetest/}
and \textit{regtest/} folders, where the \textit{Release/} folder of course represents the
release gateware and the other two are test projects, as their names suggest.
One place where the project structure is not necessarily enforced is the \textit{sim/} folder.
This folder is meant to contain files relevant for simulation of various modules within
the design and as such can be composed of folders named after the component to be simulated.
%======================================================================================
% SEC: Getting Around the Code
%======================================================================================
\pagebreak
\section{Getting around the code}
\label{sec:get-around}
Ports and signals usually follow the coding guideline at~\cite{coding-guidelines}. Most of the
top-level ports of the gateware are lower-case versions of their schematics counterparts. The
exceptions from this are due to either net names that could not be syntactically represented in
VHDL, or net names that have been made clearer in VHDL code.
\begin{figure}[h]
\centerline{\includegraphics[width=.6\textwidth]{fig/arch}}
\caption{VHDL architecture of the release gateware}
\label{fig:arch}
\end{figure}
Code in the top-level files is organized in code sections. A code section is a piece of code
pertaining to a certain part of the design, where component instantiations and input and
output port assignments are made. For example, there is a section pertaining to
pulse repetition, where there is a generate block to generate the logic necessary for pulse
repetition on each channel, including the pulse status LEDs.
The VHDL architecture of the top-level file of the release gateware is shown
in Figure~\ref{fig:arch}. Table~\ref{tbl:arch} lists the code sections of the
top-level file.
{
\rowcolors{2}{white}{gray!25}
\begin{longtable}{p{.25\textwidth} p{.65\textwidth}}
\caption{Code sections in the FPGA gateware}
\label{tbl:arch} \\
% FIRST HEADER %
\hline
\multicolumn{1}{c}{\textbf{Code section}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
\endfirsthead
% OTHER HEADERS %
\hline
\multicolumn{1}{c}{\textbf{Code section}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
\endhead
% FOOTERS %
\hline
\endfoot
% TABLE CONTENTS %
Reset logic & -- \textit{reset\_gen} instantiation \\
I$^2$C bridge & -- \textit{wb\_i2c\_bridge} instantiation \newline
-- logic for blinking the I2C bicolor LED on the front panel \newline
-- generate the CWDTO bit register \\
Converter boards
registers & -- \textit{conv\_regs} instantiation \newline
-- connect the switch lines to the SR \newline
-- connect the RTM detection lines to the SR \newline
-- implement the RST, RST\_UNLOCK and WRPRES bit registers \\
Channel logic & -- connect inputs to internal signals \newline
-- instantiation of the pulse time-tagging controller and
manual pulse trigger components\newline\newline
VHDL \textit{generate} statements then generate the
channel logic: \newline
-- glitch filters and selection between filtered and non-filtered
based on the glitch filter selection switch \newline
-- synchronization flip-flops on the input signals \newline
-- input pulse counter logic \newline
-- no signal detect block (Figure~\ref{fig:no-sig-detect}) \newline
-- \textit{conv\_pulse\_gen} instantiation \newline
-- pulse output connections \newline
-- process to light pulse LEDs on pulse output \\
MultiBoot logic & -- \textit{wb\_xil\_multiboot} instantiation \\
Status LEDs & -- \textit{bicolor\_led\_ctrl} instantiation \newline
-- connecting the \textit{led\_state\_i} input of the
component to the relevant control signals \\
RTM detection & -- inverting the input signals from the RTM detection lines \newline
-- \textit{rtm\_detector} component instantiation \\
\end{longtable}
} % end rowcolors
%==============================================================================
% Appendices
%==============================================================================
\pagebreak
\begin{appendices}
%==============================================================================
% APP: Memmap
%==============================================================================
\section{Memory map}
\label{app:memmap}
Table~\ref{tbl:memmap} shows the complete memory map of the gateware. The
following sections list the memory map of each peripheral.
In order to convert address values to register index values for SNMP access,
the following formula should be used:
\begin{center}
$reg. index = \frac{addr}{4} + 1$
\end{center}
\begin{table}[h]
\caption{CONV-TTL-BLO memory map}
\label{tbl:memmap}
\centerline
{
\rowcolors{2}{white}{gray!25}
\begin{tabular}{l l l p{.4\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Peripheral}} & \multicolumn{2}{c}{\textbf{Address range}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
Board registers & 0x000 & 0x020 & Coverter board registers \\
MultiBoot & 0x040 & 0x050 & MultiBoot module \\
Thermometer & 0x080 & 0x084 & Thermometer chip \\
\hline
\end{tabular}
}
\end{table}
%%------------------------------------------------------------------------------
%% SUBSEC: conv_regs
%%------------------------------------------------------------------------------
\include{conv-regs}
%------------------------------------------------------------------------------
% SUBSEC: MultiBoot
%------------------------------------------------------------------------------
\include{multiboot-regs}
%------------------------------------------------------------------------------
% SUBSEC: Thermo
%------------------------------------------------------------------------------
\subsection{Thermometer module}
\label{app:memmap-thermo}
\indent Base address: 0x080
\vspace*{11pt}
\centerline
{
\rowcolors{2}{white}{gray!25}
\begin{tabular}{l l l p{.5\textwidth}}
\hline
\textbf{Offset} & \textbf{Default} & \textbf{Name} & \textbf{Description} \\
\hline
0x00 & 0x00000000 & OWCSR & One-Wire Control and Status Register \\
0x04 & 0x00000004 & OWCDR & One-Wire Clock Divider Registers \\
\hline
\end{tabular}
}
\vspace*{11pt}
For details on the bits of the thermometer module access registers, see the
OneWire Master module's documentation~\cite{onewire-core}.
Note that the OWCDR should be set accordingly for proper functioning of the
one-wire timings. The value for the current version of the gateware is
\verb-OWCDR = 0x00130063-.
%------------------------------------------------------------------------------
\end{appendices}
%------------------------------------------------------------------------------
%==============================================================================
% Bibliography
%==============================================================================
\pagebreak
\bibliographystyle{ieeetr}
\bibliography{hdlguide-conv-ttl-blo}
\end{document}
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/doc/hdlguide/multiboot-regs.tex 0000664 0000000 0000000 00000022136 12314554267 0030171 0 ustar 00root root 0000000 0000000 \subsection{MultiBoot controller}
\label{app:multiboot-regs}
Base address: 0x040
{
\rowcolors{2}{white}{gray!25}
\begin{longtable}{l l l p{.5\textwidth}}
\hline
\textbf{Offset} & \textbf{Default} & \textbf{Name}
& \textbf{Description} \\
\hline
\endfirsthead
\hline
\hline
\endhead
\hline
\endfoot
0x0 & 0x00000000 & CR & Control Register\\
0x4 & 0x00000000 & SR & Status Register\\
0x8 & 0x00000000 & GBBAR & Golden Bitstream Base Address Register\\
0xc & 0x00000000 & MBBAR & MultiBoot Bitstream Base Address Register\\
0x10 & 0x10000000 & FAR & Flash Access Register\\
\end{longtable}
}
\vspace{11pt}
\subsubsection{CR -- Control Register}
\label{app:multiboot-regs-cr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}IPROG} & \multicolumn{1}{|c|}{\cellcolor{gray!25}IPROG\_UNLOCK}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{1}{|c}{-} & \multicolumn{1}{|c|}{\cellcolor{gray!25}RDCFGREG} & \multicolumn{6}{|c|}{\cellcolor{gray!25}CFGREGADR[5:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CFGREGADR
} [\emph{read/write}]: Configuration register address
\\
Address of FPGA configuration register to read.
\end{small}
\item \begin{small}
{\bf
RDCFGREG
} [\emph{write-only}]: Read FPGA configuration register
\\
1 -- Start FPGA configuration register sequence. \\ 0 -- No effect.
\end{small}
\item \begin{small}
{\bf
IPROG\_UNLOCK
} [\emph{read/write}]: Unlock bit for the IPROG command
\\
1 -- Unlock IPROG bit. \\ 0 -- No effect.
\end{small}
\item \begin{small}
{\bf
IPROG
} [\emph{read/write}]: Start IPROG sequence
\\
1 -- Start IPROG configuration sequence \\ 0 -- No effect \\ This bit needs to be unlocked by writing the IPROG\_UNLOCK bit first. \\ A write to this bit with IPROG\_UNLOCK cleared has no effect.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{SR -- Status Register}
\label{app:multiboot-regs-sr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}WDTO} & \multicolumn{1}{|c|}{\cellcolor{gray!25}IMGVALID}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CFGREGIMG[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CFGREGIMG[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CFGREGIMG
} [\emph{read-only}]: Configuration register image
\\
Image of the FPGA configuration register at address CFGREGADR (see Configuration Registers section in Xilinx UG380~\cite{ug380}); validated by IMGVALID bit
\end{small}
\item \begin{small}
{\bf
IMGVALID
} [\emph{read-only}]: Configuration register image valid
\\
1 -- CFGREGIMG valid \\ 0 -- CFGREGIMG not valid;
\end{small}
\item \begin{small}
{\bf
WDTO
} [\emph{read/write}]: MultiBoot FSM stalled at one point and was reset by FSM watchdog
\\
1 -- FSM watchdog fired \\ 0 -- FSM watchdog has not fired
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{GBBAR -- Golden Bitstream Base Address Register}
\label{app:multiboot-regs-gbbar}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
BITS
} [\emph{read/write}]: Bits of GBBAR register
\\
31..24 -- Read or fast-read OPCODE of the flash chip (obtain it from the flash chip datasheet) \\ 23..0 -- Golden bitstream address in flash
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{MBBAR -- MultiBoot Bitstream Base Address Register}
\label{app:multiboot-regs-mbbar}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
BITS
} [\emph{read/write}]: Bits of MBBAR register
\\
31..24 -- Read or fast-read OPCODE of the flash chip (obtain it from the flash chip datasheet) \\ 23..0 -- MultiBoot bitstream start address in flash
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{FAR -- Flash Access Register}
\label{app:multiboot-regs-far}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}READY} & \multicolumn{1}{|c|}{\cellcolor{gray!25}CS} & \multicolumn{1}{|c|}{\cellcolor{gray!25}XFER} & \multicolumn{2}{|c|}{\cellcolor{gray!25}NBYTES[1:0]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}DATA[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}DATA[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}DATA[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
DATA
} [\emph{read/write}]: Flash data field
\\
23..16 -- DATA[2]; after an SPI transfer, this register contains the value of data byte 2 read from the flash \\ 15..8 -- DATA[1]; after an SPI transfer, this register contains the value of data byte 1 read from the flash \\ 7..0 -- DATA[0]; after an SPI transfer, this register contains the value of data byte 0 read from the flash
\end{small}
\item \begin{small}
{\bf
NBYTES
} [\emph{read/write}]: Number of DATA fields to send and receive in one transfer:
\\
0x0 -- Send 1 byte (DATA[0]) \\ 0x1 -- Send 2 bytes (DATA[0], DATA[1]) \\ 0x2 -- Send 3 bytes (DATA[0], DATA[1], DATA[2])
\end{small}
\item \begin{small}
{\bf
XFER
} [\emph{write-only}]: Start transfer to and from flash
\\
1 -- Start transfer \\ 0 -- Idle
\end{small}
\item \begin{small}
{\bf
CS
} [\emph{read/write}]: Chip select bit
\\
1 - Flash chip selected (CS pin low) \\ 0 - Flash chip not selected (CS pin is high)
\end{small}
\item \begin{small}
{\bf
READY
} [\emph{read-only}]: Flash access ready
\\
1 - Flash access completed \\ 0 - Flash access in progress
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/ip_cores/ 0000775 0000000 0000000 00000000000 12314554267 0023740 5 ustar 00root root 0000000 0000000 conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/ip_cores/general-cores/ 0000775 0000000 0000000 00000000000 12314554267 0026466 5 ustar 00root root 0000000 0000000 conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/modules/ 0000775 0000000 0000000 00000000000 12314554267 0023605 5 ustar 00root root 0000000 0000000 conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/modules/Manifest.py 0000664 0000000 0000000 00000000402 12314554267 0025721 0 ustar 00root root 0000000 0000000 modules = {
"local" : [
# pulsetest module added from pulsetest syn folder
# Release module added from Release syn folder
"bicolor_led_ctrl"
]
}
files = [
"reset_gen.vhd",
"rtm_detector.vhd"
]
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/modules/Release/ 0000775 0000000 0000000 00000000000 12314554267 0025165 5 ustar 00root root 0000000 0000000 conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/modules/Release/Manifest.py 0000664 0000000 0000000 00000000232 12314554267 0027302 0 ustar 00root root 0000000 0000000 files = [
"conv_regs.vhd",
"ctblo_pulse_gen.vhd",
"conv_man_trig.vhd",
"conv_ring_buf.vhd",
"conv_pulse_timetag.vhd"
];
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/modules/Release/README.txt 0000664 0000000 0000000 00000003025 12314554267 0026663 0 ustar 00root root 0000000 0000000 conv_regs.wb
============
If you change the FIFO width in the top-level conv_ttl_blo.vhd, you need to
also change the width of the USEDW field.
conv_regs.vhd
=============
You need to make some changes to this file after EVERY RUN of wbgen2:
1. Add the following output port declaration after the reg_tbmr_wrtag_i port:
-- Tag buffer read request, asserted when reading from TBMR
reg_tb_rd_req_p_o : out std_logic;
2. Assign the port FOUR TIMES in the register bank process:
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
-- [...]
reg_tb_rd_req_p_o <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
-- [...]
reg_tb_rd_req_p_o <= '0';
ack_in_progress <= '0';
else
-- [...]
reg_tb_rd_req_p_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(3 downto 0) is
[...]
when "1011" =>
if (wb_we_i = '1') then
end if;
reg_tb_rd_req_p_o <= '1';
rddata_reg(5 downto 0) <= reg_tbmr_chan_i;
rddata_reg(31) <= reg_tbmr_wrtag_i;
[...]
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/modules/Release/conv_man_trig.vhd 0000664 0000000 0000000 00000016636 12314554267 0030531 0 ustar 00root root 0000000 0000000 --==============================================================================
-- CERN (BE-CO-HT)
-- Pulse trigger for pulse converter boards
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2014-01-28
--
-- version: 1.0
--
-- description:
-- This module generates a pulse for the conv_pulse_gen module for manually
-- triggering a debug pulse on a channel output. It works in conjunction
-- with the converter board registers component (conv_regs), from where it
-- obtains the value of the MPT (manual pulse trigger) field in the control
-- register.
--
-- To manually trigger a pulse, a magic sequence of numbers (0xde, 0xad, 0xbe,
-- 0xef) should first be sent to the MPT field, followed by the channel number
-- to send the pulse on. When the channel number is sent, a single pulse is
-- generated by the conv_pulse_gen component at the output.
--
-- The conv_man_trig module checks to see whether the proper magic sequence
-- is written the the MPT field using a simple FSM. The FSM advances when
-- the MPT field is written, if the MPT field corresponds to the proper byte
-- in the magic sequence. If at any time during the magic sequence the value
-- of the MPT field does not correspond to the expected value, the FSM returns
-- to IDLE.
--
-- After the magic sequence is received, the FSM waits for the channel number
-- to be written to the MPT. If a valid channel number is input, a pulse is
-- generated on this channel. The check of whether a valid number is input is
-- based on the g_nr_ttl_chan generic. Should an invalid channel number be
-- input, no error is reported and no pulse is generated.
--
-- The output trigger pulse is extended within the last state of the FSM, to
-- account for when the glitch filter of the conv_pulse_gen component is on.
-- To extend the pulse by an appropriate number of clock cycles, the length
-- of the conv_pulse_gen glitch filter should be input via the g_gf_len.
--
-- dependencies:
-- genram_pkg : git://ohwr.org/hdl-core-lib/general-cores.git
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2014-01-28 Theodor Stana File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.genram_pkg.all;
entity conv_man_trig is
generic
(
-- Number of conversion channels
g_nr_chan : positive := 6;
-- Length of pulse generator glitch filter, needed to generate a long
-- enough pulse
g_gf_len : positive := 1
);
port
(
-- Clock, active-low inputs
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Control inputs from conv_regs
reg_ld_i : in std_logic;
reg_i : in std_logic_vector(7 downto 0);
-- One-clock pulse output
trig_o : out std_logic_vector(g_nr_chan downto 1)
);
end entity conv_man_trig;
architecture behav of conv_man_trig is
--============================================================================
-- Type declarations
--============================================================================
-- Type for the "password" array
type t_pass_arr is array(integer range <>) of std_logic_vector(7 downto 0);
-- FSM type
type t_state is
(
IDLE,
PASS1,
PASS2,
PASS3,
GET_CHAN,
GEN
);
--============================================================================
-- Constant declarations
--============================================================================
constant c_pass_arr : t_pass_arr(0 to 3) := (x"de", x"ad", x"be", x"ef");
--============================================================================
-- Function and procedures declaration
--============================================================================
procedure f_change_state (
signal ld : in std_logic;
signal pass : in std_logic_vector(7 downto 0);
constant idx : in integer;
signal state : out t_state;
constant nstate : in t_state
) is
begin
if (ld = '1') then
if (pass = c_pass_arr(idx)) then
state <= nstate;
else
state <= IDLE;
end if;
end if;
end procedure f_change_state;
--============================================================================
-- Signal declarations
--============================================================================
-- Signal for the current state of the FSM
signal state : t_state;
-- Counter to extend the pulse to the needed number of channels
signal cnt : unsigned(f_log2_size(g_gf_len)-1 downto 0);
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- FSM logic
--============================================================================
p_fsm : process (clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
state <= IDLE;
cnt <= (others => '0');
trig_o <= (others => '0');
else
case state is
when IDLE =>
trig_o <= (others => '0');
f_change_state(reg_ld_i, reg_i, 0, state, PASS1);
when PASS1 =>
f_change_state(reg_ld_i, reg_i, 1, state, PASS2);
when PASS2 =>
f_change_state(reg_ld_i, reg_i, 2, state, PASS3);
when PASS3 =>
f_change_state(reg_ld_i, reg_i, 3, state, GET_CHAN);
when GET_CHAN =>
if (reg_ld_i = '1') then
for i in 1 to g_nr_chan loop
if (i = to_integer(unsigned(reg_i))) then
trig_o(i) <= '1';
end if;
end loop;
cnt <= (others => '0');
state <= GEN;
end if;
when GEN =>
cnt <= cnt + 1;
if (cnt = g_gf_len-1) then
state <= IDLE;
end if;
when others =>
state <= IDLE;
end case;
end if;
end if;
end process p_fsm;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/modules/Release/conv_pulse_timetag.vhd 0000664 0000000 0000000 00000016601 12314554267 0031563 0 ustar 00root root 0000000 0000000 --==============================================================================
-- CERN (BE-CO-HT)
-- Pulse time-tagging core
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2014-02-04
--
-- version: 1.0
--
-- description:
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2014-02-04 Theodor Stana File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
entity conv_pulse_timetag is
generic
(
-- Frequency in Hz of the clk_i signal
g_clk_rate : positive := 125000000;
-- Number of repetition channels
g_nr_chan : positive := 6
);
port
(
-- Clock and active-low reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Asynchronous pulse input
pulse_a_i : in std_logic_vector(g_nr_chan downto 1);
-- Time inputs from White Rabbit
wr_tm_cycles_i : in std_logic_vector(27 downto 0);
wr_tm_tai_i : in std_logic_vector(39 downto 0);
wr_tm_valid_i : in std_logic;
-- Timing inputs from Wishbone-mapped registers
wb_tm_tai_l_i : in std_logic_vector(31 downto 0);
wb_tm_tai_l_ld_i : in std_logic;
wb_tm_tai_h_i : in std_logic_vector( 7 downto 0);
wb_tm_tai_h_ld_i : in std_logic;
-- Timing outputs
tm_cycles_o : out std_logic_vector(27 downto 0);
tm_tai_o : out std_logic_vector(39 downto 0);
tm_wrpres_o : out std_logic;
chan_o : out std_logic_vector(g_nr_chan downto 1);
-- Ring buffer I/O
buf_wr_req_p_o : out std_logic
);
end entity conv_pulse_timetag;
architecture behav of conv_pulse_timetag is
--============================================================================
-- Signal declarations
--============================================================================
signal cycles_cnt : unsigned(27 downto 0);
signal cycles_tick : std_logic;
signal tai_cnt : unsigned(39 downto 0);
signal tai_l_ld : std_logic;
signal tai_h_ld : std_logic;
signal pulse_redge_p : std_logic_vector(g_nr_chan downto 1);
signal pulse_redge_p_d0 : std_logic_vector(g_nr_chan downto 1);
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Time counter logic
--============================================================================
-- The Wishbone bus may be in a different clock domain than the time tag core,
-- so first we need to synchronize the LD signals
cmp_sync_l_ld : gc_sync_ffs
port map
(
clk_i => clk_i,
rst_n_i => rst_n_i,
data_i => wb_tm_tai_l_ld_i,
ppulse_o => tai_l_ld
);
cmp_sync_h_ld : gc_sync_ffs
port map
(
clk_i => clk_i,
rst_n_i => rst_n_i,
data_i => wb_tm_tai_h_ld_i,
ppulse_o => tai_h_ld
);
-- Generate the counters
p_cycle_cnt : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
cycles_cnt <= (others => '0');
cycles_tick <= '0';
else
cycles_cnt <= cycles_cnt + 1;
cycles_tick <= '0';
-- TAI counter loaded from Wishbone
if tai_l_ld = '1' or tai_h_ld = '1' then
cycles_cnt <= (others => '0');
-- Tick and reset on second
elsif cycles_cnt = g_clk_rate-1 then
cycles_cnt <= (others => '0');
cycles_tick <= '1';
end if;
end if;
end if;
end process p_cycle_cnt;
p_tai_cnt : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
tai_cnt <= (others => '0');
-- Load from Wishbone
elsif tai_l_ld = '1' then
tai_cnt(31 downto 0) <= unsigned(wb_tm_tai_l_i);
elsif tai_h_ld = '1' then
tai_cnt(39 downto 32) <= unsigned(wb_tm_tai_h_i);
-- Increment on cycles second tick
elsif cycles_tick = '1' then
tai_cnt <= tai_cnt + 1;
end if;
end if;
end process p_tai_cnt;
--============================================================================
-- Control logic for the FIFO
--============================================================================
-- First, synchronize the pulse inputs in the clk_i domain
gen_sync_chains : for i in 1 to g_nr_chan generate
cmp_pulse_sync : gc_sync_ffs
generic map
(
g_sync_edge => "positive"
)
port map
(
clk_i => clk_i,
rst_n_i => '1',
data_i => pulse_a_i(i),
ppulse_o => pulse_redge_p(i)
);
end generate gen_sync_chains;
-- Set the control signals to the ring buffer on the rising edge of any
-- pulse channel
p_buf_ctrl : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
buf_wr_req_p_o <= '0';
else
buf_wr_req_p_o <= '0';
if not (pulse_redge_p = (pulse_redge_p'range => '0')) then
buf_wr_req_p_o <= '1';
end if;
end if;
end if;
end process p_buf_ctrl;
-- And delay the pulse rising edge for sampling (this is due to the delayed
-- setting of the write signal to the FIFO)
p_dly_pulse : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
pulse_redge_p_d0 <= (others => '0');
else
pulse_redge_p_d0 <= pulse_redge_p;
end if;
end if;
end process p_dly_pulse;
--============================================================================
-- Output logic
--============================================================================
-- Multiplex the timing outputs between WR and internal counters
tm_cycles_o <= wr_tm_cycles_i when wr_tm_valid_i = '1' else
std_logic_vector(cycles_cnt);
tm_tai_o <= wr_tm_tai_i when wr_tm_valid_i = '1' else
std_logic_vector(tai_cnt);
tm_wrpres_o <= wr_tm_valid_i;
chan_o <= pulse_redge_p_d0;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/modules/Release/conv_regs.vhd 0000664 0000000 0000000 00000051601 12314554267 0027660 0 ustar 00root root 0000000 0000000 ---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Converter board registers
---------------------------------------------------------------------------------------
-- File : conv_regs.vhd
-- Author : auto-generated by wbgen2 from conv_regs.wb
-- Created : Mon Mar 24 09:06:14 2014
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE conv_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity conv_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'ID register bits' in reg: 'BIDR'
reg_bidr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Gateware version' in reg: 'SR'
reg_sr_gwvers_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'Status of on-board switches' in reg: 'SR'
reg_sr_switches_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'RTM detection lines~\cite{rtm-det}' in reg: 'SR'
reg_sr_rtm_i : in std_logic_vector(5 downto 0);
-- Ports for BIT field: 'Communication watchdog timer status' in reg: 'SR'
reg_sr_i2c_wdto_o : out std_logic;
reg_sr_i2c_wdto_i : in std_logic;
reg_sr_i2c_wdto_load_o : out std_logic;
-- Port for BIT field: 'White Rabbit present' in reg: 'SR'
reg_sr_wrpres_i : in std_logic;
-- Ports for BIT field: 'Reset unlock bit' in reg: 'CR'
reg_cr_rst_unlock_o : out std_logic;
reg_cr_rst_unlock_i : in std_logic;
reg_cr_rst_unlock_load_o : out std_logic;
-- Ports for BIT field: 'Reset bit' in reg: 'CR'
reg_cr_rst_o : out std_logic;
reg_cr_rst_i : in std_logic;
reg_cr_rst_load_o : out std_logic;
-- Ports for PASS_THROUGH field: 'Manual Pulse Trigger' in reg: 'CR'
reg_cr_mpt_o : out std_logic_vector(7 downto 0);
reg_cr_mpt_wr_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH1PCR'
reg_ch1pcr_o : out std_logic_vector(31 downto 0);
reg_ch1pcr_i : in std_logic_vector(31 downto 0);
reg_ch1pcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH2PCR'
reg_ch2pcr_o : out std_logic_vector(31 downto 0);
reg_ch2pcr_i : in std_logic_vector(31 downto 0);
reg_ch2pcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH3PCR'
reg_ch3pcr_o : out std_logic_vector(31 downto 0);
reg_ch3pcr_i : in std_logic_vector(31 downto 0);
reg_ch3pcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH4PCR'
reg_ch4pcr_o : out std_logic_vector(31 downto 0);
reg_ch4pcr_i : in std_logic_vector(31 downto 0);
reg_ch4pcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH5PCR'
reg_ch5pcr_o : out std_logic_vector(31 downto 0);
reg_ch5pcr_i : in std_logic_vector(31 downto 0);
reg_ch5pcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH6PCR'
reg_ch6pcr_o : out std_logic_vector(31 downto 0);
reg_ch6pcr_i : in std_logic_vector(31 downto 0);
reg_ch6pcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'TAI seconds counter bits 31..0' in reg: 'TVLR'
reg_tvlr_o : out std_logic_vector(31 downto 0);
reg_tvlr_i : in std_logic_vector(31 downto 0);
reg_tvlr_load_o : out std_logic;
-- Port for std_logic_vector field: 'TAI seconds counter bits 39..32' in reg: 'TVHR'
reg_tvhr_o : out std_logic_vector(7 downto 0);
reg_tvhr_i : in std_logic_vector(7 downto 0);
reg_tvhr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Channel mask' in reg: 'TBMR'
reg_tbmr_chan_i : in std_logic_vector(5 downto 0);
-- Port for BIT field: 'White Rabbit present' in reg: 'TBMR'
reg_tbmr_wrtag_i : in std_logic;
-- Tag buffer read request, asserted when reading from TBMR
reg_tb_rd_req_p_o : out std_logic;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'TBCYR'
reg_tbcyr_i : in std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'TBTLR'
reg_tbtlr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'TBTHR'
reg_tbthr_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'Buffer counter' in reg: 'TBCSR'
reg_tbcsr_usedw_i : in std_logic_vector(6 downto 0);
-- Port for BIT field: 'Buffer full' in reg: 'TBCSR'
reg_tbcsr_full_i : in std_logic;
-- Port for BIT field: 'Buffer empty' in reg: 'TBCSR'
reg_tbcsr_empty_i : in std_logic;
-- Ports for BIT field: 'Clear tag buffer' in reg: 'TBCSR'
reg_tbcsr_clr_o : out std_logic;
reg_tbcsr_clr_i : in std_logic;
reg_tbcsr_clr_load_o : out std_logic
);
end conv_regs;
architecture syn of conv_regs is
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(3 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
reg_sr_i2c_wdto_load_o <= '0';
reg_cr_rst_unlock_load_o <= '0';
reg_cr_rst_load_o <= '0';
reg_cr_mpt_wr_o <= '0';
reg_ch1pcr_load_o <= '0';
reg_ch2pcr_load_o <= '0';
reg_ch3pcr_load_o <= '0';
reg_ch4pcr_load_o <= '0';
reg_ch5pcr_load_o <= '0';
reg_ch6pcr_load_o <= '0';
reg_tvlr_load_o <= '0';
reg_tvhr_load_o <= '0';
reg_tbcsr_clr_load_o <= '0';
reg_tb_rd_req_p_o <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
reg_sr_i2c_wdto_load_o <= '0';
reg_cr_rst_unlock_load_o <= '0';
reg_cr_rst_load_o <= '0';
reg_cr_mpt_wr_o <= '0';
reg_ch1pcr_load_o <= '0';
reg_ch2pcr_load_o <= '0';
reg_ch3pcr_load_o <= '0';
reg_ch4pcr_load_o <= '0';
reg_ch5pcr_load_o <= '0';
reg_ch6pcr_load_o <= '0';
reg_tvlr_load_o <= '0';
reg_tvhr_load_o <= '0';
reg_tbcsr_clr_load_o <= '0';
reg_tb_rd_req_p_o <= '0';
ack_in_progress <= '0';
else
reg_sr_i2c_wdto_load_o <= '0';
reg_cr_rst_unlock_load_o <= '0';
reg_cr_rst_load_o <= '0';
reg_cr_mpt_wr_o <= '0';
reg_ch1pcr_load_o <= '0';
reg_ch2pcr_load_o <= '0';
reg_ch3pcr_load_o <= '0';
reg_ch4pcr_load_o <= '0';
reg_ch5pcr_load_o <= '0';
reg_ch6pcr_load_o <= '0';
reg_tvlr_load_o <= '0';
reg_tvhr_load_o <= '0';
reg_tbcsr_clr_load_o <= '0';
reg_tb_rd_req_p_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(3 downto 0) is
when "0000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= reg_bidr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0001" =>
if (wb_we_i = '1') then
reg_sr_i2c_wdto_load_o <= '1';
end if;
rddata_reg(7 downto 0) <= reg_sr_gwvers_i;
rddata_reg(15 downto 8) <= reg_sr_switches_i;
rddata_reg(21 downto 16) <= reg_sr_rtm_i;
rddata_reg(22) <= reg_sr_i2c_wdto_i;
rddata_reg(23) <= reg_sr_wrpres_i;
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0010" =>
if (wb_we_i = '1') then
reg_cr_rst_unlock_load_o <= '1';
reg_cr_rst_load_o <= '1';
reg_cr_mpt_wr_o <= '1';
end if;
rddata_reg(0) <= reg_cr_rst_unlock_i;
rddata_reg(1) <= reg_cr_rst_i;
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0011" =>
if (wb_we_i = '1') then
reg_ch1pcr_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= reg_ch1pcr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0100" =>
if (wb_we_i = '1') then
reg_ch2pcr_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= reg_ch2pcr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0101" =>
if (wb_we_i = '1') then
reg_ch3pcr_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= reg_ch3pcr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0110" =>
if (wb_we_i = '1') then
reg_ch4pcr_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= reg_ch4pcr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0111" =>
if (wb_we_i = '1') then
reg_ch5pcr_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= reg_ch5pcr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1000" =>
if (wb_we_i = '1') then
reg_ch6pcr_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= reg_ch6pcr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1001" =>
if (wb_we_i = '1') then
reg_tvlr_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= reg_tvlr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1010" =>
if (wb_we_i = '1') then
reg_tvhr_load_o <= '1';
end if;
rddata_reg(7 downto 0) <= reg_tvhr_i;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1011" =>
if (wb_we_i = '1') then
end if;
reg_tb_rd_req_p_o <= '1';
rddata_reg(5 downto 0) <= reg_tbmr_chan_i;
rddata_reg(31) <= reg_tbmr_wrtag_i;
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(27 downto 0) <= reg_tbcyr_i;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= reg_tbtlr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= reg_tbthr_i;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1111" =>
if (wb_we_i = '1') then
reg_tbcsr_clr_load_o <= '1';
end if;
rddata_reg(6 downto 0) <= reg_tbcsr_usedw_i;
rddata_reg(16) <= reg_tbcsr_full_i;
rddata_reg(17) <= reg_tbcsr_empty_i;
rddata_reg(18) <= reg_tbcsr_clr_i;
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- ID register bits
-- Gateware version
-- Status of on-board switches
-- RTM detection lines~\cite{rtm-det}
-- Communication watchdog timer status
reg_sr_i2c_wdto_o <= wrdata_reg(22);
-- White Rabbit present
-- Reset unlock bit
reg_cr_rst_unlock_o <= wrdata_reg(0);
-- Reset bit
reg_cr_rst_o <= wrdata_reg(1);
-- Manual Pulse Trigger
-- pass-through field: Manual Pulse Trigger in register: CR
reg_cr_mpt_o <= wrdata_reg(9 downto 2);
-- Pulse counter value
reg_ch1pcr_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
reg_ch2pcr_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
reg_ch3pcr_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
reg_ch4pcr_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
reg_ch5pcr_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
reg_ch6pcr_o <= wrdata_reg(31 downto 0);
-- TAI seconds counter bits 31..0
reg_tvlr_o <= wrdata_reg(31 downto 0);
-- TAI seconds counter bits 39..32
reg_tvhr_o <= wrdata_reg(7 downto 0);
-- Channel mask
-- White Rabbit present
-- Cycles counter
-- Lower part of TAI seconds counter
-- Upper part of TAI seconds counter
-- Buffer counter
-- Buffer full
-- Buffer empty
-- Clear tag buffer
reg_tbcsr_clr_o <= wrdata_reg(18);
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/modules/Release/conv_regs.wb 0000664 0000000 0000000 00000021120 12314554267 0027500 0 ustar 00root root 0000000 0000000 peripheral {
name = "Converter board registers";
hdl_entity = "conv_regs";
prefix = "reg";
-- Board ID register
reg {
name = "BIDR";
description = "Board ID Register";
prefix = "bidr";
reset_value = "0x54424c4f";
field {
name = "ID register bits";
reset_value = "0x54424c4f";
type = SLV;
size = 32;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
-- Status register
reg {
name = "SR";
description = "Status Register";
prefix = "sr";
field {
name = "Gateware version";
description = "Leftmost nibble hex value is major release decimal value \
Rightmost nibble hex value is minor release decimal value \
e.g. \
0x11 -- v1.1 \
0x1e -- v1.14 \
0x20 -- v2.0";
prefix = "gwvers";
type = SLV;
size = 8;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "Status of on-board switches";
description = "0 -- switch is ON \
1 -- switch is OFF \
bit 0 -- SW1.1 \
bit 1 -- SW1.2 \
... \
bit 4 -- SW2.1 \
... \
bit 7 -- SW2.4";
prefix = "switches";
type = SLV;
size = 8;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "RTM detection lines~\\cite{rtm-det}";
description = "0 -- line active \
1 -- line inactive";
prefix = "rtm";
type = SLV;
size = 6;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "Communication watchdog timer status";
description = "1 -- timeout occured \
0 -- no timeout \
This bit can be cleared by writing a '1' to it";
prefix = "i2c_wdto";
type = BIT;
size = 1;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "White Rabbit present";
description = "1 -- White Rabbit present \
0 -- White Rabbit not present";
prefix = "wrpres";
type = BIT;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
-- Control Register
reg {
name = "CR";
description = "Control Register";
prefix = "cr";
-- Logic reset bits
field {
name = "Reset unlock bit";
description = "1 -- Reset bit unlocked \
0 -- Reset bit locked";
prefix = "rst_unlock";
type = BIT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Reset bit";
description = "1 -- initiate logic reset \
0 -- no reset";
prefix = "rst";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Manual Pulse Trigger";
description = "Write the following sequence to trigger a pulse: \
0xde -- Byte 1 of magic sequence \
0xad -- Byte 2 of magic sequence \
0xbe -- Byte 3 of magic sequence \
0xef -- Byte 4 of magic sequence \
Number in range 1..6 -- trigger a pulse";
prefix = "mpt";
size = 8;
type = PASS_THROUGH;
};
};
-- Pulse counter registers, R/W access from SysMon
reg {
name = "CH1PCR";
description = "Channel 1 Pulse Counter Register";
prefix = "ch1pcr";
field {
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH2PCR";
description = "Channel 2 Pulse Counter Register";
prefix = "ch2pcr";
field {
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH3PCR";
description = "Channel 3 Pulse Counter Register";
prefix = "ch3pcr";
field {
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH4PCR";
description = "Channel 4 Pulse Counter Register";
prefix = "ch4pcr";
field {
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH5PCR";
description = "Channel 5 Pulse Counter Register";
prefix = "ch5pcr";
field {
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH6PCR";
description = "Channel 6 Pulse Counter Register";
prefix = "ch6pcr";
field {
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "TVLR";
description = "Time Value Low Register";
prefix = "tvlr";
field {
name = "TAI seconds counter bits 31..0";
description = "Writing this field resets the internal cycles counter.";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "TVHR";
description = "Time Value High Register";
prefix = "tvhr";
field {
name = "TAI seconds counter bits 39..32";
description = "Writing this field resets the internal cycles counter.";
type = SLV;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "TBMR";
description = "Tag Buffer Meta Register";
prefix = "tbmr";
field {
name = "Channel mask";
description = "Mask for the channel(s) that triggered time-tag storage: \
bit 0 -- channel 1 \
bit 1 -- channel 2 \
... \
bit 5 -- channel 6";
prefix = "chan";
type = SLV;
size = 6;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "White Rabbit present";
description = "1 - Current time tag generated with White Rabbit \
0 - Current time tag generated with internal counter";
prefix = "wrtag";
type = BIT;
align = 31;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "TBCYR";
description = "Tag Buffer Cycles Register";
prefix = "tbcyr";
field {
name = "Cycles counter";
description = "Value of the 8-ns cycles counter when time tag was taken.";
type = SLV;
size = 28;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "TBTLR";
description = "Tag Buffer TAI Low Register";
prefix = "tbtlr";
field {
name = "Lower part of TAI seconds counter";
description = "Value of the TAI seconds counter bits 31..0 when time tag was taken.";
type = SLV;
size = 32;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "TBTHR";
description = "Tag Buffer TAI High Register";
prefix = "tbthr";
field {
name = "Upper part of TAI seconds counter";
description = "Value of the TAI seconds counter bits 39..32 when time tag was taken.";
type = SLV;
size = 8;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "TBCSR";
description = "Tag Buffer Control and Status Register";
prefix = "tbcsr";
field {
name = "Buffer counter";
prefix = "usedw";
description = "Number of samples in the ring buffer";
type = SLV;
size = 7;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "Buffer full";
description = "1 -- buffer full \
0 -- buffer is not full";
prefix = "full";
type = BIT;
align = 16;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "Buffer empty";
description = "1 -- buffer empty\
0 -- buffer is not empty";
prefix = "empty";
type = BIT;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "Clear tag buffer";
description = "1 -- clear\
0 -- no effect";
prefix = "clr";
type = BIT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
};
};
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/modules/Release/conv_ring_buf.vhd 0000664 0000000 0000000 00000017510 12314554267 0030514 0 ustar 00root root 0000000 0000000 --==============================================================================
-- CERN (BE-CO-HT)
-- Ring buffer for converter board designs
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2014-03-19
--
-- version: 1.0
--
-- description:
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2014-03-19 Theodor Stana Created file and copied content from
-- fd_ring_buffer.
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.genram_pkg.all;
entity conv_ring_buf is
generic
(
-- Buffer data input and output width
g_data_width : positive;
-- Buffer size in number of samples
g_size : positive
);
port
(
-- Clocks and reset
clk_rd_i : in std_logic;
clk_wr_i : in std_logic;
rst_n_a_i : in std_logic;
-- Buffer inputs
buf_dat_i : in std_logic_vector(g_data_width-1 downto 0);
buf_rd_req_i : in std_logic;
buf_wr_req_i : in std_logic;
buf_clr_i : in std_logic;
-- Buffer outputs
buf_dat_o : out std_logic_vector(g_data_width-1 downto 0);
buf_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
buf_full_o : out std_logic;
buf_empty_o : out std_logic
);
end entity conv_ring_buf;
architecture behav of conv_ring_buf is
--============================================================================
-- Type declarations
--============================================================================
--============================================================================
-- Constant declarations
--============================================================================
constant c_fifo_size : positive := 8;
--============================================================================
-- Signal declarations
--============================================================================
-- FIFO signals
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal fifo_read : std_logic;
signal fifo_read_d0 : std_logic;
signal fifo_write : std_logic;
signal fifo_in : std_logic_vector(g_data_width-1 downto 0);
signal fifo_out : std_logic_vector(g_data_width-1 downto 0);
-- Buffer signals
signal buf_write : std_logic;
signal buf_read : std_logic;
signal buf_wr_ptr : unsigned(f_log2_size(g_size)-1 downto 0);
signal buf_rd_ptr : unsigned(f_log2_size(g_size)-1 downto 0);
signal buf_wr_data : std_logic_vector(g_data_width-1 downto 0);
signal buf_rd_data : std_logic_vector(g_data_width-1 downto 0);
signal buf_count : unsigned(f_log2_size(g_size)-1 downto 0);
signal buf_empty : std_logic;
signal buf_full : std_logic;
signal buf_overflow : std_logic;
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Buffer FIFO and RAM
--============================================================================
-- Assign FIFO input and control
fifo_in <= buf_dat_i;
fifo_write <= not fifo_full and buf_wr_req_i;
fifo_read <= not fifo_empty;
-- Instantiate FIFO to synchronize data inputs from read clock to write clock
cmp_clk_adjust_fifo : generic_async_fifo
generic map
(
g_data_width => fifo_in'length,
g_size => c_fifo_size
)
port map (
rst_n_i => rst_n_a_i,
clk_wr_i => clk_wr_i,
d_i => fifo_in,
we_i => fifo_write,
wr_full_o => fifo_full,
clk_rd_i => clk_rd_i,
q_o => fifo_out,
rd_i => fifo_read,
rd_empty_o => fifo_empty);
-- Instantiate the actual buffer RAM
-- The buffer gets fed with data from the FIFO
buf_wr_data <= fifo_out;
cmp_buf_ram : generic_dpram
generic map (
g_data_width => g_data_width,
g_size => g_size,
g_dual_clock => false)
port map (
rst_n_i => rst_n_a_i,
clka_i => clk_rd_i,
bwea_i => (others => '1'),
wea_i => buf_write,
aa_i => std_logic_vector(buf_wr_ptr),
da_i => buf_wr_data,
qa_o => open,
clkb_i => clk_rd_i,
bweb_i => (others => '0'),
web_i => '0',
ab_i => std_logic_vector(buf_rd_ptr),
db_i => (others => '0'),
qb_o => buf_rd_data);
--============================================================================
-- Buffer control
--============================================================================
-- Assign buffer control signals
buf_write <= fifo_read_d0;
buf_read <= '1' when ((buf_rd_req_i = '1') and (buf_empty = '0')) or
(buf_overflow = '1')
else '0';
buf_overflow <= '1' when (buf_write = '1') and (buf_full = '1') else '0';
-- Buffer control process
p_buffer_control : process(clk_rd_i)
begin
if rising_edge(clk_rd_i) then
if (rst_n_a_i = '0') or (buf_clr_i = '1') then
buf_rd_ptr <= (others => '0');
buf_wr_ptr <= (others => '0');
buf_count <= (others => '0');
buf_full <= '0';
buf_empty <= '1';
fifo_read_d0 <= '0';
else
fifo_read_d0 <= fifo_read;
-- Read and write signals
if(buf_write = '1') then
buf_wr_ptr <= buf_wr_ptr + 1;
end if;
if(buf_read = '1') then
buf_rd_ptr <= buf_rd_ptr + 1;
end if;
-- Buffer count and full/empty control
if (buf_write = '1') and (buf_read = '0') and (buf_full = '0') then
buf_count <= buf_count + 1;
buf_empty <= '0';
if (buf_count = (buf_count'range => '1')) then
buf_full <= '1';
end if;
end if;
if (buf_write = '0') and (buf_read = '1') and (buf_empty = '0') then
buf_count <= buf_count - 1;
buf_full <= '0';
if (buf_count = 1) then
buf_empty <= '1';
end if;
end if;
end if;
end if;
end process;
--============================================================================
-- Output signals
--============================================================================
buf_full_o <= buf_full;
buf_empty_o <= buf_empty;
buf_count_o <= std_logic_vector(buf_count);
buf_dat_o <= buf_rd_data;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/modules/Release/ctblo_pulse_gen.vhd 0000664 0000000 0000000 00000031625 12314554267 0031043 0 ustar 00root root 0000000 0000000 --==============================================================================
-- CERN (BE-CO-HT)
-- Pulse generator with trigger
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-03-01
--
-- version: 1.0
--
-- description:
-- This module generates a constant-width pulse. The width is set using the
-- g_pwidth generic, given in number of clk_i cycles. With a clk_i period of
-- 50 ns, the output pulse width is by default 50*24=1.2 us.
--
-- The module is designed to work with an external glitch filter. Enabling
-- this glitch filter will result in jitter on the leading edge of the
-- output pulse signal. This jitter can be avoided by bypassing the glitch
-- filter; this is done via the gf_en_n_i input.
--
-- Regardless of whether the glitch filter is enabled, the input trigger signal
-- is extended or cut to g_pwidth, if it is shorter or respectively longer than
-- g_pwidth. At the end of the pulse, a rejection phase is implemented in order
-- to avoid too many pulses arriving on the input. This is to safeguard the
-- blocking output stage of the CONV-TTL-BLO boards. The isolation phase limits
-- the input pulse to 1/500 duty cycle.
--
-- dependencies:
-- none
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 01-03-2013 Theodor Stana File created.
-- 02-08-2013 Theodor Stana Implemented rejection phase.
-- 17-02-2014 Theodor Stana Moved the glitch filter to outside the
-- module.
-- 04-03-2014 Theodor Stana Added first pulse inhibit on glitch-filtered
-- side.
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ctblo_pulse_gen is
generic
(
-- Pulse width, in number of clk_i cycles
-- Default pulse width (20 MHz clock): 1.2 us
-- Minimum allowable pulse width (20 MHz clock): 1 us
-- Maximum allowable pulse width (20 MHz clock): 2 us
g_pwidth : natural range 20 to 40 := 24;
-- Duty cycle divider: D = 1/g_duty_cycle_div
g_duty_cycle_div : natural := 5
);
port
(
-- Clock and active-low reset inputs
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Glitch filter enable input
-- '1' - Glitch filter disabled (glitch-sensitive, no output jitter)
-- '0' - Glitch filter enabled (glitch-insensitive, with output jitter)
gf_en_n_i : in std_logic;
-- Enable input, pulse generation is enabled when '1'
en_i : in std_logic;
-- Trigger input, has to be '1' to assure pulse output with delay no greater
-- than internal gate delays.
trig_a_i : in std_logic;
-- Pulse output, active-high
-- latency:
-- glitch filter disabled: none
-- glitch filter enabled: glitch filter length + 5 clk_i cycles
pulse_o : out std_logic
);
end entity ctblo_pulse_gen;
architecture behav of ctblo_pulse_gen is
--============================================================================
-- Type declarations
--============================================================================
type t_state is (
IDLE, -- idle state, wait for pulse
GEN_GF_OFF, -- pulse generation, glitch filter off
REJ_GF_OFF, -- pulse rejection, glitch filter off
GEN_GF_ON, -- pulse generation, glitch filter on
REJ_GF_ON -- pulse rejection, glitch filter on
);
--============================================================================
-- Constant declarations
--============================================================================
-- Max value of pulse counter for pulse width and pulse rejection width.
-- glitch filter OFF:
-- generate:
-- * g_pwidth-1: counter starts from 0
-- * g_pwidth-4: three-cycle delay through synchronizer
-- * g_pwidth-5: reset signal applied in REJ_GF_OFF state
-- reject:
-- * g_duty_cycle_div*g_pwidth: D duty cycle
-- * g_duty_cycle_div*g_pwidth-5: 5-cycle delay added from the generate phase
-- glitch filter ON:
-- generate:
-- * g_pwidth-1: counter starts from 0
-- reject:
-- * g_duty_cycle_div*g_pwidth: D duty cycle
-- * g_duty_cycle_div*g_pwidth-2: need one cycle less to allow for true 1/D
-- duty cycle,
-- since the FSM needs to go through IDLE to accept a pulse
constant c_max_gen_gf_off : natural := g_pwidth-5;
constant c_max_rej_gf_off : natural := g_duty_cycle_div*g_pwidth - 5;
constant c_max_gen_gf_on : natural := g_pwidth-1;
constant c_max_rej_gf_on : natural := g_duty_cycle_div*g_pwidth - 2;
--============================================================================
-- Function and procedure declarations
--============================================================================
function f_log2_size (A : natural) return natural is
begin
for I in 1 to 64 loop -- Works for up to 64 bits
if (2**I >= A) then
return(I);
end if;
end loop;
return(63);
end function f_log2_size;
--============================================================================
-- Signal declarations
--============================================================================
-- Trigger signals
signal pulse_gf_off_d0 : std_logic;
signal pulse_gf_off_d1 : std_logic;
signal pulse_gf_off_d2 : std_logic;
signal trig_gf_on : std_logic;
signal trig_gf_on_d0 : std_logic;
-- Pulse output signals
signal pulse_gf_on : std_logic;
signal pulse_gf_off : std_logic;
signal pulse_gf_off_rst : std_logic;
-- Inhibit first pulse
signal inh_fp_gf_on : std_logic;
-- Pulse length counter
signal pulse_cnt : unsigned(f_log2_size(g_duty_cycle_div*g_pwidth)-1 downto 0);
-- FSM signal
signal state : t_state;
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Output logic
--============================================================================
pulse_o <= pulse_gf_off when (gf_en_n_i = '1') else
pulse_gf_on;
--============================================================================
-- Pulse generation logic
--============================================================================
-- Generate the pulse on rising edge of trig_a_i
p_pulse_gf_off: process(pulse_gf_off_rst, trig_a_i)
begin
if (pulse_gf_off_rst = '1') then
pulse_gf_off <= '0';
elsif rising_edge(trig_a_i) then
if (en_i = '1') and (gf_en_n_i = '1') then
pulse_gf_off <= '1';
end if;
end if;
end process p_pulse_gf_off;
-- and synchronize the trigger in clk_i domain
p_sync_pulse_gf_off: process (clk_i) is
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
pulse_gf_off_d0 <= '0';
pulse_gf_off_d1 <= '0';
pulse_gf_off_d2 <= '0';
elsif (en_i = '1') and (gf_en_n_i = '1') then
pulse_gf_off_d0 <= pulse_gf_off;
pulse_gf_off_d1 <= pulse_gf_off_d0;
pulse_gf_off_d2 <= pulse_gf_off_d1;
end if;
end if;
end process p_sync_pulse_gf_off;
--============================================================================
-- Pulse width adjustment logic
--============================================================================
-- Trigger signal with glitch filter ON is input signal
trig_gf_on <= trig_a_i;
-- Generate the FSM logic
p_pulse_width: process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
state <= IDLE;
pulse_gf_off_rst <= '1';
pulse_gf_on <= '0';
pulse_cnt <= (others => '0');
trig_gf_on_d0 <= '0';
inh_fp_gf_on <= '1';
elsif (en_i = '1') then
-- Deglitched trigger delay.
trig_gf_on_d0 <= trig_gf_on;
-- On the first cycle after the reset, the pulse channel needs to be
-- inhibited when the converter board is in TTL-BAR repetition mode,
-- since in this mode, an unconnected channel is HIGH for the first
-- 100us until the "no signal detect" block triggers, and the HIGH level
-- on the line will get interpreted by the trigger delay (due to its reset
-- state) as a rising edge on the line, thus triggering a pulse.
if inh_fp_gf_on = '1' then
inh_fp_gf_on <= '0';
end if;
-- State machine logic
case state is
---------------------------------------------------------------------
-- IDLE
---------------------------------------------------------------------
-- Clear all values and go to pulse generation state when the
-- appropriate input arrives
---------------------------------------------------------------------
when IDLE =>
pulse_cnt <= (others => '0');
pulse_gf_off_rst <= '0';
if (gf_en_n_i = '1') then
if (pulse_gf_off_d1 = '1') and (pulse_gf_off_d2 = '0') then
state <= GEN_GF_OFF;
end if;
else
if (trig_gf_on = '1') and (trig_gf_on_d0 = '0') and
(inh_fp_gf_on = '0') then
state <= GEN_GF_ON;
end if;
end if;
---------------------------------------------------------------------
-- GEN_GF_OFF
---------------------------------------------------------------------
-- Extend the generated pulse to the required pulse width.
---------------------------------------------------------------------
when GEN_GF_OFF =>
pulse_cnt <= pulse_cnt + 1;
if (pulse_cnt = c_max_gen_gf_off) then
state <= REJ_GF_OFF;
end if;
---------------------------------------------------------------------
-- REJ_GF_OFF
---------------------------------------------------------------------
-- Cut and reject input pulses, to safeguard the output transformers.
---------------------------------------------------------------------
when REJ_GF_OFF =>
pulse_gf_off_rst <= '1';
pulse_cnt <= pulse_cnt + 1;
if (pulse_cnt = c_max_rej_gf_off) then
state <= IDLE;
end if;
---------------------------------------------------------------------
-- GEN_GF_ON
---------------------------------------------------------------------
-- Start generating the output pulse with the required width.
---------------------------------------------------------------------
when GEN_GF_ON =>
pulse_cnt <= pulse_cnt + 1;
pulse_gf_on <= '1';
if (pulse_cnt = c_max_gen_gf_on) then
state <= REJ_GF_ON;
end if;
---------------------------------------------------------------------
-- REJ_GF_ON
---------------------------------------------------------------------
-- Stop generating the output pulse and reject incoming pulses.
---------------------------------------------------------------------
when REJ_GF_ON =>
pulse_gf_on <= '0';
pulse_cnt <= pulse_cnt + 1;
if (pulse_cnt = c_max_rej_gf_on) then
state <= IDLE;
end if;
when others =>
state <= IDLE;
end case;
end if;
end if;
end process p_pulse_width;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/modules/bicolor_led_ctrl/ 0000775 0000000 0000000 00000000000 12314554267 0027106 5 ustar 00root root 0000000 0000000 conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/modules/bicolor_led_ctrl/Manifest.py 0000664 0000000 0000000 00000000117 12314554267 0031225 0 ustar 00root root 0000000 0000000 files = [
"bicolor_led_ctrl_pkg.vhd",
"bicolor_led_ctrl.vhd"
]
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/modules/bicolor_led_ctrl/README 0000664 0000000 0000000 00000000176 12314554267 0027772 0 ustar 00root root 0000000 0000000 Taken from:
http://www.ohwr.org/projects/svec/repository/revisions/master/show/hdl/top/bicolor_led_test
Revision: 220c7837
bicolor_led_ctrl.vhd 0000664 0000000 0000000 00000021760 12314554267 0033041 0 ustar 00root root 0000000 0000000 conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/modules/bicolor_led_ctrl --------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Bi-color LED controller
-- http://www.ohwr.org/projects/svec
--------------------------------------------------------------------------------
--
-- unit name: bicolor_led_ctrl
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 11-07-2012
--
-- version: 1.0
--
-- description: Bi-color LED controller. It controls a matrix of bi-color LED.
-- The FPGA ouputs for the columns (C) are connected to buffers
-- and serial resistances and then to the LEDs. The FPGA outputs
-- for lines (L) are connected to tri-state buffers and the to
-- the LEDs. The FPGA outputs for lines output enable (L_OEN) are
-- connected to the output enable of the tri-state buffers.
--
-- Example with three lines and two columns:
--
-- ||
--
-- L1/L2/L3 __|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__
--
-- L1_OEN -----|___________|-----|___________|-----|___________|-----|___________|--
--
-- L2_OEN _____|-----|___________|-----|___________|-----|___________|-----|________
--
-- L3_OEN ___________|-----|___________|-----|___________|-----|___________|-----|__
--
-- Cn __|--|__|--|__|--|_________________|-----------------|--|__|--|__|--|__|--
--
-- LED Ln/Cn OFF | color_1 | color_2 | both_colors |
--
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library work;
use work.bicolor_led_ctrl_pkg.all;
entity bicolor_led_ctrl is
generic(
g_NB_COLUMN : natural := 4;
g_NB_LINE : natural := 2;
g_CLK_FREQ : natural := 125000000; -- in Hz
g_REFRESH_RATE : natural := 250 -- in Hz
);
port
(
rst_n_i : in std_logic;
clk_i : in std_logic;
led_intensity_i : in std_logic_vector(6 downto 0);
led_state_i : in std_logic_vector((g_NB_LINE * g_NB_COLUMN * 2) - 1 downto 0);
column_o : out std_logic_vector(g_NB_COLUMN - 1 downto 0);
line_o : out std_logic_vector(g_NB_LINE - 1 downto 0);
line_oen_o : out std_logic_vector(g_NB_LINE - 1 downto 0)
);
end bicolor_led_ctrl;
architecture rtl of bicolor_led_ctrl is
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant c_REFRESH_CNT_INIT : natural := natural(g_CLK_FREQ/(2 * g_NB_LINE * g_REFRESH_RATE)) - 1;
constant c_REFRESH_CNT_NB_BITS : natural := log2_ceil(c_REFRESH_CNT_INIT);
constant c_LINE_OEN_CNT_NB_BITS : natural := log2_ceil(g_NB_LINE);
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
signal refresh_rate_cnt : unsigned(c_REFRESH_CNT_NB_BITS - 1 downto 0);
signal refresh_rate : std_logic;
signal line_ctrl : std_logic;
signal intensity_ctrl_cnt : unsigned(c_REFRESH_CNT_NB_BITS - 1 downto 0);
signal intensity_ctrl : std_logic;
signal line_oen_cnt : unsigned(c_LINE_OEN_CNT_NB_BITS - 1 downto 0);
signal line_oen : std_logic_vector(2**c_LINE_OEN_CNT_NB_BITS - 1 downto 0);
signal led_state : std_logic_vector((g_NB_LINE * g_NB_COLUMN) -1 downto 0);
begin
------------------------------------------------------------------------------
-- Refresh rate counter
------------------------------------------------------------------------------
p_refresh_rate_cnt : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
refresh_rate_cnt <= (others => '0');
refresh_rate <= '0';
elsif refresh_rate_cnt = 0 then
refresh_rate_cnt <= to_unsigned(c_REFRESH_CNT_INIT, c_REFRESH_CNT_NB_BITS);
refresh_rate <= '1';
else
refresh_rate_cnt <= refresh_rate_cnt - 1;
refresh_rate <= '0';
end if;
end if;
end process p_refresh_rate_cnt;
------------------------------------------------------------------------------
-- Intensity control
------------------------------------------------------------------------------
p_intensity_ctrl_cnt : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
intensity_ctrl_cnt <= (others => '0');
elsif refresh_rate = '1' then
intensity_ctrl_cnt <= to_unsigned(natural(c_REFRESH_CNT_INIT/100) * to_integer(unsigned(led_intensity_i)), c_REFRESH_CNT_NB_BITS);
else
intensity_ctrl_cnt <= intensity_ctrl_cnt - 1;
end if;
end if;
end process p_intensity_ctrl_cnt;
p_intensity_ctrl : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
intensity_ctrl <= '0';
elsif refresh_rate = '1' then
intensity_ctrl <= '1';
elsif intensity_ctrl_cnt = 0 then
intensity_ctrl <= '0';
end if;
end if;
end process p_intensity_ctrl;
------------------------------------------------------------------------------
-- Lines ouput
------------------------------------------------------------------------------
p_line_ctrl : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
line_ctrl <= '0';
elsif refresh_rate = '1' then
line_ctrl <= not(line_ctrl);
end if;
end if;
end process p_line_ctrl;
f_line_o : for I in 0 to g_NB_LINE - 1 generate
line_o(I) <= line_ctrl and intensity_ctrl;
end generate f_line_o;
------------------------------------------------------------------------------
-- Lines output enable
------------------------------------------------------------------------------
p_line_oen_cnt : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
line_oen_cnt <= (others => '0');
elsif line_ctrl = '1' and refresh_rate = '1' then
if line_oen_cnt = 0 then
line_oen_cnt <= to_unsigned(g_NB_LINE - 1, c_LINE_OEN_CNT_NB_BITS);
else
line_oen_cnt <= line_oen_cnt - 1;
end if;
end if;
end if;
end process p_line_oen_cnt;
p_line_oen_decode : process(line_oen_cnt)
variable v_onehot : std_logic_vector((2**line_oen_cnt'length)-1 downto 0);
variable v_index : integer range 0 to (2**line_oen_cnt'length)-1;
begin
v_onehot := (others => '0');
v_index := 0;
for i in line_oen_cnt'range loop
if (line_oen_cnt(i) = '1') then
v_index := 2*v_index+1;
else
v_index := 2*v_index;
end if;
end loop;
v_onehot(v_index) := '1';
line_oen <= v_onehot;
end process p_line_oen_decode;
line_oen_o <= line_oen(line_oen_o'left downto 0);
------------------------------------------------------------------------------
-- Columns output
------------------------------------------------------------------------------
f_led_state : for I in 0 to (g_NB_COLUMN * g_NB_LINE) - 1 generate
led_state(I) <= '0' when led_state_i(2 * I + 1 downto 2 * I) = c_LED_RED else
'1' when led_state_i(2 * I + 1 downto 2 * I) = c_LED_GREEN else
not(line_ctrl and intensity_ctrl) when led_state_i(2 * I + 1 downto 2 * I) = c_LED_RED_GREEN else
(line_ctrl and intensity_ctrl);-- when led_state_i(2 * I + 1 downto 2 * I) = c_LED_OFF else
end generate f_led_state;
f_column_o : for C in 0 to g_NB_COLUMN - 1 generate
column_o(C) <= led_state(g_NB_COLUMN * to_integer(line_oen_cnt) + C);
end generate f_column_o;
end rtl;
bicolor_led_ctrl_pkg.vhd 0000664 0000000 0000000 00000007456 12314554267 0033710 0 ustar 00root root 0000000 0000000 conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/modules/bicolor_led_ctrl --------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Bi-color LED controller package
-- http://www.ohwr.org/projects/svec
--------------------------------------------------------------------------------
--
-- unit name: bicolor_led_ctrl_pkg
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 11-07-2012
--
-- version: 1.0
--
-- description: Package for Bi-color LED controller.
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
package bicolor_led_ctrl_pkg is
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant c_LED_RED : std_logic_vector(1 downto 0) := "10";
constant c_LED_GREEN : std_logic_vector(1 downto 0) := "01";
constant c_LED_RED_GREEN : std_logic_vector(1 downto 0) := "11";
constant c_LED_OFF : std_logic_vector(1 downto 0) := "00";
------------------------------------------------------------------------------
-- Functions declaration
------------------------------------------------------------------------------
function log2_ceil(N : natural) return positive;
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component bicolor_led_ctrl
generic(
g_NB_COLUMN : natural := 4;
g_NB_LINE : natural := 2;
g_CLK_FREQ : natural := 125000000; -- in Hz
g_REFRESH_RATE : natural := 250 -- in Hz
);
port
(
rst_n_i : in std_logic;
clk_i : in std_logic;
led_intensity_i : in std_logic_vector(6 downto 0);
led_state_i : in std_logic_vector((g_NB_LINE * g_NB_COLUMN * 2) - 1 downto 0);
column_o : out std_logic_vector(g_NB_COLUMN - 1 downto 0);
line_o : out std_logic_vector(g_NB_LINE - 1 downto 0);
line_oen_o : out std_logic_vector(g_NB_LINE - 1 downto 0)
);
end component;
end bicolor_led_ctrl_pkg;
package body bicolor_led_ctrl_pkg is
------------------------------------------------------------------------------
-- Function : Returns log of 2 of a natural number
------------------------------------------------------------------------------
function log2_ceil(N : natural) return positive is
begin
if N <= 2 then
return 1;
elsif N mod 2 = 0 then
return 1 + log2_ceil(N/2);
else
return 1 + log2_ceil((N+1)/2);
end if;
end;
end bicolor_led_ctrl_pkg;
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/modules/pulsetest/ 0000775 0000000 0000000 00000000000 12314554267 0025635 5 ustar 00root root 0000000 0000000 conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/modules/pulsetest/Manifest.py 0000664 0000000 0000000 00000000146 12314554267 0027756 0 ustar 00root root 0000000 0000000 files = [
"conv_regs.vhd",
"pulse_cnt_regs.vhd",
"pgen_ctrl_regs.vhd",
"pulse_gen_gp.vhd"
]
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/modules/pulsetest/conv_regs.vhd 0000664 0000000 0000000 00000017704 12314554267 0030336 0 ustar 00root root 0000000 0000000 ---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Converter board registers
---------------------------------------------------------------------------------------
-- File : conv_regs.vhd
-- Author : auto-generated by wbgen2 from conv_regs.wb
-- Created : Sat Dec 7 14:11:02 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE conv_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity conv_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'bits' in reg: 'Board ID Register'
reg_id_bits_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'fwvers' in reg: 'Status Register'
reg_sr_fwvers_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'switches' in reg: 'Status Register'
reg_sr_switches_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'RTM detection' in reg: 'Status Register'
reg_sr_rtm_i : in std_logic_vector(5 downto 0);
-- Ports for BIT field: 'I2C Watchdog Timeout' in reg: 'Status Register'
reg_sr_i2c_wdto_o : out std_logic;
reg_sr_i2c_wdto_i : in std_logic;
reg_sr_i2c_wdto_load_o : out std_logic;
-- Ports for BIT field: 'Reset unlock bit' in reg: 'Control Register'
reg_cr_rst_unlock_o : out std_logic;
reg_cr_rst_unlock_i : in std_logic;
reg_cr_rst_unlock_load_o : out std_logic;
-- Ports for BIT field: 'Reset bit' in reg: 'Control Register'
reg_cr_rst_o : out std_logic;
reg_cr_rst_i : in std_logic;
reg_cr_rst_load_o : out std_logic
);
end conv_regs;
architecture syn of conv_regs is
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
reg_sr_i2c_wdto_load_o <= '0';
reg_cr_rst_unlock_load_o <= '0';
reg_cr_rst_load_o <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
reg_sr_i2c_wdto_load_o <= '0';
reg_cr_rst_unlock_load_o <= '0';
reg_cr_rst_load_o <= '0';
ack_in_progress <= '0';
else
reg_sr_i2c_wdto_load_o <= '0';
reg_cr_rst_unlock_load_o <= '0';
reg_cr_rst_load_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= reg_id_bits_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
if (wb_we_i = '1') then
reg_sr_i2c_wdto_load_o <= '1';
end if;
rddata_reg(7 downto 0) <= reg_sr_fwvers_i;
rddata_reg(15 downto 8) <= reg_sr_switches_i;
rddata_reg(21 downto 16) <= reg_sr_rtm_i;
rddata_reg(22) <= reg_sr_i2c_wdto_i;
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
if (wb_we_i = '1') then
reg_cr_rst_unlock_load_o <= '1';
reg_cr_rst_load_o <= '1';
end if;
rddata_reg(0) <= reg_cr_rst_unlock_i;
rddata_reg(1) <= reg_cr_rst_i;
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- bits
-- fwvers
-- switches
-- RTM detection
-- I2C Watchdog Timeout
reg_sr_i2c_wdto_o <= wrdata_reg(22);
-- Reset unlock bit
reg_cr_rst_unlock_o <= wrdata_reg(0);
-- Reset bit
reg_cr_rst_o <= wrdata_reg(1);
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/modules/pulsetest/conv_regs.wb 0000664 0000000 0000000 00000005646 12314554267 0030167 0 ustar 00root root 0000000 0000000 peripheral {
name = "Converter board registers";
hdl_entity = "conv_regs";
prefix = "reg";
reg {
name = "Board ID Register";
description = "Bits of ID register, defaulting to ASCII string TBLO";
prefix = "id";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "Status Register";
description = "Contains various board status information";
prefix = "sr";
field {
name = "fwvers";
prefix = "fwvers";
type = SLV;
size = 8;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "switches";
prefix = "switches";
type = SLV;
size = 8;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "RTM detection";
prefix = "rtm";
type = SLV;
size = 6;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "I2C Watchdog Timeout";
prefix = "i2c_wdto";
type = BIT;
size = 1;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "Control Register";
description = "Contains bits that control operation of the converter modules";
prefix = "cr";
-- field {
-- name = "blocking chan 1 enable";
-- prefix = "bch1_en";
-- type = BIT;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- field {
-- name = "blocking chan 2 enable";
-- prefix = "bch2_en";
-- type = BIT;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- field {
-- name = "blocking chan 3 enable";
-- prefix = "bch3_en";
-- type = BIT;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- field {
-- name = "blocking chan 4 enable";
-- prefix = "bch4_en";
-- type = BIT;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- field {
-- name = "blocking chan 5 enable";
-- prefix = "bch5_en";
-- type = BIT;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- field {
-- name = "blocking chan 6 enable";
-- prefix = "bch6_en";
-- type = BIT;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
field {
name = "Reset unlock bit";
prefix = "rst_unlock";
description = "1 - Reset bit unlocked\
0 - Reset bit locked";
type = BIT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Reset bit";
prefix = "rst";
description = "1 - initiate logic reset\
0 - no reset";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
};
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/modules/pulsetest/pgen_ctrl_regs.vhd 0000664 0000000 0000000 00000043214 12314554267 0031341 0 ustar 00root root 0000000 0000000 ---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Pulse generation control registers
---------------------------------------------------------------------------------------
-- File : pgen_ctrl_regs.vhd
-- Author : auto-generated by wbgen2 from pgen_ctrl_regs.wb
-- Created : Fri Aug 16 11:22:20 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pgen_ctrl_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pgen_ctrl_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'channel enable' in reg: 'Enable register'
pgen_ctrl_regs_en_ch_o : out std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH1 delay register'
pgen_ctrl_regs_ch1_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH2 delay register'
pgen_ctrl_regs_ch2_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH3 delay register'
pgen_ctrl_regs_ch3_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH4 delay register'
pgen_ctrl_regs_ch4_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH5 delay register'
pgen_ctrl_regs_ch5_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH6 delay register'
pgen_ctrl_regs_ch6_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH1 pulse width register'
pgen_ctrl_regs_ch1_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH2 pulse width register'
pgen_ctrl_regs_ch2_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH3 pulse width register'
pgen_ctrl_regs_ch3_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH4 pulse width register'
pgen_ctrl_regs_ch4_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH5 pulse width register'
pgen_ctrl_regs_ch5_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH6 pulse width register'
pgen_ctrl_regs_ch6_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH1 frequency register'
pgen_ctrl_regs_ch1_freq_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH2 frequency register'
pgen_ctrl_regs_ch2_freq_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH3 frequency register'
pgen_ctrl_regs_ch3_freq_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH4 frequency register'
pgen_ctrl_regs_ch4_freq_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH5 frequency register'
pgen_ctrl_regs_ch5_freq_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH6 frequency register'
pgen_ctrl_regs_ch6_freq_bits_o : out std_logic_vector(31 downto 0)
);
end pgen_ctrl_regs;
architecture syn of pgen_ctrl_regs is
signal pgen_ctrl_regs_en_ch_int : std_logic_vector(5 downto 0);
signal pgen_ctrl_regs_ch1_delay_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch2_delay_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch3_delay_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch4_delay_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch5_delay_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch6_delay_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch1_pwidth_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch2_pwidth_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch3_pwidth_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch4_pwidth_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch5_pwidth_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch6_pwidth_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch1_freq_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch2_freq_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch3_freq_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch4_freq_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch5_freq_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch6_freq_bits_int : std_logic_vector(31 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(4 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
pgen_ctrl_regs_en_ch_int <= "000000";
pgen_ctrl_regs_ch1_delay_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch2_delay_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch3_delay_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch4_delay_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch5_delay_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch6_delay_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch1_pwidth_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch2_pwidth_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch3_pwidth_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch4_pwidth_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch5_pwidth_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch6_pwidth_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch1_freq_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch2_freq_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch3_freq_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch4_freq_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch5_freq_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch6_freq_bits_int <= "00000000000000000000000000000000";
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(4 downto 0) is
when "00000" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_en_ch_int <= wrdata_reg(5 downto 0);
end if;
rddata_reg(5 downto 0) <= pgen_ctrl_regs_en_ch_int;
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch1_delay_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch1_delay_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch2_delay_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch2_delay_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch3_delay_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch3_delay_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch4_delay_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch4_delay_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch5_delay_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch5_delay_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch6_delay_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch6_delay_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch1_pwidth_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch1_pwidth_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch2_pwidth_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch2_pwidth_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch3_pwidth_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch3_pwidth_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch4_pwidth_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch4_pwidth_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch5_pwidth_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch5_pwidth_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch6_pwidth_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch6_pwidth_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch1_freq_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch1_freq_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch2_freq_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch2_freq_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch3_freq_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch3_freq_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch4_freq_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch4_freq_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch5_freq_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch5_freq_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch6_freq_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch6_freq_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- channel enable
pgen_ctrl_regs_en_ch_o <= pgen_ctrl_regs_en_ch_int;
-- bits
pgen_ctrl_regs_ch1_delay_bits_o <= pgen_ctrl_regs_ch1_delay_bits_int;
-- bits
pgen_ctrl_regs_ch2_delay_bits_o <= pgen_ctrl_regs_ch2_delay_bits_int;
-- bits
pgen_ctrl_regs_ch3_delay_bits_o <= pgen_ctrl_regs_ch3_delay_bits_int;
-- bits
pgen_ctrl_regs_ch4_delay_bits_o <= pgen_ctrl_regs_ch4_delay_bits_int;
-- bits
pgen_ctrl_regs_ch5_delay_bits_o <= pgen_ctrl_regs_ch5_delay_bits_int;
-- bits
pgen_ctrl_regs_ch6_delay_bits_o <= pgen_ctrl_regs_ch6_delay_bits_int;
-- bits
pgen_ctrl_regs_ch1_pwidth_bits_o <= pgen_ctrl_regs_ch1_pwidth_bits_int;
-- bits
pgen_ctrl_regs_ch2_pwidth_bits_o <= pgen_ctrl_regs_ch2_pwidth_bits_int;
-- bits
pgen_ctrl_regs_ch3_pwidth_bits_o <= pgen_ctrl_regs_ch3_pwidth_bits_int;
-- bits
pgen_ctrl_regs_ch4_pwidth_bits_o <= pgen_ctrl_regs_ch4_pwidth_bits_int;
-- bits
pgen_ctrl_regs_ch5_pwidth_bits_o <= pgen_ctrl_regs_ch5_pwidth_bits_int;
-- bits
pgen_ctrl_regs_ch6_pwidth_bits_o <= pgen_ctrl_regs_ch6_pwidth_bits_int;
-- bits
pgen_ctrl_regs_ch1_freq_bits_o <= pgen_ctrl_regs_ch1_freq_bits_int;
-- bits
pgen_ctrl_regs_ch2_freq_bits_o <= pgen_ctrl_regs_ch2_freq_bits_int;
-- bits
pgen_ctrl_regs_ch3_freq_bits_o <= pgen_ctrl_regs_ch3_freq_bits_int;
-- bits
pgen_ctrl_regs_ch4_freq_bits_o <= pgen_ctrl_regs_ch4_freq_bits_int;
-- bits
pgen_ctrl_regs_ch5_freq_bits_o <= pgen_ctrl_regs_ch5_freq_bits_int;
-- bits
pgen_ctrl_regs_ch6_freq_bits_o <= pgen_ctrl_regs_ch6_freq_bits_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/modules/pulsetest/pgen_ctrl_regs.wb 0000664 0000000 0000000 00000006720 12314554267 0031171 0 ustar 00root root 0000000 0000000 peripheral {
name = "Pulse generation control registers";
description = "Registers containing control signals for the general-purpose pulse generator blocks";
hdl_entity = "pgen_ctrl_regs";
prefix = "pgen_ctrl_regs";
reg {
name = "Enable register";
prefix = "en";
field {
name = "channel enable";
prefix = "ch";
type = SLV;
size = 6;
};
};
reg {
name = "CH1 delay register";
prefix = "ch1_delay";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH2 delay register";
prefix = "ch2_delay";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH3 delay register";
prefix = "ch3_delay";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH4 delay register";
prefix = "ch4_delay";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH5 delay register";
prefix = "ch5_delay";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH6 delay register";
prefix = "ch6_delay";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH1 pulse width register";
prefix = "ch1_pwidth";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH2 pulse width register";
prefix = "ch2_pwidth";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH3 pulse width register";
prefix = "ch3_pwidth";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH4 pulse width register";
prefix = "ch4_pwidth";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH5 pulse width register";
prefix = "ch5_pwidth";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH6 pulse width register";
prefix = "ch6_pwidth";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH1 frequency register";
prefix = "ch1_freq";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH2 frequency register";
prefix = "ch2_freq";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH3 frequency register";
prefix = "ch3_freq";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH4 frequency register";
prefix = "ch4_freq";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH5 frequency register";
prefix = "ch5_freq";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH6 frequency register";
prefix = "ch6_freq";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
};
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/modules/pulsetest/pulse_cnt_regs.vhd 0000664 0000000 0000000 00000023715 12314554267 0031364 0 ustar 00root root 0000000 0000000 ---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Pulse counter registers
---------------------------------------------------------------------------------------
-- File : pulse_cnt_regs.vhd
-- Author : auto-generated by wbgen2 from pulse_cnt_regs.wb
-- Created : Mon Sep 16 18:23:47 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pulse_cnt_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pulse_cnt_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH1 input'
pulse_cnt_ch1i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH1 output'
pulse_cnt_ch1o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH2 input'
pulse_cnt_ch2i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH2 output'
pulse_cnt_ch2o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH3 input'
pulse_cnt_ch3i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH3 output'
pulse_cnt_ch3o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH4 input'
pulse_cnt_ch4i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH4 output'
pulse_cnt_ch4o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH5 input'
pulse_cnt_ch5i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH5 output'
pulse_cnt_ch5o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH6 input'
pulse_cnt_ch6i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH6 output'
pulse_cnt_ch6o_val_i : in std_logic_vector(31 downto 0);
-- Port for BIT field: 'reset' in reg: 'Counter reset'
pulse_cnt_rst_bit_o : out std_logic
);
end pulse_cnt_regs;
architecture syn of pulse_cnt_regs is
signal pulse_cnt_rst_bit_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(3 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
pulse_cnt_rst_bit_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(3 downto 0) is
when "0000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch1i_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch1o_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch2i_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch2o_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch3i_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch3o_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch4i_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch4o_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch5i_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch5o_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch6i_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch6o_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1100" =>
if (wb_we_i = '1') then
pulse_cnt_rst_bit_int <= wrdata_reg(0);
end if;
rddata_reg(0) <= pulse_cnt_rst_bit_int;
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- reset
pulse_cnt_rst_bit_o <= pulse_cnt_rst_bit_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/modules/pulsetest/pulse_cnt_regs.wb 0000664 0000000 0000000 00000006025 12314554267 0031206 0 ustar 00root root 0000000 0000000 peripheral {
name = "Pulse counter registers";
description = "Registers containing the values for input and output generated pulses";
hdl_entity = "pulse_cnt_regs";
prefix = "pulse_cnt";
reg {
name = "CH1 input";
prefix = "ch1i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH1 output";
prefix = "ch1o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH2 input";
prefix = "ch2i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH2 output";
prefix = "ch2o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH3 input";
prefix = "ch3i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH3 output";
prefix = "ch3o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH4 input";
prefix = "ch4i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH4 output";
prefix = "ch4o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH5 input";
prefix = "ch5i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH5 output";
prefix = "ch5o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH6 input";
prefix = "ch6i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH6 output";
prefix = "ch6o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Counter reset";
prefix = "rst";
field {
name = "reset";
prefix = "bit";
type = BIT;
};
};
};
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/modules/pulsetest/pulse_gen_gp.vhd 0000664 0000000 0000000 00000013601 12314554267 0031010 0 ustar 00root root 0000000 0000000 --==============================================================================
-- CERN (BE-CO-HT)
-- General-purpose pulse generator
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-02-28
--
-- version: 2.0
--
-- description:
--
-- This module generates pulses with configurable frequency, width and delay.
--
-- In order to generate pulses, the module must be enabled via the en_i port.
-- Once en_i is high, pulses are generated at the frequency specified via
-- freq_i, with the width specified via pwidth_i.
--
-- An optional delay can be added before the start of the pulse, via the delay_i
-- port.
--
-- Note that this delay can be set only before the module is enabled.
--
-- freq_i, pwidth_i and delay_i are given in clk_i cycles.
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-02-28 Theodor Stana t.stana@cern.ch File created
-- 2013 08-15 Theodor Stana t.stana@cern.ch v2.0, delay, pwidth, freq
-- now controllable via
-- inputs (regs, etc.)
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pulse_gen_gp is
port
(
-- Input clock and active-low reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Active high enable signal
en_i : in std_logic;
-- Delay, pulse width and frequency inputs, in number of clk_i cycles
delay_i : in std_logic_vector(31 downto 0);
pwidth_i : in std_logic_vector(31 downto 0);
freq_i : in std_logic_vector(31 downto 0);
-- Output pulse signal
pulse_o : out std_logic
);
end entity pulse_gen_gp;
architecture behav of pulse_gen_gp is
--============================================================================
-- Function and procedure declarations
--============================================================================
function f_log2_size (A : natural) return natural is
begin
for I in 1 to 64 loop -- Works for up to 64 bits
if (2**I >= A) then
return(I);
end if;
end loop;
return(63);
end function f_log2_size;
--============================================================================
-- Signal declarations
--============================================================================
signal delay_int : unsigned(31 downto 0);
signal pwidth_int : unsigned(31 downto 0);
signal freq_int : unsigned(31 downto 0);
signal pulse_cnt : unsigned(31 downto 0);
signal delay_cnt : unsigned(31 downto 0);
signal delay_en : std_logic;
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Convert std_logic_vector inputs to unsigned
--============================================================================
delay_int <= unsigned(delay_i);
pwidth_int <= unsigned(pwidth_i);
freq_int <= unsigned(freq_i);
--============================================================================
-- Delay logic
--============================================================================
p_delay: process (clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') or (en_i = '0') then
delay_en <= '1';
delay_cnt <= (others => '0');
else
if (delay_int = (delay_int'range => '0')) then
delay_en <= '0';
elsif (delay_en = '1') then
delay_cnt <= delay_cnt + 1;
if (delay_cnt = delay_int) then
delay_en <= '0';
delay_cnt <= (others => '0');
end if;
end if;
end if;
end if;
end process p_delay;
--============================================================================
-- Pulse generation logic
--============================================================================
p_gen_pulse: process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') or (en_i = '0') then
pulse_cnt <= (others => '0');
pulse_o <= '0';
elsif (delay_en = '0') then
pulse_cnt <= pulse_cnt + 1;
pulse_o <= '0';
if (pulse_cnt < pwidth_int) then
pulse_o <= '1';
elsif (pulse_cnt = freq_int-1) then
pulse_cnt <= (others => '0');
end if;
end if;
end if;
end process p_gen_pulse;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/modules/reset_gen.vhd 0000664 0000000 0000000 00000010000 12314554267 0026252 0 ustar 00root root 0000000 0000000 --==============================================================================
-- CERN (BE-CO-HT)
-- Reset generator for CONV-TTL-* boards
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-03-05
--
-- version: 1.0
--
-- description:
-- This module generates a controllable-width reset pulse. The width of the
-- reset pulse is set via the g_reset_time pulse; an internal counter counts
-- up to this value and de-asserts the active-low reset line when the value
-- has been reached. At the same time, the module is de-activated.
--
-- By default, a 20 MHz clock (50 ns period) is assumed, resulting in a 100ms
-- reset width.
--
-- dependencies:
-- none
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-03-05 Theodor Stana File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity reset_gen is
generic
(
-- Reset time in number of clk_i cycles
g_reset_time : positive := 2_000_000
);
port
(
clk_i : in std_logic;
rst_i : in std_logic;
rst_n_o : out std_logic
);
end entity reset_gen;
architecture behav of reset_gen is
--============================================================================
-- Function and procedure declarations
--============================================================================
function f_log2_size (A : natural) return natural is
begin
for I in 1 to 64 loop -- Works for up to 64 bits
if (2**I >= A) then
return(I);
end if;
end loop;
return(63);
end function f_log2_size;
--============================================================================
-- Signal declarations
--============================================================================
signal cnt : unsigned(f_log2_size(g_reset_time)-1 downto 0) := (others => '0');
signal cnt_en : std_logic := '1';
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Reset generation logic
--============================================================================
p_rst_gen: process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_i = '1') then
cnt_en <= '1';
cnt <= (others => '0');
elsif (cnt_en = '1') then
rst_n_o <= '0';
cnt <= cnt + 1;
if (cnt = g_reset_time-1) then
rst_n_o <= '1';
cnt_en <= '0';
end if;
end if;
end if;
end process p_rst_gen;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/modules/rtm_detector.vhd 0000664 0000000 0000000 00000010427 12314554267 0027007 0 ustar 00root root 0000000 0000000 --==============================================================================
-- CERN (BE-CO-HT)
-- Rear transition module (RTM) detector
--==============================================================================
--
-- author: Carlos Gil Soriano
-- Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-01-09
--
-- version: 2.0
--
-- description:
--
-- This module detects the presence of rear transition module motherboards
-- (RTMMs) and piggybacks (RTMPs). Detection works by checking the RTMM and
-- RTMP input pins and these pins are pulled up on the front module. The
-- RTMM_OK and RTMP_OK ouputs are set if the corresponding inputs do not
-- yield errors. Different boards have the RTMM/P pins setup differently,
-- as outlined in the tables below:
--
-- Table 1. RTMM detection pins.
-- __________________________________________
-- | Board | RTMM[2] | RTMM[1] | RTMM[0] |
-- +-----------------------------------------+
-- | Error | '1' | '1' | '1' |
-- | RTMM_V1 | '1' | '1' | '0' |
-- | RTMM_V2 | '1' | '0' | '1' |
-- | Reserved | '1' | '0' | '0' |
-- | Reserved | '0' | '1' | '1' |
-- | Reserved | '0' | '1' | '0' |
-- | Reserved | '0' | '0' | '1' |
-- | Reserved | '0' | '0' | '0' |
-- +-----------+---------+---------+---------+
--
--
-- Table 2. RTMP detection pins.
-- _____________________________________________
-- | Board | RTMP[2] | RTMP[1] | RTMP[0] |
-- +-------------------------------------------+
-- | Error OR | '1' | '1' | '1' |
-- | Blocking_V1 | | | |
-- | RS485_V1 | '1' | '1' | '0' |
-- | -Reserved- | '1' | '0' | '1' |
-- | -Reserved- | '1' | '0' | '0' |
-- | -Reserved- | '0' | '1' | '1' |
-- | -Reserved- | '0' | '1' | '0' |
-- | -Reserved- | '0' | '0' | '1' |
-- | Error | '0' | '0' | '0' |
-- +-------------+---------+---------+---------+
--
--
-- dependencies:
-- none
--
-- references:
-- http://www.ohwr.org/projects/conv-ttl-blo/wiki/RTM_board_detection
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-01-09 Theodor Stana t.stana@cern.ch File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rtm_detector is
port
(
rtmm_i : in std_logic_vector(2 downto 0);
rtmp_i : in std_logic_vector(2 downto 0);
rtmm_ok_o : out std_logic;
rtmp_ok_o : out std_logic
);
end entity rtm_detector;
architecture behav of rtm_detector is
--==============================================================================
-- architecture begin
--==============================================================================
begin
rtmm_ok_o <= '0' when (rtmm_i = "111") else '1';
rtmp_ok_o <= '0' when (rtmp_i = "111") else '1';
end behav;
--==============================================================================
-- architecture end
--==============================================================================
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/sim/ 0000775 0000000 0000000 00000000000 12314554267 0022725 5 ustar 00root root 0000000 0000000 conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/sim/Release/ 0000775 0000000 0000000 00000000000 12314554267 0024305 5 ustar 00root root 0000000 0000000 conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/sim/Release/Makefile 0000664 0000000 0000000 00000132103 12314554267 0025745 0 ustar 00root root 0000000 0000000 ########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
## variables #############################
PWD := $(shell pwd)
MODELSIM_INI_PATH := /opt/modelsim_10.0d/modeltech
VCOM_FLAGS := -quiet -modelsimini modelsim.ini
VSIM_FLAGS :=
VLOG_FLAGS := -quiet -modelsimini modelsim.ini
VERILOG_SRC := ../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v \
VERILOG_OBJ := work/sockit_owm/.sockit_owm_v \
work/spi_clgen/.spi_clgen_v \
work/spi_shift/.spi_shift_v \
work/spi_top/.spi_top_v \
work/lm32_allprofiles/.lm32_allprofiles_v \
work/lm32_mc_arithmetic/.lm32_mc_arithmetic_v \
work/jtag_cores/.jtag_cores_v \
work/lm32_adder/.lm32_adder_v \
work/lm32_addsub/.lm32_addsub_v \
work/lm32_logic_op/.lm32_logic_op_v \
work/lm32_shifter/.lm32_shifter_v \
work/lm32_multiplier/.lm32_multiplier_v \
work/jtag_tap/.jtag_tap_v \
VHDL_SRC := i2c_bus_model.vhd \
testbench.vhd \
../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
../../modules/Release/conv_regs.vhd \
../../modules/Release/conv_pulse_gen.vhd \
../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
../../modules/Release/conv_ring_buf.vhd \
../../modules/Release/conv_pulse_timetag.vhd \
../../modules/reset_gen.vhd \
../../modules/rtm_detector.vhd \
../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
../../ip_cores/general-cores/modules/common/gc_moving_average.vhd \
../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd \
../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd \
../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd \
../../ip_cores/general-cores/modules/common/gc_reset.vhd \
../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd \
../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd \
../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd \
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd \
../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd \
../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd \
../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd \
../../ip_cores/general-cores/modules/common/gc_word_packer.vhd \
../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd \
../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd \
../../ip_cores/general-cores/modules/common/gc_big_adder.vhd \
../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd \
../../modules/Release/conv_man_trig.vhd \
../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd \
../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd \
../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd \
../../modules/bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd \
../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd \
../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/wb_xil_multiboot.vhd \
../../top/Release/conv_ttl_blo.vhd \
../../modules/bicolor_led_ctrl/bicolor_led_ctrl.vhd \
VHDL_OBJ := work/i2c_bus_model/.i2c_bus_model_vhd \
work/testbench/.testbench_vhd \
work/genram_pkg/.genram_pkg_vhd \
work/conv_regs/.conv_regs_vhd \
work/conv_pulse_gen/.conv_pulse_gen_vhd \
work/gencores_pkg/.gencores_pkg_vhd \
work/conv_ring_buf/.conv_ring_buf_vhd \
work/conv_pulse_timetag/.conv_pulse_timetag_vhd \
work/reset_gen/.reset_gen_vhd \
work/rtm_detector/.rtm_detector_vhd \
work/wishbone_pkg/.wishbone_pkg_vhd \
work/gc_crc_gen/.gc_crc_gen_vhd \
work/gc_moving_average/.gc_moving_average_vhd \
work/gc_extend_pulse/.gc_extend_pulse_vhd \
work/gc_delay_gen/.gc_delay_gen_vhd \
work/gc_dual_pi_controller/.gc_dual_pi_controller_vhd \
work/gc_reset/.gc_reset_vhd \
work/gc_serial_dac/.gc_serial_dac_vhd \
work/gc_sync_ffs/.gc_sync_ffs_vhd \
work/gc_arbitrated_mux/.gc_arbitrated_mux_vhd \
work/gc_pulse_synchronizer/.gc_pulse_synchronizer_vhd \
work/gc_pulse_synchronizer2/.gc_pulse_synchronizer2_vhd \
work/gc_frequency_meter/.gc_frequency_meter_vhd \
work/gc_rr_arbiter/.gc_rr_arbiter_vhd \
work/gc_prio_encoder/.gc_prio_encoder_vhd \
work/gc_word_packer/.gc_word_packer_vhd \
work/gc_i2c_slave/.gc_i2c_slave_vhd \
work/gc_glitch_filt/.gc_glitch_filt_vhd \
work/gc_big_adder/.gc_big_adder_vhd \
work/gc_fsm_watchdog/.gc_fsm_watchdog_vhd \
work/conv_man_trig/.conv_man_trig_vhd \
work/memory_loader_pkg/.memory_loader_pkg_vhd \
work/generic_shiftreg_fifo/.generic_shiftreg_fifo_vhd \
work/inferred_sync_fifo/.inferred_sync_fifo_vhd \
work/inferred_async_fifo/.inferred_async_fifo_vhd \
work/bicolor_led_ctrl_pkg/.bicolor_led_ctrl_pkg_vhd \
work/generic_dpram/.generic_dpram_vhd \
work/generic_dpram_sameclock/.generic_dpram_sameclock_vhd \
work/generic_dpram_dualclock/.generic_dpram_dualclock_vhd \
work/generic_simple_dpram/.generic_simple_dpram_vhd \
work/generic_spram/.generic_spram_vhd \
work/gc_shiftreg/.gc_shiftreg_vhd \
work/generic_async_fifo/.generic_async_fifo_vhd \
work/generic_sync_fifo/.generic_sync_fifo_vhd \
work/wb_async_bridge/.wb_async_bridge_vhd \
work/xwb_async_bridge/.xwb_async_bridge_vhd \
work/wb_onewire_master/.wb_onewire_master_vhd \
work/xwb_onewire_master/.xwb_onewire_master_vhd \
work/i2c_master_bit_ctrl/.i2c_master_bit_ctrl_vhd \
work/i2c_master_byte_ctrl/.i2c_master_byte_ctrl_vhd \
work/i2c_master_top/.i2c_master_top_vhd \
work/wb_i2c_master/.wb_i2c_master_vhd \
work/xwb_i2c_master/.xwb_i2c_master_vhd \
work/xwb_bus_fanout/.xwb_bus_fanout_vhd \
work/xwb_dpram/.xwb_dpram_vhd \
work/wb_gpio_port/.wb_gpio_port_vhd \
work/xwb_gpio_port/.xwb_gpio_port_vhd \
work/wb_tics/.wb_tics_vhd \
work/xwb_tics/.xwb_tics_vhd \
work/uart_async_rx/.uart_async_rx_vhd \
work/uart_async_tx/.uart_async_tx_vhd \
work/uart_baud_gen/.uart_baud_gen_vhd \
work/simple_uart_pkg/.simple_uart_pkg_vhd \
work/simple_uart_wb/.simple_uart_wb_vhd \
work/wb_simple_uart/.wb_simple_uart_vhd \
work/xwb_simple_uart/.xwb_simple_uart_vhd \
work/vic_prio_enc/.vic_prio_enc_vhd \
work/wbgen2_pkg/.wbgen2_pkg_vhd \
work/wb_vic/.wb_vic_vhd \
work/xwb_vic/.xwb_vic_vhd \
work/wb_spi/.wb_spi_vhd \
work/xwb_spi/.xwb_spi_vhd \
work/sdb_rom/.sdb_rom_vhd \
work/xwb_crossbar/.xwb_crossbar_vhd \
work/xwb_sdb_crossbar/.xwb_sdb_crossbar_vhd \
work/wb_irq_pkg/.wb_irq_pkg_vhd \
work/irqm_core/.irqm_core_vhd \
work/wb_irq_lm32/.wb_irq_lm32_vhd \
work/wb_irq_slave/.wb_irq_slave_vhd \
work/wb_irq_master/.wb_irq_master_vhd \
work/wb_irq_timer/.wb_irq_timer_vhd \
work/xwb_lm32/.xwb_lm32_vhd \
work/lm32_dp_ram/.lm32_dp_ram_vhd \
work/lm32_ram/.lm32_ram_vhd \
work/wb_slave_adapter/.wb_slave_adapter_vhd \
work/xwb_clock_crossing/.xwb_clock_crossing_vhd \
work/xwb_dma/.xwb_dma_vhd \
work/xwb_streamer/.xwb_streamer_vhd \
work/wb_serial_lcd/.wb_serial_lcd_vhd \
work/wb_spi_flash/.wb_spi_flash_vhd \
work/simple_pwm_wbgen2_pkg/.simple_pwm_wbgen2_pkg_vhd \
work/simple_pwm_wb/.simple_pwm_wb_vhd \
work/wb_simple_pwm/.wb_simple_pwm_vhd \
work/xwb_simple_pwm/.xwb_simple_pwm_vhd \
work/wb_i2c_bridge/.wb_i2c_bridge_vhd \
work/wbgen2_dpssram/.wbgen2_dpssram_vhd \
work/wbgen2_eic/.wbgen2_eic_vhd \
work/wbgen2_fifo_async/.wbgen2_fifo_async_vhd \
work/wbgen2_fifo_sync/.wbgen2_fifo_sync_vhd \
work/wb_slave_vic/.wb_slave_vic_vhd \
work/xloader_registers_pkg/.xloader_registers_pkg_vhd \
work/xwb_xilinx_fpga_loader/.xwb_xilinx_fpga_loader_vhd \
work/wb_xilinx_fpga_loader/.wb_xilinx_fpga_loader_vhd \
work/xloader_wb/.xloader_wb_vhd \
work/spi_master/.spi_master_vhd \
work/multiboot_fsm/.multiboot_fsm_vhd \
work/multiboot_regs/.multiboot_regs_vhd \
work/wb_xil_multiboot/.wb_xil_multiboot_vhd \
work/conv_ttl_blo/.conv_ttl_blo_vhd \
work/bicolor_led_ctrl/.bicolor_led_ctrl_vhd \
LIBS := work
LIB_IND := work/.work
## rules #################################
sim: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ): $(VHDL_OBJ)
$(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< .
clean:
rm -rf ./modelsim.ini $(LIBS)
.PHONY: clean
work/.work:
(vlib work && vmap -modelsimini modelsim.ini work && touch work/.work )|| rm -rf work
work/sockit_owm/.sockit_owm_v: ../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_onewire_master $<
@mkdir -p $(dir $@) && touch $@
work/spi_clgen/.spi_clgen_v: ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_spi $<
@mkdir -p $(dir $@) && touch $@
work/spi_shift/.spi_shift_v: ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_spi $<
@mkdir -p $(dir $@) && touch $@
work/spi_top/.spi_top_v: ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_spi $<
@mkdir -p $(dir $@) && touch $@
work/lm32_allprofiles/.lm32_allprofiles_v: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated $<
@mkdir -p $(dir $@) && touch $@
work/lm32_mc_arithmetic/.lm32_mc_arithmetic_v: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src $<
@mkdir -p $(dir $@) && touch $@
work/jtag_cores/.jtag_cores_v: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src $<
@mkdir -p $(dir $@) && touch $@
work/lm32_adder/.lm32_adder_v: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src $<
@mkdir -p $(dir $@) && touch $@
work/lm32_addsub/.lm32_addsub_v: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src $<
@mkdir -p $(dir $@) && touch $@
work/lm32_logic_op/.lm32_logic_op_v: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src $<
@mkdir -p $(dir $@) && touch $@
work/lm32_shifter/.lm32_shifter_v: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src $<
@mkdir -p $(dir $@) && touch $@
work/lm32_multiplier/.lm32_multiplier_v: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/../../src/lm32_include.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic $<
@mkdir -p $(dir $@) && touch $@
work/jtag_tap/.jtag_tap_v: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic $<
@mkdir -p $(dir $@) && touch $@
work/i2c_bus_model/.i2c_bus_model_vhd: i2c_bus_model.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/testbench/.testbench_vhd: testbench.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/genram_pkg/.genram_pkg_vhd: ../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/conv_regs/.conv_regs_vhd: ../../modules/Release/conv_regs.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/conv_pulse_gen/.conv_pulse_gen_vhd: ../../modules/Release/conv_pulse_gen.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gencores_pkg/.gencores_pkg_vhd: ../../ip_cores/general-cores/modules/common/gencores_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gencores_pkg/.gencores_pkg: \
work/genram_pkg/.genram_pkg
work/conv_ring_buf/.conv_ring_buf_vhd: ../../modules/Release/conv_ring_buf.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/conv_ring_buf/.conv_ring_buf: \
work/genram_pkg/.genram_pkg
work/conv_pulse_timetag/.conv_pulse_timetag_vhd: ../../modules/Release/conv_pulse_timetag.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/conv_pulse_timetag/.conv_pulse_timetag: \
work/gencores_pkg/.gencores_pkg
work/reset_gen/.reset_gen_vhd: ../../modules/reset_gen.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/rtm_detector/.rtm_detector_vhd: ../../modules/rtm_detector.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wishbone_pkg/.wishbone_pkg_vhd: ../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wishbone_pkg/.wishbone_pkg: \
work/genram_pkg/.genram_pkg
work/gc_crc_gen/.gc_crc_gen_vhd: ../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_crc_gen/.gc_crc_gen: \
work/gencores_pkg/.gencores_pkg
work/gc_moving_average/.gc_moving_average_vhd: ../../ip_cores/general-cores/modules/common/gc_moving_average.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_moving_average/.gc_moving_average: \
work/gencores_pkg/.gencores_pkg
work/gc_extend_pulse/.gc_extend_pulse_vhd: ../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_extend_pulse/.gc_extend_pulse: \
work/genram_pkg/.genram_pkg \
work/gencores_pkg/.gencores_pkg
work/gc_delay_gen/.gc_delay_gen_vhd: ../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_delay_gen/.gc_delay_gen: \
work/gencores_pkg/.gencores_pkg
work/gc_dual_pi_controller/.gc_dual_pi_controller_vhd: ../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_dual_pi_controller/.gc_dual_pi_controller: \
work/gencores_pkg/.gencores_pkg
work/gc_reset/.gc_reset_vhd: ../../ip_cores/general-cores/modules/common/gc_reset.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_serial_dac/.gc_serial_dac_vhd: ../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_sync_ffs/.gc_sync_ffs_vhd: ../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_arbitrated_mux/.gc_arbitrated_mux_vhd: ../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_arbitrated_mux/.gc_arbitrated_mux: \
work/genram_pkg/.genram_pkg \
work/gencores_pkg/.gencores_pkg
work/gc_pulse_synchronizer/.gc_pulse_synchronizer_vhd: ../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_pulse_synchronizer/.gc_pulse_synchronizer: \
work/gencores_pkg/.gencores_pkg
work/gc_pulse_synchronizer2/.gc_pulse_synchronizer2_vhd: ../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_pulse_synchronizer2/.gc_pulse_synchronizer2: \
work/gencores_pkg/.gencores_pkg
work/gc_frequency_meter/.gc_frequency_meter_vhd: ../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_frequency_meter/.gc_frequency_meter: \
work/gencores_pkg/.gencores_pkg
work/gc_rr_arbiter/.gc_rr_arbiter_vhd: ../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_prio_encoder/.gc_prio_encoder_vhd: ../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_word_packer/.gc_word_packer_vhd: ../../ip_cores/general-cores/modules/common/gc_word_packer.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_word_packer/.gc_word_packer: \
work/genram_pkg/.genram_pkg
work/gc_i2c_slave/.gc_i2c_slave_vhd: ../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_i2c_slave/.gc_i2c_slave: \
work/gencores_pkg/.gencores_pkg
work/gc_glitch_filt/.gc_glitch_filt_vhd: ../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_glitch_filt/.gc_glitch_filt: \
work/gencores_pkg/.gencores_pkg
work/gc_big_adder/.gc_big_adder_vhd: ../../ip_cores/general-cores/modules/common/gc_big_adder.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_big_adder/.gc_big_adder: \
work/wishbone_pkg/.wishbone_pkg \
work/gencores_pkg/.gencores_pkg
work/gc_fsm_watchdog/.gc_fsm_watchdog_vhd: ../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_fsm_watchdog/.gc_fsm_watchdog: \
work/genram_pkg/.genram_pkg
work/conv_man_trig/.conv_man_trig_vhd: ../../modules/Release/conv_man_trig.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/conv_man_trig/.conv_man_trig: \
work/genram_pkg/.genram_pkg
work/memory_loader_pkg/.memory_loader_pkg_vhd: ../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/memory_loader_pkg/.memory_loader_pkg: \
work/genram_pkg/.genram_pkg
work/generic_shiftreg_fifo/.generic_shiftreg_fifo_vhd: ../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/generic_shiftreg_fifo/.generic_shiftreg_fifo: \
work/genram_pkg/.genram_pkg
work/inferred_sync_fifo/.inferred_sync_fifo_vhd: ../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/inferred_sync_fifo/.inferred_sync_fifo: \
work/genram_pkg/.genram_pkg
work/inferred_async_fifo/.inferred_async_fifo_vhd: ../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/inferred_async_fifo/.inferred_async_fifo: \
work/genram_pkg/.genram_pkg
work/bicolor_led_ctrl_pkg/.bicolor_led_ctrl_pkg_vhd: ../../modules/bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/generic_dpram/.generic_dpram_vhd: ../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/generic_dpram/.generic_dpram: \
work/genram_pkg/.genram_pkg \
work/memory_loader_pkg/.memory_loader_pkg
work/generic_dpram_sameclock/.generic_dpram_sameclock_vhd: ../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/generic_dpram_sameclock/.generic_dpram_sameclock: \
work/genram_pkg/.genram_pkg \
work/memory_loader_pkg/.memory_loader_pkg
work/generic_dpram_dualclock/.generic_dpram_dualclock_vhd: ../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/generic_dpram_dualclock/.generic_dpram_dualclock: \
work/genram_pkg/.genram_pkg \
work/memory_loader_pkg/.memory_loader_pkg
work/generic_simple_dpram/.generic_simple_dpram_vhd: ../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/generic_simple_dpram/.generic_simple_dpram: \
work/genram_pkg/.genram_pkg \
work/memory_loader_pkg/.memory_loader_pkg
work/generic_spram/.generic_spram_vhd: ../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/generic_spram/.generic_spram: \
work/genram_pkg/.genram_pkg
work/gc_shiftreg/.gc_shiftreg_vhd: ../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_shiftreg/.gc_shiftreg: \
work/genram_pkg/.genram_pkg
work/generic_async_fifo/.generic_async_fifo_vhd: ../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/generic_async_fifo/.generic_async_fifo: \
work/genram_pkg/.genram_pkg
work/generic_sync_fifo/.generic_sync_fifo_vhd: ../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/generic_sync_fifo/.generic_sync_fifo: \
work/genram_pkg/.genram_pkg
work/wb_async_bridge/.wb_async_bridge_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_async_bridge/.wb_async_bridge: \
work/wishbone_pkg/.wishbone_pkg \
work/gencores_pkg/.gencores_pkg
work/xwb_async_bridge/.xwb_async_bridge_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_async_bridge/.xwb_async_bridge: \
work/wishbone_pkg/.wishbone_pkg
work/wb_onewire_master/.wb_onewire_master_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_onewire_master/.wb_onewire_master: \
work/wishbone_pkg/.wishbone_pkg \
work/gencores_pkg/.gencores_pkg
work/xwb_onewire_master/.xwb_onewire_master_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_onewire_master/.xwb_onewire_master: \
work/wishbone_pkg/.wishbone_pkg
work/i2c_master_bit_ctrl/.i2c_master_bit_ctrl_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/i2c_master_byte_ctrl/.i2c_master_byte_ctrl_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/i2c_master_top/.i2c_master_top_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_i2c_master/.wb_i2c_master_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_i2c_master/.wb_i2c_master: \
work/wishbone_pkg/.wishbone_pkg
work/xwb_i2c_master/.xwb_i2c_master_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_i2c_master/.xwb_i2c_master: \
work/wishbone_pkg/.wishbone_pkg
work/xwb_bus_fanout/.xwb_bus_fanout_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_bus_fanout/.xwb_bus_fanout: \
work/wishbone_pkg/.wishbone_pkg
work/xwb_dpram/.xwb_dpram_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_dpram/.xwb_dpram: \
work/wishbone_pkg/.wishbone_pkg \
work/genram_pkg/.genram_pkg
work/wb_gpio_port/.wb_gpio_port_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_gpio_port/.wb_gpio_port: \
work/wishbone_pkg/.wishbone_pkg \
work/gencores_pkg/.gencores_pkg
work/xwb_gpio_port/.xwb_gpio_port_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_gpio_port/.xwb_gpio_port: \
work/wishbone_pkg/.wishbone_pkg
work/wb_tics/.wb_tics_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_tics/.wb_tics: \
work/wishbone_pkg/.wishbone_pkg
work/xwb_tics/.xwb_tics_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_tics/.xwb_tics: \
work/wishbone_pkg/.wishbone_pkg
work/uart_async_rx/.uart_async_rx_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/uart_async_tx/.uart_async_tx_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/uart_baud_gen/.uart_baud_gen_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/simple_uart_pkg/.simple_uart_pkg_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/simple_uart_wb/.simple_uart_wb_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/simple_uart_wb/.simple_uart_wb: \
work/simple_uart_pkg/.simple_uart_pkg
work/wb_simple_uart/.wb_simple_uart_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_simple_uart/.wb_simple_uart: \
work/wishbone_pkg/.wishbone_pkg \
work/simple_uart_pkg/.simple_uart_pkg \
work/genram_pkg/.genram_pkg
work/xwb_simple_uart/.xwb_simple_uart_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_simple_uart/.xwb_simple_uart: \
work/wishbone_pkg/.wishbone_pkg
work/vic_prio_enc/.vic_prio_enc_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wbgen2_pkg/.wbgen2_pkg_vhd: ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_vic/.wb_vic_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_vic/.wb_vic: \
work/wishbone_pkg/.wishbone_pkg \
work/genram_pkg/.genram_pkg
work/xwb_vic/.xwb_vic_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_vic/.xwb_vic: \
work/wishbone_pkg/.wishbone_pkg
work/wb_spi/.wb_spi_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_spi/.wb_spi: \
work/wishbone_pkg/.wishbone_pkg
work/xwb_spi/.xwb_spi_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_spi/.xwb_spi: \
work/wishbone_pkg/.wishbone_pkg
work/sdb_rom/.sdb_rom_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/sdb_rom/.sdb_rom: \
work/wishbone_pkg/.wishbone_pkg
work/xwb_crossbar/.xwb_crossbar_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_crossbar/.xwb_crossbar: \
work/wishbone_pkg/.wishbone_pkg
work/xwb_sdb_crossbar/.xwb_sdb_crossbar_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_sdb_crossbar/.xwb_sdb_crossbar: \
work/wishbone_pkg/.wishbone_pkg
work/wb_irq_pkg/.wb_irq_pkg_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_irq_pkg/.wb_irq_pkg: \
work/wishbone_pkg/.wishbone_pkg
work/irqm_core/.irqm_core_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/irqm_core/.irqm_core: \
work/wishbone_pkg/.wishbone_pkg \
work/wb_irq_pkg/.wb_irq_pkg \
work/genram_pkg/.genram_pkg
work/wb_irq_lm32/.wb_irq_lm32_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_irq_lm32/.wb_irq_lm32: \
work/wishbone_pkg/.wishbone_pkg \
work/wb_irq_pkg/.wb_irq_pkg
work/wb_irq_slave/.wb_irq_slave_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_irq_slave/.wb_irq_slave: \
work/wishbone_pkg/.wishbone_pkg \
work/wb_irq_pkg/.wb_irq_pkg \
work/genram_pkg/.genram_pkg
work/wb_irq_master/.wb_irq_master_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_irq_master/.wb_irq_master: \
work/wishbone_pkg/.wishbone_pkg \
work/wb_irq_pkg/.wb_irq_pkg \
work/genram_pkg/.genram_pkg
work/wb_irq_timer/.wb_irq_timer_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_irq_timer/.wb_irq_timer: \
work/wishbone_pkg/.wishbone_pkg \
work/wb_irq_pkg/.wb_irq_pkg \
work/gencores_pkg/.gencores_pkg \
work/genram_pkg/.genram_pkg
work/xwb_lm32/.xwb_lm32_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_lm32/.xwb_lm32: \
work/wishbone_pkg/.wishbone_pkg
work/lm32_dp_ram/.lm32_dp_ram_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/lm32_dp_ram/.lm32_dp_ram: \
work/genram_pkg/.genram_pkg
work/lm32_ram/.lm32_ram_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/lm32_ram/.lm32_ram: \
work/genram_pkg/.genram_pkg
work/wb_slave_adapter/.wb_slave_adapter_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_slave_adapter/.wb_slave_adapter: \
work/wishbone_pkg/.wishbone_pkg
work/xwb_clock_crossing/.xwb_clock_crossing_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_clock_crossing/.xwb_clock_crossing: \
work/wishbone_pkg/.wishbone_pkg \
work/genram_pkg/.genram_pkg
work/xwb_dma/.xwb_dma_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_dma/.xwb_dma: \
work/wishbone_pkg/.wishbone_pkg \
work/genram_pkg/.genram_pkg
work/xwb_streamer/.xwb_streamer_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_streamer/.xwb_streamer: \
work/wishbone_pkg/.wishbone_pkg
work/wb_serial_lcd/.wb_serial_lcd_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_serial_lcd/.wb_serial_lcd: \
work/wishbone_pkg/.wishbone_pkg \
work/genram_pkg/.genram_pkg
work/wb_spi_flash/.wb_spi_flash_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_spi_flash/.wb_spi_flash: \
work/wishbone_pkg/.wishbone_pkg \
work/gencores_pkg/.gencores_pkg \
work/genram_pkg/.genram_pkg
work/simple_pwm_wbgen2_pkg/.simple_pwm_wbgen2_pkg_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/simple_pwm_wb/.simple_pwm_wb_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/simple_pwm_wb/.simple_pwm_wb: \
work/simple_pwm_wbgen2_pkg/.simple_pwm_wbgen2_pkg
work/wb_simple_pwm/.wb_simple_pwm_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_simple_pwm/.wb_simple_pwm: \
work/wishbone_pkg/.wishbone_pkg \
work/simple_pwm_wbgen2_pkg/.simple_pwm_wbgen2_pkg
work/xwb_simple_pwm/.xwb_simple_pwm_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_simple_pwm/.xwb_simple_pwm: \
work/wishbone_pkg/.wishbone_pkg
work/wb_i2c_bridge/.wb_i2c_bridge_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_i2c_bridge/.wb_i2c_bridge: \
work/gencores_pkg/.gencores_pkg
work/wbgen2_dpssram/.wbgen2_dpssram_vhd: ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wbgen2_dpssram/.wbgen2_dpssram: \
work/wbgen2_pkg/.wbgen2_pkg
work/wbgen2_eic/.wbgen2_eic_vhd: ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wbgen2_eic/.wbgen2_eic: \
work/wbgen2_pkg/.wbgen2_pkg
work/wbgen2_fifo_async/.wbgen2_fifo_async_vhd: ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wbgen2_fifo_async/.wbgen2_fifo_async: \
work/wbgen2_pkg/.wbgen2_pkg \
work/genram_pkg/.genram_pkg
work/wbgen2_fifo_sync/.wbgen2_fifo_sync_vhd: ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wbgen2_fifo_sync/.wbgen2_fifo_sync: \
work/wbgen2_pkg/.wbgen2_pkg
work/wb_slave_vic/.wb_slave_vic_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_slave_vic/.wb_slave_vic: \
work/wbgen2_pkg/.wbgen2_pkg
work/xloader_registers_pkg/.xloader_registers_pkg_vhd: ../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/xloader_registers_pkg/.xloader_registers_pkg: \
work/wbgen2_pkg/.wbgen2_pkg
work/xwb_xilinx_fpga_loader/.xwb_xilinx_fpga_loader_vhd: ../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_xilinx_fpga_loader/.xwb_xilinx_fpga_loader: \
work/wishbone_pkg/.wishbone_pkg
work/wb_xilinx_fpga_loader/.wb_xilinx_fpga_loader_vhd: ../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_xilinx_fpga_loader/.wb_xilinx_fpga_loader: \
work/wishbone_pkg/.wishbone_pkg \
work/xloader_registers_pkg/.xloader_registers_pkg \
work/gencores_pkg/.gencores_pkg
work/xloader_wb/.xloader_wb_vhd: ../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/xloader_wb/.xloader_wb: \
work/wbgen2_pkg/.wbgen2_pkg \
work/xloader_registers_pkg/.xloader_registers_pkg
work/spi_master/.spi_master_vhd: ../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/multiboot_fsm/.multiboot_fsm_vhd: ../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/multiboot_fsm/.multiboot_fsm: \
work/gencores_pkg/.gencores_pkg
work/multiboot_regs/.multiboot_regs_vhd: ../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_xil_multiboot/.wb_xil_multiboot_vhd: ../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/wb_xil_multiboot.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_xil_multiboot/.wb_xil_multiboot: \
work/wishbone_pkg/.wishbone_pkg
work/conv_ttl_blo/.conv_ttl_blo_vhd: ../../top/Release/conv_ttl_blo.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/conv_ttl_blo/.conv_ttl_blo: \
work/wishbone_pkg/.wishbone_pkg \
work/bicolor_led_ctrl_pkg/.bicolor_led_ctrl_pkg \
work/gencores_pkg/.gencores_pkg \
work/genram_pkg/.genram_pkg
work/bicolor_led_ctrl/.bicolor_led_ctrl_vhd: ../../modules/bicolor_led_ctrl/bicolor_led_ctrl.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/bicolor_led_ctrl/.bicolor_led_ctrl: \
work/bicolor_led_ctrl_pkg/.bicolor_led_ctrl_pkg
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/sim/Release/Manifest.py 0000664 0000000 0000000 00000000233 12314554267 0026423 0 ustar 00root root 0000000 0000000 target = "xilinx"
action = "simulation"
files = [
"i2c_bus_model.vhd",
"testbench.vhd"
]
modules = { "local" : "../../top/Release" }
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/sim/Release/i2c_bus_model.vhd 0000664 0000000 0000000 00000006277 12314554267 0027532 0 ustar 00root root 0000000 0000000 --==============================================================================
-- CERN (BE-CO-HT)
-- I2C bus model
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-11-27
--
-- version: 1.0
--
-- description:
-- A very simple I2C bus model for use in simulation, implementing the
-- wired-AND on the I2C protocol.
--
-- Masters and slaves should implement the buffers internally and connect the
-- SCL and SDA lines to the input ports of this model, as below:
-- - masters should connect to mscl_i and msda_i
-- - slaves should connect to sscl_i and ssda_i
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-11-27 Theodor Stana File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity i2c_bus_model is
generic
(
g_nr_masters : positive := 1;
g_nr_slaves : positive := 1
);
port
(
-- Input ports from master lines
mscl_i : in std_logic_vector(g_nr_masters-1 downto 0);
msda_i : in std_logic_vector(g_nr_masters-1 downto 0);
-- Input ports from slave lines
sscl_i : in std_logic_vector(g_nr_slaves-1 downto 0);
ssda_i : in std_logic_vector(g_nr_slaves-1 downto 0);
-- SCL and SDA line outputs
scl_o : out std_logic;
sda_o : out std_logic
);
end entity i2c_bus_model;
architecture behav of i2c_bus_model is
--==============================================================================
-- architecture begin
--==============================================================================
begin
scl_o <= '1' when (mscl_i = (mscl_i'range => '1')) and
(sscl_i = (sscl_i'range => '1')) else
'0';
sda_o <= '1' when (msda_i = (msda_i'range => '1')) and
(ssda_i = (ssda_i'range => '1')) else
'0';
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/sim/Release/run.do 0000664 0000000 0000000 00000000205 12314554267 0025432 0 ustar 00root root 0000000 0000000 vlib work
vsim -t 1ps -voptargs="+acc" -lib work work.testbench
radix -hexadecimal
#add wave *
do wave.do
run 10 ms
wave zoomfull
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/sim/Release/testbench.vhd 0000664 0000000 0000000 00000063101 12314554267 0026770 0 ustar 00root root 0000000 0000000 --==============================================================================
-- CERN (BE-CO-HT)
-- Testbench for CONV-TTL-BLO design
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2014-02-18
--
-- version: 1.0
--
-- description:
-- Design-wide simulation testbench for the CONV-TTL-BLO gateware. Currently
-- simulated features include:
-- - pulse triggering
-- - I2C master for reading register contents
--
-- dependencies:
-- None.
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2014-02-18 Theodor Stana File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity testbench is
end entity testbench;
architecture behav of testbench is
--============================================================================
-- Type declarations
--============================================================================
type t_state_i2c_mst is
(
IDLE,
I2C_ADDR, I2C_ADDR_ACK,
WB_ADDR_B0, WB_ADDR_B0_ACK,
WB_ADDR_B1, WB_ADDR_B1_ACK,
ST_OP,
RD_RESTART, RD_RESTART_ACK,
RD, RD_ACK,
WR, WR_ACK,
STO,
SUCCESS,
ERR
);
--============================================================================
-- Constant declarations
--============================================================================
-- Clock periods
constant c_clk_20_per : time := 50 ns;
constant c_clk_125_per : time := 8 ns;
-- Number of I2C masters and slaves for the I2C bus model
constant c_nr_masters : positive := 1;
constant c_nr_slaves : positive := 1;
--============================================================================
-- Component declarations
--============================================================================
component conv_ttl_blo is
generic
(
g_nr_ttl_chan : natural := 6;
g_nr_inv_chan : natural := 4;
g_sim : boolean := false
);
port
(
-- Clocks
-- 20 MHz from VCXO
clk_20_vcxo_i : in std_logic;
-- 125 MHz from clock generator
fpga_clk_p_i : in std_logic;
fpga_clk_n_i : in std_logic;
-- LEDs
led_ctrl0_o : out std_logic;
led_ctrl0_oen_o : out std_logic;
led_ctrl1_o : out std_logic;
led_ctrl1_oen_o : out std_logic;
led_multicast_2_0_o : out std_logic;
led_multicast_3_1_o : out std_logic;
led_wr_gmt_ttl_ttln_o : out std_logic;
led_wr_link_syserror_o : out std_logic;
led_wr_ok_syspw_o : out std_logic;
led_wr_ownaddr_i2c_o : out std_logic;
-- I/Os for pulses
pulse_front_led_n_o : out std_logic_vector(g_nr_ttl_chan downto 1);
pulse_rear_led_n_o : out std_logic_vector(g_nr_ttl_chan downto 1);
fpga_input_ttl_n_i : in std_logic_vector(g_nr_ttl_chan downto 1);
fpga_out_ttl_o : out std_logic_vector(g_nr_ttl_chan downto 1);
fpga_blo_in_i : in std_logic_vector(g_nr_ttl_chan downto 1);
fpga_trig_blo_o : out std_logic_vector(g_nr_ttl_chan downto 1);
inv_in_n_i : in std_logic_vector(g_nr_inv_chan downto 1);
inv_out_o : out std_logic_vector(g_nr_inv_chan downto 1);
-- Output enable lines
fpga_oe_o : out std_logic;
fpga_blo_oe_o : out std_logic;
fpga_trig_ttl_oe_o : out std_logic;
fpga_inv_oe_o : out std_logic;
--TTL/INV_TTL_N
ttl_switch_n_i : in std_logic;
extra_switch_n_i : in std_logic_vector(7 downto 1);
-- Lines for the i2c_slave
scl_i : in std_logic;
scl_o : out std_logic;
scl_oe_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
sda_oe_o : out std_logic;
fpga_ga_i : in std_logic_vector(4 downto 0);
fpga_gap_i : in std_logic;
-- Flash memory lines
fpga_prom_cclk_o : out std_logic;
fpga_prom_cso_b_n_o : out std_logic;
fpga_prom_mosi_o : out std_logic;
fpga_prom_miso_i : in std_logic;
-- Blocking power supply reset line
mr_n_o : out std_logic;
-- Thermometer line
thermometer_b : inout std_logic;
-- PLL DACs
-- DAC1: 20 MHz VCXO control
fpga_plldac1_din_o : out std_logic;
fpga_plldac1_sclk_o : out std_logic;
fpga_plldac1_sync_n_o : out std_logic;
-- DAC2: 125 MHz clock generator control
fpga_plldac2_din_o : out std_logic;
fpga_plldac2_sclk_o : out std_logic;
fpga_plldac2_sync_n_o : out std_logic;
-- SFP lines
fpga_sfp_los_i : in std_logic;
fpga_sfp_mod_def0_i : in std_logic;
fpga_sfp_rate_select_o : out std_logic;
fpga_sfp_mod_def1_b : inout std_logic;
fpga_sfp_mod_def2_b : inout std_logic;
fpga_sfp_tx_disable_o : out std_logic;
fpga_sfp_tx_fault_i : in std_logic;
-- RTM identifiers, should match with the expected values
fpga_rtmm_n_i : in std_logic_vector(2 downto 0);
fpga_rtmp_n_i : in std_logic_vector(2 downto 0)
);
end component conv_ttl_blo;
-- I2C bus model
component i2c_bus_model is
generic
(
g_nr_masters : positive := 1;
g_nr_slaves : positive := 1
);
port
(
-- Input ports from master lines
mscl_i : in std_logic_vector(g_nr_masters-1 downto 0);
msda_i : in std_logic_vector(g_nr_masters-1 downto 0);
-- Input ports from slave lines
sscl_i : in std_logic_vector(g_nr_slaves-1 downto 0);
ssda_i : in std_logic_vector(g_nr_slaves-1 downto 0);
-- SCL and SDA line outputs
scl_o : out std_logic;
sda_o : out std_logic
);
end component i2c_bus_model;
-- I2C master
component i2c_master_byte_ctrl is
port
(
clk : in std_logic;
rst : in std_logic; -- synchronous active high reset (WISHBONE compatible)
nReset : in std_logic; -- asynchornous active low reset (FPGA compatible)
ena : in std_logic; -- core enable signal
clk_cnt : in unsigned(15 downto 0); -- 4x SCL
-- input signals
start,
stop,
read,
write,
ack_in : std_logic;
din : in std_logic_vector(7 downto 0);
-- output signals
cmd_ack : out std_logic; -- command done
ack_out : out std_logic;
i2c_busy : out std_logic; -- arbitration lost
i2c_al : out std_logic; -- i2c bus busy
dout : out std_logic_vector(7 downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end component i2c_master_byte_ctrl;
--============================================================================
-- Signal declarations
--============================================================================
signal clk_20, clk_125 : std_logic;
signal clk_125_p, clk_125_n : std_logic;
signal rst_n, rst : std_logic;
signal pulse_led_front_n : std_logic_vector(6 downto 1);
signal pulse_led_front : std_logic_vector(6 downto 1);
signal pulse_led_rear_n : std_logic_vector(6 downto 1);
signal pulse_led_rear : std_logic_vector(6 downto 1);
signal ttl_inp_n, ttl_outp : std_logic_vector(6 downto 1);
signal ttl_pulse : std_logic_vector(6 downto 1);
signal inv_pulse : std_logic_vector(6 downto 1);
signal blo_inp, blo_outp : std_logic_vector(6 downto 1);
signal blo_pulse : std_logic_vector(6 downto 1);
signal oe, blo_oe, ttl_oe, inv_oe : std_logic;
signal ttl_switch_n : std_logic;
signal switches_n : std_logic_vector(7 downto 1);
-- I2C signals
signal state_i2c_mst : t_state_i2c_mst;
signal mst_fsm_op : std_logic;
signal mst_fsm_start : std_logic;
signal stim_cnt : unsigned(31 downto 0);
signal cnt : unsigned(2 downto 0);
signal buf_byte_cnt : integer;
signal once : boolean;
signal byte_cnt : unsigned(1 downto 0);
signal rcvd : std_logic_vector(31 downto 0);
signal send : std_logic_vector(31 downto 0);
signal send_val : std_logic_vector(31 downto 0);
signal wrote : std_logic;
signal slv_addr : std_logic_vector(6 downto 0);
signal adr : std_logic_vector(31 downto 0);
signal mst_sta : std_logic;
signal mst_sto : std_logic;
signal mst_rd : std_logic;
signal mst_wr : std_logic;
signal mst_ack : std_logic;
signal mst_dat_in : std_logic_vector(7 downto 0);
signal mst_dat_out : std_logic_vector(7 downto 0);
signal mst_cmd_ack : std_logic;
signal ack_fr_slv : std_logic;
signal mscl, msda : std_logic_vector(c_nr_masters-1 downto 0);
signal sscl, ssda : std_logic_vector(c_nr_slaves-1 downto 0);
signal scl, sda : std_logic;
signal scl_fr_mst : std_logic;
signal scl_en_mst : std_logic;
signal sda_fr_mst : std_logic;
signal sda_en_mst : std_logic;
signal scl_fr_slv : std_logic;
signal scl_en_slv : std_logic;
signal sda_fr_slv : std_logic;
signal sda_en_slv : std_logic;
signal t : boolean;
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Generate clock signals
--============================================================================
p_clk_20 : process
begin
clk_20 <= '0';
wait for c_clk_20_per/2;
clk_20 <= '1';
wait for c_clk_20_per/2;
end process;
p_clk_125 : process
begin
clk_125 <= '0';
wait for c_clk_125_per/2;
clk_125 <= '1';
wait for c_clk_125_per/2;
end process;
clk_125_p <= clk_125;
clk_125_n <= not clk_125;
--============================================================================
-- Instantiate the DUT
--============================================================================
cmp_dut : conv_ttl_blo
generic map
(
g_nr_ttl_chan => 6,
g_nr_inv_chan => 4,
g_sim => true
)
port map
(
-- Clocks
-- 20 MHz from VCXO
clk_20_vcxo_i => clk_20,
-- 125 MHz from clock generator
fpga_clk_p_i => clk_125_p,
fpga_clk_n_i => clk_125_n,
-- LEDs
led_ctrl0_o => open,
led_ctrl0_oen_o => open,
led_ctrl1_o => open,
led_ctrl1_oen_o => open,
led_multicast_2_0_o => open,
led_multicast_3_1_o => open,
led_wr_gmt_ttl_ttln_o => open,
led_wr_link_syserror_o => open,
led_wr_ok_syspw_o => open,
led_wr_ownaddr_i2c_o => open,
-- I/Os for pulses
pulse_front_led_n_o => pulse_led_front_n,
pulse_rear_led_n_o => pulse_led_rear_n,
fpga_input_ttl_n_i => ttl_inp_n,
fpga_out_ttl_o => ttl_outp,
fpga_blo_in_i => blo_inp,
fpga_trig_blo_o => blo_outp,
inv_in_n_i => (others => '1'),
inv_out_o => open,
-- Output enable lines
fpga_oe_o => oe,
fpga_blo_oe_o => blo_oe,
fpga_trig_ttl_oe_o => ttl_oe,
fpga_inv_oe_o => inv_oe,
--TTL/INV_TTL_N
ttl_switch_n_i => ttl_switch_n,
extra_switch_n_i => switches_n,
-- Lines for the i2c_slave
scl_i => scl,
scl_o => scl_fr_slv,
scl_oe_o => scl_en_slv,
sda_i => sda,
sda_o => sda_fr_slv,
sda_oe_o => sda_en_slv,
fpga_ga_i => "11110",
fpga_gap_i => '0',
-- Flash memory lines
fpga_prom_cclk_o => open,
fpga_prom_cso_b_n_o => open,
fpga_prom_mosi_o => open,
fpga_prom_miso_i => 'Z',
-- Blocking power supply reset line
mr_n_o => rst_n,
-- Thermometer line
thermometer_b => open,
-- PLL DACs
-- DAC1: 20 MHz VCXO control
fpga_plldac1_din_o => open,
fpga_plldac1_sclk_o => open,
fpga_plldac1_sync_n_o => open,
-- DAC2: 125 MHz clock generator control
fpga_plldac2_din_o => open,
fpga_plldac2_sclk_o => open,
fpga_plldac2_sync_n_o => open,
-- SFP lines
fpga_sfp_los_i => '1',
fpga_sfp_mod_def0_i => '1',
fpga_sfp_rate_select_o => open,
fpga_sfp_mod_def1_b => open,
fpga_sfp_mod_def2_b => open,
fpga_sfp_tx_disable_o => open,
fpga_sfp_tx_fault_i => '1',
-- RTM identifiers, should match with the expected values
fpga_rtmm_n_i => (others => '0'),
fpga_rtmp_n_i => (others => '0')
);
-- Tri-state buffers on the I2C lines
sscl(0) <= scl_fr_slv when (scl_en_slv = '1') else
'1';
ssda(0) <= sda_fr_slv when (sda_en_slv = '1') else
'1';
-- Active-high reset
rst <= not rst_n;
--============================================================================
-- Pulse outputs assignment based on OE signals
--============================================================================
ttl_pulse <= ttl_outp when oe = '1' and ttl_oe = '1' else (others => '0');
blo_pulse <= blo_outp when oe = '1' and blo_oe = '1' else (others => '0');
inv_pulse <= blo_outp when oe = '1' and inv_oe = '1' else (others => '0');
--============================================================================
-- Switches
--============================================================================
-- TTL
ttl_switch_n <= '0';
-- GF
switches_n(1) <= '0';
-- other
switches_n(7 downto 2) <= (others => '1');
--============================================================================
-- Pulse LEDs
--============================================================================
pulse_led_front <= not pulse_led_front_n;
pulse_led_rear <= not pulse_led_rear_n;
--============================================================================
-- Pulse stimuli
--============================================================================
blo_inp(6) <= '0';
ttl_inp_n(5 downto 1) <= (others => '1');
gen_pulse_chain : for i in 6 downto 2 generate
blo_inp(i-1) <= blo_outp(i);
end generate gen_pulse_chain;
p_stim_pulse : process
begin
ttl_inp_n(6) <= '1';
wait until t = true;
while (t = true) loop
wait for 5.561 us;
ttl_inp_n(6) <= '0';
wait for 500 ns;
ttl_inp_n(6) <= '1';
if ttl_outp(6) /= '1' then
assert false report "ttl_outp not '1'" severity warning;
end if;
if blo_outp(6) /= '1' then
assert false report "blo_outp not '1'" severity warning;
end if;
end loop;
end process p_stim_pulse;
process
begin
t <= true;
wait for 2 ms;
t <= false;
wait for 500 ms;
t <= true;
wait for 10 ms;
t <= false;
wait;
end process;
--============================================================================
-- I2C master
--============================================================================
------------------------------------------------------------------------------
-- First, the component instantiation
------------------------------------------------------------------------------
cmp_master : i2c_master_byte_ctrl
port map
(
clk => clk_20,
rst => rst,
nReset => rst_n,
ena => '1',
clk_cnt => x"0027",
-- input signals
start => mst_sta,
stop => mst_sto,
read => mst_rd,
write => mst_wr,
ack_in => mst_ack,
din => mst_dat_in,
-- output signals
cmd_ack => mst_cmd_ack,
ack_out => ack_fr_slv,
i2c_busy => open,
i2c_al => open,
dout => mst_dat_out,
-- i2c lines
scl_i => scl,
scl_o => scl_fr_mst,
scl_oen => scl_en_mst,
sda_i => sda,
sda_o => sda_fr_mst,
sda_oen => sda_en_mst
);
-- Then, the tri-state_i2c_mst buffers on the line
mscl(0) <= scl_fr_mst when (scl_en_mst = '0') else
'1';
msda(0) <= sda_fr_mst when (sda_en_mst = '0') else
'1';
------------------------------------------------------------------------------
-- Bus model instantiation and connection to master and slaves
------------------------------------------------------------------------------
cmp_i2c_bus : i2c_bus_model
generic map
(
g_nr_masters => c_nr_masters,
g_nr_slaves => c_nr_slaves
)
port map
(
mscl_i => mscl,
msda_i => msda,
sscl_i => sscl,
ssda_i => ssda,
scl_o => scl,
sda_o => sda
);
------------------------------------------------------------------------------
-- This FSM controls the signals to the master component to implement the I2C
-- protocol defined together with ELMA. The FSM is controlled by the
-- stimuli process below
------------------------------------------------------------------------------
p_mst_fsm : process (clk_20) is
begin
if rising_edge(clk_20) then
if (rst_n = '0') then
state_i2c_mst <= IDLE;
mst_sta <= '0';
mst_wr <= '0';
mst_sto <= '0';
mst_rd <= '0';
mst_dat_in <= (others => '0');
mst_ack <= '0';
cnt <= (others => '0');
once <= true;
byte_cnt <= (others => '0');
rcvd <= (others => '0');
send <= (others => '0');
else
case state_i2c_mst is
when IDLE =>
if (mst_fsm_start = '1') then
state_i2c_mst <= I2C_ADDR;
send <= std_logic_vector(send_val);
end if;
when I2C_ADDR =>
mst_sta <= '1';
mst_wr <= '1';
mst_dat_in <= slv_addr & '0';
if (mst_cmd_ack = '1') then
mst_sta <= '0';
mst_wr <= '0';
state_i2c_mst <= I2C_ADDR_ACK;
end if;
when I2C_ADDR_ACK =>
cnt <= cnt + 1;
if (cnt = 7) then
if (ack_fr_slv = '0') then
state_i2c_mst <= WB_ADDR_B0;
else
state_i2c_mst <= ERR;
end if;
end if;
when WB_ADDR_B0 =>
mst_wr <= '1';
mst_dat_in <= adr(15 downto 8);
if (mst_cmd_ack = '1') then
mst_wr <= '0';
state_i2c_mst <= WB_ADDR_B0_ACK;
end if;
when WB_ADDR_B0_ACK =>
cnt <= cnt + 1;
if (cnt = 7) then
if (ack_fr_slv = '0') then
state_i2c_mst <= WB_ADDR_B1;
else
state_i2c_mst <= ERR;
end if;
end if;
when WB_ADDR_B1 =>
mst_wr <= '1';
mst_dat_in <= adr(7 downto 0);
if (mst_cmd_ack = '1') then
mst_wr <= '0';
state_i2c_mst <= WB_ADDR_B1_ACK;
end if;
when WB_ADDR_B1_ACK =>
cnt <= cnt + 1;
if (cnt = 7) then
if (ack_fr_slv = '0') then
state_i2c_mst <= ST_OP;
else
state_i2c_mst <= ERR;
end if;
end if;
when ST_OP =>
if (mst_fsm_op = '1') then
state_i2c_mst <= RD_RESTART;
else
state_i2c_mst <= WR;
end if;
when RD_RESTART =>
mst_wr <= '1';
mst_dat_in <= slv_addr & '1';
mst_sta <= '1';
if (mst_cmd_ack = '1') then
mst_sta <= '0';
mst_wr <= '0';
state_i2c_mst <= RD_RESTART_ACK;
end if;
when RD_RESTART_ACK =>
cnt <= cnt + 1;
if (cnt = 7) then
if (ack_fr_slv = '0') then
state_i2c_mst <= RD;
else
state_i2c_mst <= ERR;
end if;
end if;
when RD =>
mst_rd <= '1';
mst_ack <= '0';
if (byte_cnt = 3) then
mst_ack <= '1';
end if;
if (mst_cmd_ack = '1') then
mst_rd <= '0';
byte_cnt <= byte_cnt + 1;
rcvd <= mst_dat_out & rcvd(31 downto 8);
mst_ack <= '0';
state_i2c_mst <= RD;
if (byte_cnt = 3) then
state_i2c_mst <= STO;
end if;
end if;
when RD_ACK =>
cnt <= cnt + 1;
if (cnt = 7) then
byte_cnt <= byte_cnt + 1;
rcvd <= mst_dat_out & rcvd(31 downto 8);
mst_ack <= '0';
state_i2c_mst <= RD;
if (byte_cnt = 3) then
state_i2c_mst <= STO;
end if;
end if;
when WR =>
mst_wr <= '1';
mst_dat_in <= send(7 downto 0);
if (mst_cmd_ack = '1') then
mst_wr <= '0';
state_i2c_mst <= WR_ACK;
end if;
when WR_ACK =>
cnt <= cnt + 1;
if (cnt = 7) then
if (ack_fr_slv = '0') then
byte_cnt <= byte_cnt + 1;
send <= x"00" & send(31 downto 8);
state_i2c_mst <= WR;
if (byte_cnt = 3) then
state_i2c_mst <= STO;
end if;
else
state_i2c_mst <= ERR;
end if;
end if;
when STO =>
mst_sto <= '1';
if (mst_cmd_ack = '1') then
mst_sto <= '0';
state_i2c_mst <= IDLE;
end if;
when ERR =>
if (once) then
report("Error!");
once <= false;
end if;
when others =>
state_i2c_mst <= ERR;
end case;
end if;
end if;
end process p_mst_fsm;
------------------------------------------------------------------------------
-- Process to "stimulate" the master FSM above
------------------------------------------------------------------------------
p_stim_mst_fsm : process (rst_n, t, state_i2c_mst)
begin
if (rst_n = '0') then
mst_fsm_start <= '0';
mst_fsm_op <= '0';
slv_addr <= "1011110";
adr <= (others => '0');
buf_byte_cnt <= 0;
elsif (not t) and (state_i2c_mst = IDLE) then
mst_fsm_start <= '1';
mst_fsm_op <= '1';
buf_byte_cnt <= buf_byte_cnt + 1;
case buf_byte_cnt is
when 0 =>
adr(11 downto 0) <= x"030";
when 1 =>
adr(11 downto 0) <= x"034";
when 2 =>
adr(11 downto 0) <= x"038";
when 3 =>
adr(11 downto 0) <= x"02c";
buf_byte_cnt <= 0;
when others =>
buf_byte_cnt <= 0;
end case;
else
mst_fsm_start <= '0';
end if;
end process p_stim_mst_fsm;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/sim/Release/wave.do 0000664 0000000 0000000 00000005307 12314554267 0025600 0 ustar 00root root 0000000 0000000 onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /testbench/clk_20
add wave -noupdate /testbench/clk_125
add wave -noupdate /testbench/rst_n
add wave -noupdate -divider Testbench
add wave -noupdate /testbench/ttl_inp_n
add wave -noupdate /testbench/ttl_outp
add wave -noupdate /testbench/ttl_pulse
add wave -noupdate /testbench/inv_pulse
add wave -noupdate /testbench/blo_inp
add wave -noupdate /testbench/blo_outp
add wave -noupdate /testbench/blo_pulse
add wave -noupdate /testbench/ttl_switch_n
add wave -noupdate /testbench/switches_n
add wave -noupdate -divider Internal
add wave -noupdate /testbench/cmp_dut/fpga_input_ttl_n_i
add wave -noupdate /testbench/cmp_dut/fpga_blo_in_i
add wave -noupdate /testbench/cmp_dut/trig_a
add wave -noupdate /testbench/cmp_dut/trig_ttl_a
add wave -noupdate -expand /testbench/cmp_dut/trig_blo_a
add wave -noupdate /testbench/cmp_dut/trig_chan
add wave -noupdate /testbench/cmp_dut/trig_man
add wave -noupdate -divider counters
add wave -noupdate -expand /testbench/cmp_dut/pulse_cnt
add wave -noupdate -divider i2c
add wave -noupdate /testbench/scl
add wave -noupdate /testbench/sda
add wave -noupdate /testbench/cmp_dut/cmp_conv_regs/wb_cyc_i
add wave -noupdate /testbench/cmp_dut/cmp_conv_regs/wb_stb_i
add wave -noupdate /testbench/cmp_dut/cmp_conv_regs/wb_we_i
add wave -noupdate /testbench/cmp_dut/cmp_conv_regs/reg_tb_rd_req_p_o
add wave -noupdate /testbench/cmp_dut/cmp_conv_regs/wb_adr_i
add wave -noupdate /testbench/cmp_dut/cmp_conv_regs/wb_dat_o
add wave -noupdate -divider fifo
add wave -noupdate /testbench/cmp_dut/cmp_ring_buf/buf_count
add wave -noupdate /testbench/cmp_dut/cmp_ring_buf/buf_wr_req_i
add wave -noupdate /testbench/cmp_dut/cmp_ring_buf/buf_empty
add wave -noupdate /testbench/cmp_dut/cmp_ring_buf/buf_full
add wave -noupdate /testbench/cmp_dut/cmp_ring_buf/buf_overflow
add wave -noupdate /testbench/cmp_dut/cmp_ring_buf/buf_read
add wave -noupdate /testbench/cmp_dut/cmp_ring_buf/buf_write
add wave -noupdate /testbench/cmp_dut/cmp_ring_buf/buf_rd_ptr
add wave -noupdate /testbench/cmp_dut/cmp_ring_buf/buf_wr_ptr
add wave -noupdate /testbench/cmp_dut/cmp_ring_buf/buf_rd_data
add wave -noupdate /testbench/cmp_dut/cmp_ring_buf/buf_wr_data
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {1225000 ps} 0}
configure wave -namecolwidth 397
configure wave -valuecolwidth 164
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ps} {10253908 ps}
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/sim/conv_man_trig/ 0000775 0000000 0000000 00000000000 12314554267 0025552 5 ustar 00root root 0000000 0000000 conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/sim/conv_man_trig/run.do 0000664 0000000 0000000 00000001161 12314554267 0026701 0 ustar 00root root 0000000 0000000 vlib work
vcom -explicit -93 "../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gencores_pkg.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd"
vcom -explicit -93 "../../modules/Release/conv_pulse_gen.vhd"
vcom -explicit -93 "../../modules/Release/conv_man_trig.vhd"
vcom -explicit -93 "testbench.vhd"
vsim -t 1ps -voptargs="+acc" -lib work work.testbench
radix -hexadecimal
# add wave *
do wave.do
run 300 us
wave zoomfull
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/sim/conv_man_trig/testbench.vhd 0000664 0000000 0000000 00000024055 12314554267 0030242 0 ustar 00root root 0000000 0000000 --==============================================================================
-- CERN (BE-CO-HT)
-- Testbench for the manual trigger module
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2014-01-30
--
-- version: 1.0
--
-- description:
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2014-01-30 Theodor Stana File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.genram_pkg.all;
entity testbench is
end entity testbench;
architecture behav of testbench is
--============================================================================
-- Constant declarations
--============================================================================
constant c_clk_per : time := 50 ns;
constant c_reset_width : time := 31 ns;
constant c_gf_len : positive := 1;
--============================================================================
-- Functions and procedures
--============================================================================
procedure f_mantrig
(
constant chan : in integer;
signal mpt : out std_logic_vector(7 downto 0);
signal mpt_wr : out std_logic
) is
begin
wait for 1 us;
mpt <= x"de";
mpt_wr <= '1';
wait for c_clk_per;
mpt_wr <= '0';
wait for 1 us;
mpt <= x"ad";
mpt_wr <= '1';
wait for c_clk_per;
mpt_wr <= '0';
wait for 1 us;
mpt <= x"be";
mpt_wr <= '1';
wait for c_clk_per;
mpt_wr <= '0';
wait for 1 us;
mpt <= x"ef";
mpt_wr <= '1';
wait for c_clk_per;
mpt_wr <= '0';
wait for 1 us;
mpt <= std_logic_vector(to_unsigned(chan, 8));
mpt_wr <= '1';
wait for c_clk_per;
mpt_wr <= '0';
wait for 1 us;
mpt_wr <= '1';
wait for c_clk_per;
mpt_wr <= '0';
end procedure;
--============================================================================
-- Component declarations
--============================================================================
-- DUT
component conv_man_trig is
generic
(
-- Number of conversion channels
g_nr_chan : positive := 6;
-- Glitch filter length, to generate a long enough pulse
g_gf_len : positive := 1
);
port
(
-- Clock, active-low inputs
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Control inputs from conv_regs
reg_ld_i : in std_logic;
reg_i : in std_logic_vector(7 downto 0);
-- One-clock pulse output
trig_o : out std_logic_vector(g_nr_chan downto 1)
);
end component conv_man_trig;
-- Pulse generator driven by DUT
component conv_pulse_gen is
generic
(
-- Pulse width, in number of clk_i cycles
-- Default pulse width (20 MHz clock): 1.2 us
-- Minimum allowable pulse width (20 MHz clock): 1 us
-- Maximum allowable pulse width (20 MHz clock): 2 us
g_pwidth : natural range 20 to 40 := 24;
-- Glitch filter length:
-- g_gf_len=1 => trigger width should be > 1 clk_i cycle
-- g_gf_len=2 => trigger width should be > 2 clk_i cycles
-- etc.
g_gf_len : natural := 1
);
port
(
-- Clock and active-low reset inputs
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Glitch filter enable input
-- '1' - Glitch filter disabled (glitch-sensitive, no output jitter)
-- '0' - Glitch filter enabled (glitch-insensitive, with output jitter)
gf_en_n_i : in std_logic;
-- Enable input, pulse generation is enabled when '1'
en_i : in std_logic;
-- Trigger input, has to be '1' to assure pulse output with delay no greater
-- than internal gate delays.
trig_a_i : in std_logic;
-- Pulse output, active-high
-- latency:
-- glitch filter disabled : none
-- glitch filter enabled : g_gf_len+6 clk_i cycles
pulse_o : out std_logic
);
end component conv_pulse_gen;
--============================================================================
-- Signal declarations
--============================================================================
signal clk20 : std_logic := '0';
signal rst_n : std_logic;
signal mpt_wr : std_logic;
signal mpt_wr_d0 : std_logic;
signal mpt_ld : std_logic;
signal mpt : std_logic_vector(7 downto 0);
signal trig_man : std_logic_vector(6 downto 1);
signal pulse : std_logic_vector(6 downto 1);
signal gf_n : std_logic;
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Generate clock and reset signals
--============================================================================
p_clk: process
begin
clk20 <= not clk20;
wait for c_clk_per/2;
end process p_clk;
p_rst_n: process
begin
rst_n <= '0';
wait for c_reset_width;
rst_n <= '1';
wait;
end process p_rst_n;
--============================================================================
-- Instantiate DUT and conv_pulse_gen blocks it drives
--============================================================================
-- First, the DUT
cmp_dut : conv_man_trig
generic map
(
g_nr_chan => 6,
g_gf_len => c_gf_len
)
port map
(
clk_i => clk20,
rst_n_i => rst_n,
reg_ld_i => mpt_ld,
reg_i => mpt,
trig_o => trig_man
);
-- Then, the pulse generators with a generate statement
gen_pulse_gens : for i in 1 to 6 generate
cmp_pulse_gen : conv_pulse_gen
generic map
(
g_pwidth => 24,
g_gf_len => c_gf_len
)
port map
(
clk_i => clk20,
rst_n_i => rst_n,
gf_en_n_i => gf_n,
en_i => '1',
trig_a_i => trig_man(i),
pulse_o => pulse(i)
);
end generate gen_pulse_gens;
--============================================================================
-- Some stimuli for the DUT
--============================================================================
p_mpt_ld : process (clk20)
begin
if rising_edge(clk20) then
if rst_n = '0' then
mpt_ld <= '0';
mpt_wr_d0 <= '0';
else
mpt_wr_d0 <= mpt_wr;
mpt_ld <= mpt_wr and not mpt_wr_d0;
end if;
end if;
end process;
p_stim : process
begin
mpt_wr <= '0';
mpt <= (others => '0');
--------------------------
-- No glitch filt
--------------------------
gf_n <= '1';
f_mantrig(6, mpt, mpt_wr);
wait for 1 us;
f_mantrig(6, mpt, mpt_wr);
wait for 1 us;
f_mantrig(5, mpt, mpt_wr);
wait for 1 us;
f_mantrig(5, mpt, mpt_wr);
wait for 1 us;
f_mantrig(4, mpt, mpt_wr);
wait for 1 us;
f_mantrig(4, mpt, mpt_wr);
wait for 1 us;
f_mantrig(3, mpt, mpt_wr);
wait for 1 us;
f_mantrig(3, mpt, mpt_wr);
wait for 1 us;
f_mantrig(2, mpt, mpt_wr);
wait for 1 us;
f_mantrig(2, mpt, mpt_wr);
wait for 1 us;
f_mantrig(1, mpt, mpt_wr);
wait for 1 us;
f_mantrig(1, mpt, mpt_wr);
wait for 1 us;
--------------------------
-- With glitch filt
--------------------------
gf_n <= '0';
f_mantrig(6, mpt, mpt_wr);
wait for 1 us;
f_mantrig(6, mpt, mpt_wr);
wait for 1 us;
f_mantrig(5, mpt, mpt_wr);
wait for 1 us;
f_mantrig(5, mpt, mpt_wr);
wait for 1 us;
f_mantrig(4, mpt, mpt_wr);
wait for 1 us;
gf_n <= '1';
f_mantrig(4, mpt, mpt_wr);
wait for 1 us;
f_mantrig(3, mpt, mpt_wr);
wait for 1 us;
f_mantrig(3, mpt, mpt_wr);
wait for 1 us;
f_mantrig(2, mpt, mpt_wr);
wait for 1 us;
f_mantrig(2, mpt, mpt_wr);
wait for 1 us;
f_mantrig(1, mpt, mpt_wr);
wait for 1 us;
f_mantrig(1, mpt, mpt_wr);
wait for 1 us;
--------------------------
-- No glitch filt
--------------------------
gf_n <= '1';
f_mantrig(6, mpt, mpt_wr);
wait for 1 us;
f_mantrig(6, mpt, mpt_wr);
wait for 1 us;
f_mantrig(5, mpt, mpt_wr);
wait for 1 us;
gf_n <= '0';
f_mantrig(5, mpt, mpt_wr);
wait for 1 us;
f_mantrig(4, mpt, mpt_wr);
wait for 1 us;
f_mantrig(4, mpt, mpt_wr);
wait for 1 us;
f_mantrig(3, mpt, mpt_wr);
wait for 1 us;
f_mantrig(3, mpt, mpt_wr);
wait for 1 us;
f_mantrig(2, mpt, mpt_wr);
wait for 1 us;
f_mantrig(2, mpt, mpt_wr);
wait for 1 us;
f_mantrig(1, mpt, mpt_wr);
wait for 1 us;
f_mantrig(1, mpt, mpt_wr);
wait for 1 us;
wait;
end process p_stim;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/sim/conv_man_trig/wave.do 0000664 0000000 0000000 00000004666 12314554267 0027054 0 ustar 00root root 0000000 0000000 onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /testbench/clk20
add wave -noupdate /testbench/rst_n
add wave -noupdate /testbench/mpt_ld
add wave -noupdate /testbench/mpt
add wave -noupdate /testbench/trig_man
add wave -noupdate -expand /testbench/pulse
add wave -noupdate -divider DUT
add wave -noupdate /testbench/cmp_dut/state
add wave -noupdate /testbench/cmp_dut/pass
add wave -noupdate /testbench/cmp_dut/chnr
add wave -noupdate /testbench/cmp_dut/cnt
add wave -noupdate /testbench/cmp_dut/trig_o
add wave -noupdate -divider {glitch filt}
add wave -noupdate /testbench/gen_pulse_gens(1)/cmp_pulse_gen/gf_en_n_i
add wave -noupdate /testbench/gen_pulse_gens(2)/cmp_pulse_gen/gf_en_n_i
add wave -noupdate /testbench/gen_pulse_gens(3)/cmp_pulse_gen/gf_en_n_i
add wave -noupdate /testbench/gen_pulse_gens(4)/cmp_pulse_gen/gf_en_n_i
add wave -noupdate /testbench/gen_pulse_gens(5)/cmp_pulse_gen/gf_en_n_i
add wave -noupdate /testbench/gen_pulse_gens(6)/cmp_pulse_gen/gf_en_n_i
add wave -noupdate -divider {pulse gen}
add wave -noupdate /testbench/gen_pulse_gens(1)/cmp_pulse_gen/pulse_gf_off
add wave -noupdate /testbench/gen_pulse_gens(1)/cmp_pulse_gen/pulse_gf_on
add wave -noupdate /testbench/gen_pulse_gens(2)/cmp_pulse_gen/pulse_gf_off
add wave -noupdate /testbench/gen_pulse_gens(2)/cmp_pulse_gen/pulse_gf_on
add wave -noupdate /testbench/gen_pulse_gens(3)/cmp_pulse_gen/pulse_gf_off
add wave -noupdate /testbench/gen_pulse_gens(3)/cmp_pulse_gen/pulse_gf_on
add wave -noupdate /testbench/gen_pulse_gens(4)/cmp_pulse_gen/pulse_gf_off
add wave -noupdate /testbench/gen_pulse_gens(4)/cmp_pulse_gen/pulse_gf_on
add wave -noupdate /testbench/gen_pulse_gens(5)/cmp_pulse_gen/pulse_gf_off
add wave -noupdate /testbench/gen_pulse_gens(5)/cmp_pulse_gen/pulse_gf_on
add wave -noupdate /testbench/gen_pulse_gens(6)/cmp_pulse_gen/pulse_gf_off
add wave -noupdate /testbench/gen_pulse_gens(6)/cmp_pulse_gen/pulse_gf_on
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {218986486 ps} 0} {{Cursor 2} {74966216 ps} 0}
configure wave -namecolwidth 383
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ps} {315 us}
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/sim/conv_pulse_gen/ 0000775 0000000 0000000 00000000000 12314554267 0025733 5 ustar 00root root 0000000 0000000 conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/sim/conv_pulse_gen/run.do 0000664 0000000 0000000 00000001256 12314554267 0027067 0 ustar 00root root 0000000 0000000 vlib work
vcom -explicit -93 "../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gencores_pkg.vhd"
vcom -explicit -93 "../../modules/pulsetest/pulse_gen_gp.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd"
vcom -explicit -93 "../../modules/Release/conv_pulse_gen.vhd"
vcom -explicit -93 "../../modules/Release/conv_man_trig.vhd"
vcom -explicit -93 "testbench.vhd"
vsim -t 1ps -voptargs="+acc" -lib work work.testbench
radix -hexadecimal
# add wave *
do wave.do
run 10 ms
wave zoomfull
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/sim/conv_pulse_gen/testbench.vhd 0000664 0000000 0000000 00000015345 12314554267 0030425 0 ustar 00root root 0000000 0000000 --==============================================================================
-- CERN (BE-CO-HT)
-- Testbench for old repeater design
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-02-28
--
-- version: 1.0
--
-- description:
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-02-28 Theodor Stana t.stana@cern.ch File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
entity testbench is
end entity testbench;
architecture behav of testbench is
--============================================================================
-- Constant declarations
--============================================================================
constant c_clk_per : time := 50 ns;
constant c_reset_width : time := 31 ns;
--============================================================================
-- Component declarations
--============================================================================
component conv_pulse_gen is
generic
(
-- Pulse width, in number of clk_i cycles
-- Default pulse width (20 MHz clock): 1.2 us
-- Minimum allowable pulse width (20 MHz clock): 1 us
-- Maximum allowable pulse width (20 MHz clock): 2 us
g_pwidth : natural range 20 to 40 := 24;
-- Duty cycle divider: D = 1/g_duty_cycle_div
g_duty_cycle_div : natural := 5
);
port
(
-- Clock and active-low reset inputs
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Glitch filter enable input
-- '1' - Glitch filter disabled (glitch-sensitive, no output jitter)
-- '0' - Glitch filter enabled (glitch-insensitive, with output jitter)
gf_en_n_i : in std_logic;
-- Enable input, pulse generation is enabled when '1'
en_i : in std_logic;
-- Trigger input, has to be '1' to assure pulse output with delay no greater
-- than internal gate delays.
trig_a_i : in std_logic;
-- Pulse output, active-high
-- latency:
-- glitch filter disabled: none
-- glitch filter enabled: glitch filter length + 5 clk_i cycles
pulse_o : out std_logic
);
end component conv_pulse_gen;
component pulse_gen_gp is
port
(
-- Input clock and active-low reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Active high enable signal
en_i : in std_logic;
-- Delay, pulse width and frequency inputs, in number of clk_i cycles
delay_i : in std_logic_vector(31 downto 0);
pwidth_i : in std_logic_vector(31 downto 0);
freq_i : in std_logic_vector(31 downto 0);
-- Output pulse signal
pulse_o : out std_logic
);
end component pulse_gen_gp;
--============================================================================
-- Signal declarations
--============================================================================
signal clk, clk4, rst_n, pulse, trig, lvl, lvl_n : std_logic := '0';
signal trig_degl : std_logic;
signal trig_chan : std_logic;
signal trig_man : std_logic;
signal actual_trig : std_logic := '0';
signal actual_pulse : std_logic := '0';
signal gf_en : std_logic;
signal gf_en_n : std_logic;
signal pgen_en : std_logic;
--==============================================================================
-- architecture begin
--==============================================================================
begin
-- DUT INSTANTIATION
DUT: conv_pulse_gen
generic map
(
g_pwidth => 24,
g_duty_cycle_div => 500
)
port map
(
clk_i => clk,
rst_n_i => rst_n,
gf_en_n_i => gf_en_n,
en_i => '1',
trig_a_i => actual_trig,
pulse_o => pulse
);
-- CLOCK GENERATION
p_clk: process
begin
clk <= not clk;
wait for c_clk_per/2;
end process p_clk;
-- SECOND CLOCK GENERATION
p_clk4: process
begin
clk4 <= not clk4;
wait for 2 ns;
end process p_clk4;
-- RESET GENERATION
p_rst_n: process
begin
rst_n <= '0';
wait for c_reset_width;
rst_n <= '1';
wait;
end process p_rst_n;
-- PULSE GENERATOR FOR TRIGGER
cmp_pulse_gen : pulse_gen_gp
port map
(
clk_i => clk4,
rst_n_i => rst_n,
en_i => pgen_en,
delay_i => (others => '0'),
pwidth_i => x"0000012c",
freq_i => x"000249f0",
pulse_o => trig
);
-- Glitch filter instantiation
cmp_gf : gc_glitch_filt
generic map
(
g_len => 1
)
port map
(
clk_i => clk,
rst_n_i => rst_n,
dat_i => trig,
dat_o => trig_degl
);
-- Trigger signal
trig_chan <= trig when gf_en_n = '1' else
trig_degl;
actual_trig <= trig_chan or trig_man;
-- Glitch filter enable
gf_en_n <= '0';
-- manual trigger stimuli
p_man_trig : process
begin
trig_man <= '0';
pgen_en <= '0';
wait for 10 us;
trig_man <= '1';
wait for c_clk_per;
trig_man <= '0';
wait for 10 us;
trig_man <= '1';
wait for c_clk_per;
trig_man <= '0';
wait for 10 us;
pgen_en <= '1';
-- wait for 30 us;
-- pgen_en <= '0';
-- wait for 10 us;
-- trig_man <= '1';
-- wait for c_clk_per;
-- trig_man <= '0';
-- wait for 10 us;
-- pgen_en <= '1';
wait;
end process;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/sim/conv_pulse_gen/wave.do 0000664 0000000 0000000 00000002307 12314554267 0027223 0 ustar 00root root 0000000 0000000 onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /testbench/clk
add wave -noupdate /testbench/pulse
add wave -noupdate /testbench/trig
add wave -noupdate /testbench/trig_man
add wave -noupdate /testbench/actual_trig
add wave -noupdate /testbench/actual_pulse
add wave -noupdate /testbench/gf_en_n
add wave -noupdate -divider ctb_pulse_gen
add wave -noupdate /testbench/DUT/pulse_o
add wave -noupdate /testbench/DUT/trig_a_i
add wave -noupdate /testbench/DUT/state
add wave -noupdate /testbench/DUT/pulse_cnt
add wave -noupdate /testbench/DUT/pulse_gf_on
add wave -noupdate /testbench/DUT/pulse_gf_off
add wave -noupdate /testbench/DUT/pulse_gf_off_rst
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {2711183 ps} 0} {{Cursor 2} {23915869 ps} 0}
configure wave -namecolwidth 253
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ps} {105 us}
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/sim/pulse_timetag/ 0000775 0000000 0000000 00000000000 12314554267 0025567 5 ustar 00root root 0000000 0000000 conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/sim/pulse_timetag/run.do 0000664 0000000 0000000 00000000736 12314554267 0026725 0 ustar 00root root 0000000 0000000 vlib work
vcom -explicit -93 "../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gencores_pkg.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd"
vcom -explicit -93 "../../modules/Release/pulse_timetag.vhd"
vcom -explicit -93 "testbench.vhd"
vsim -t 1ps -voptargs="+acc" -lib work work.testbench
radix -hexadecimal
add wave *
#do wave.do
run 100 us
wave zoomfull
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/sim/pulse_timetag/testbench.vhd 0000664 0000000 0000000 00000016115 12314554267 0030255 0 ustar 00root root 0000000 0000000 --==============================================================================
-- CERN (BE-CO-HT)
-- Testbench for pulse time-tagging core
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2014-02-06
--
-- version: 1.0
--
-- description:
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2014-02-06 Theodor Stana File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
entity testbench is
end entity testbench;
architecture behav of testbench is
--============================================================================
-- Type declarations
--============================================================================
--============================================================================
-- Constant declarations
--============================================================================
constant c_clk_20_per : time := 50 ns;
constant c_clk_125_per : time := 8 ns;
constant c_reset_width : time := 31 ns;
--============================================================================
-- Component declarations
--============================================================================
-- DUT component
component pulse_timetag is
generic
(
-- Frequency in Hz of the clk_i signal
g_clk_rate : positive := 125000000;
-- Number of repetition channels
g_nr_chan : positive := 6
);
port
(
-- Clock and active-low reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Asynchronous pulse input
pulse_a_i : in std_logic_vector(g_nr_chan-1 downto 0);
-- Time inputs from White Rabbit
wr_tm_cycles_i : in std_logic_vector(27 downto 0);
wr_tm_tai_i : in std_logic_vector(39 downto 0);
wr_tm_valid_i : in std_logic;
-- Timing inputs from Wishbone-mapped registers
wb_tm_tai_l_i : in std_logic_vector(31 downto 0);
wb_tm_tai_l_ld_i : in std_logic;
wb_tm_tai_h_i : in std_logic_vector( 7 downto 0);
wb_tm_tai_h_ld_i : in std_logic;
-- Timing outputs
tm_cycles_o : out std_logic_vector(27 downto 0);
tm_tai_o : out std_logic_vector(39 downto 0)
);
end component pulse_timetag;
--============================================================================
-- Signal declarations
--============================================================================
-- Clock, reset signals
signal clk_20, clk_125 : std_logic;
signal rst_20_n, rst_125_n : std_logic;
-- Register signals to/from "Wishbone"
signal tvlr_ld, tvhr_ld : std_logic;
signal ldh, ldl : std_logic;
signal tvlr, l : std_logic_vector(31 downto 0);
signal tvhr, h : std_logic_vector(7 downto 0);
-- Cycles, TAI and tick to "Wishbone"
signal tm_cycles : std_logic_vector(27 downto 0);
signal tm_tai : std_logic_vector(39 downto 0);
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- DUT instantiation
--============================================================================
cmp_dut : pulse_timetag
generic map
(
g_clk_rate => 125000000,
g_nr_chan => 6
)
port map
(
clk_i => clk_125,
rst_n_i => rst_125_n,
pulse_a_i => (others => '0'),
wr_tm_cycles_i => (others => '0'),
wr_tm_tai_i => (others => '0'),
wr_tm_valid_i => '0',
wb_tm_tai_l_i => tvlr,
wb_tm_tai_l_ld_i => tvlr_ld,
wb_tm_tai_h_i => tvhr,
wb_tm_tai_h_ld_i => tvhr_ld,
tm_cycles_o => tm_cycles,
tm_tai_o => tm_tai
);
--============================================================================
-- Clock and reset generation
--============================================================================
p_clk_20 : process
begin
clk_20 <= '0';
wait for c_clk_20_per/2;
clk_20 <= '1';
wait for c_clk_20_per/2;
end process p_clk_20;
p_clk_125 : process
begin
clk_125 <= '0';
wait for c_clk_125_per/2;
clk_125 <= '1';
wait for c_clk_125_per/2;
end process p_clk_125;
p_rst_20_n : process
begin
rst_20_n <= '0';
wait for c_reset_width;
wait for c_clk_20_per;
rst_20_n <= '1';
wait;
end process p_rst_20_n;
cmp_sync_rst : gc_sync_ffs
port map
(
clk_i => clk_125,
rst_n_i => '1',
data_i => rst_20_n,
synced_o => rst_125_n
);
--============================================================================
-- Stimuli
--============================================================================
-- Stimuli process
p_stim : process
begin
l <= (others => '0');
h <= (others => '0');
ldh <= '0';
ldl <= '0';
wait for 1 us;
l <= x"0000f000";
ldl <= '1';
wait for c_clk_20_per;
ldl <= '0';
wait for 1 us;
h <= x"01";
ldh <= '1';
wait for c_clk_20_per;
ldh <= '0';
wait;
end process p_stim;
-- Set the TVR on clock boundaries
p_tvr : process (clk_20)
begin
if rising_edge(clk_20) then
if rst_20_n = '0' then
tvlr <= (others => '0');
tvhr <= (others => '0');
tvlr_ld <= '0';
tvhr_ld <= '0';
elsif ldl = '1' then
tvlr <= l;
tvlr_ld <= '1';
elsif ldh = '1' then
tvhr <= h;
tvhr_ld <= '1';
else
tvlr_ld <= '0';
tvhr_ld <= '0';
end if;
end if;
end process p_tvr;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/syn/ 0000775 0000000 0000000 00000000000 12314554267 0022746 5 ustar 00root root 0000000 0000000 conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/syn/Release/ 0000775 0000000 0000000 00000000000 12314554267 0024326 5 ustar 00root root 0000000 0000000 conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/syn/Release/Makefile 0000664 0000000 0000000 00000002564 12314554267 0025775 0 ustar 00root root 0000000 0000000 ########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
PROJECT := conv_ttl_blo.xise
ISE_CRAP := *.b conv_ttl_blo_summary.html *.tcl conv_ttl_blo.bld conv_ttl_blo.cmd_log *.drc conv_ttl_blo.lso *.ncd conv_ttl_blo.ngc conv_ttl_blo.ngd conv_ttl_blo.ngr conv_ttl_blo.pad conv_ttl_blo.par conv_ttl_blo.pcf conv_ttl_blo.prj conv_ttl_blo.ptwx conv_ttl_blo.stx conv_ttl_blo.syr conv_ttl_blo.twr conv_ttl_blo.twx conv_ttl_blo.gise conv_ttl_blo.unroutes conv_ttl_blo.ut conv_ttl_blo.xpi conv_ttl_blo.xst conv_ttl_blo_bitgen.xwbt conv_ttl_blo_envsettings.html conv_ttl_blo_guide.ncd conv_ttl_blo_map.map conv_ttl_blo_map.mrp conv_ttl_blo_map.ncd conv_ttl_blo_map.ngm conv_ttl_blo_map.xrpt conv_ttl_blo_ngdbuild.xrpt conv_ttl_blo_pad.csv conv_ttl_blo_pad.txt conv_ttl_blo_par.xrpt conv_ttl_blo_summary.xml conv_ttl_blo_usage.xml conv_ttl_blo_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl
#target for performing local synthesis
local:
echo "project open $(PROJECT)" > run.tcl
echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
xtclsh run.tcl
#target for cleaing all intermediate stuff
clean:
rm -f $(ISE_CRAP)
rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
#target for cleaning final files
mrproper:
rm -f *.bit *.bin *.mcs
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/syn/Release/Manifest.py 0000664 0000000 0000000 00000000361 12314554267 0026446 0 ustar 00root root 0000000 0000000 target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "conv_ttl_blo"
syn_project = "conv_ttl_blo.xise"
modules = {
"local" : [
"../../top/Release"
]
}
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/syn/Release/conv_ttl_blo.xise 0000664 0000000 0000000 00000165230 12314554267 0027713 0 ustar 00root root 0000000 0000000
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/syn/pulsetest/ 0000775 0000000 0000000 00000000000 12314554267 0024776 5 ustar 00root root 0000000 0000000 conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/syn/pulsetest/Makefile 0000664 0000000 0000000 00000026203 12314554267 0026441 0 ustar 00root root 0000000 0000000 ########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
PROJECT := pulsetest.xise
ISE_CRAP := *.b pulsetest_summary.html *.tcl pulsetest.bld pulsetest.cmd_log *.drc pulsetest.lso *.ncd pulsetest.ngc pulsetest.ngd pulsetest.ngr pulsetest.pad pulsetest.par pulsetest.pcf pulsetest.prj pulsetest.ptwx pulsetest.stx pulsetest.syr pulsetest.twr pulsetest.twx pulsetest.gise pulsetest.unroutes pulsetest.ut pulsetest.xpi pulsetest.xst pulsetest_bitgen.xwbt pulsetest_envsettings.html pulsetest_guide.ncd pulsetest_map.map pulsetest_map.mrp pulsetest_map.ncd pulsetest_map.ngm pulsetest_map.xrpt pulsetest_ngdbuild.xrpt pulsetest_pad.csv pulsetest_pad.txt pulsetest_par.xrpt pulsetest_summary.xml pulsetest_usage.xml pulsetest_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl
#target for performing local synthesis
local:
echo "project open $(PROJECT)" > run.tcl
echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
xtclsh run.tcl
#target for cleaing all intermediate stuff
clean:
rm -f $(ISE_CRAP)
rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
#target for cleaning final files
mrproper:
rm -f *.bit *.bin *.mcs
USER:=$(HDLMAKE_USER)#take the value from the environment
SERVER:=$(HDLMAKE_SERVER)#take the value from the environment
R_NAME:=pulsetest
__test_for_remote_synthesis_variables:
ifeq (x$(USER),x)
@echo "Remote synthesis user is not set. You can set it by editing variable USER in the makefile." && false
endif
ifeq (x$(SERVER),x)
@echo "Remote synthesis server is not set. You can set it by editing variable SERVER in the makefile." && false
endif
CWD := $(shell pwd)
FILES := ../../top/pulsetest/pulsetest.ucf \
../../top/pulsetest/pulsetest.vhd \
../../modules/pulsetest/conv_regs.vhd \
../../modules/pulsetest/pulse_cnt_regs.vhd \
../../modules/pulsetest/pgen_ctrl_regs.vhd \
../../modules/pulsetest/pulse_gen_gp.vhd \
../../modules/reset_gen.vhd \
../../modules/rtm_detector.vhd \
../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
../../ip_cores/general-cores/modules/common/gc_moving_average.vhd \
../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd \
../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd \
../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd \
../../ip_cores/general-cores/modules/common/gc_reset.vhd \
../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd \
../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd \
../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd \
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd \
../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd \
../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd \
../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd \
../../ip_cores/general-cores/modules/common/gc_word_packer.vhd \
../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd \
../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd \
../../ip_cores/general-cores/modules/common/gc_big_adder.vhd \
../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd \
../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd \
../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd \
../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd \
../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd \
../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd \
../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v \
../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/wb_xil_multiboot.vhd \
../../modules/bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd \
../../modules/bicolor_led_ctrl/bicolor_led_ctrl.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v \
run.tcl \
pulsetest.xise
#target for running simulation in the remote location
remote: __test_for_remote_synthesis_variables __send __do_synthesis __send_back
__send_back: __do_synthesis
__do_synthesis: __send
__send: __test_for_remote_synthesis_variables
__send:
ssh $(USER)@$(SERVER) 'mkdir -p $(R_NAME)'
rsync -Rav $(foreach file, $(FILES), $(shell readlink -f $(file))) $(USER)@$(SERVER):$(R_NAME)
__do_synthesis:
ssh $(USER)@$(SERVER) 'cd $(R_NAME)$(CWD) && xtclsh run.tcl'
__send_back:
cd .. && rsync -av $(USER)@$(SERVER):$(R_NAME)$(CWD) . && cd $(CWD)
#target for removing stuff from the remote location
cleanremote:
ssh $(USER)@$(SERVER) 'rm -rf $(R_NAME)'
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/syn/pulsetest/Manifest.py 0000664 0000000 0000000 00000000356 12314554267 0027122 0 ustar 00root root 0000000 0000000 target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "pulsetest"
syn_project = "pulsetest.xise"
modules = {
"local" : [
"../../top/pulsetest"
]
}
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/syn/pulsetest/pulsetest.xise 0000664 0000000 0000000 00000164731 12314554267 0027734 0 ustar 00root root 0000000 0000000
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/syn/regtest/ 0000775 0000000 0000000 00000000000 12314554267 0024423 5 ustar 00root root 0000000 0000000 conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/syn/regtest/Makefile 0000664 0000000 0000000 00000025600 12314554267 0026066 0 ustar 00root root 0000000 0000000 ########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
PROJECT := regtest.xise
ISE_CRAP := *.b regtest_summary.html *.tcl regtest.bld regtest.cmd_log *.drc regtest.lso *.ncd regtest.ngc regtest.ngd regtest.ngr regtest.pad regtest.par regtest.pcf regtest.prj regtest.ptwx regtest.stx regtest.syr regtest.twr regtest.twx regtest.gise regtest.unroutes regtest.ut regtest.xpi regtest.xst regtest_bitgen.xwbt regtest_envsettings.html regtest_guide.ncd regtest_map.map regtest_map.mrp regtest_map.ncd regtest_map.ngm regtest_map.xrpt regtest_ngdbuild.xrpt regtest_pad.csv regtest_pad.txt regtest_par.xrpt regtest_summary.xml regtest_usage.xml regtest_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl
#target for performing local synthesis
local:
echo "project open $(PROJECT)" > run.tcl
echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
xtclsh run.tcl
#target for cleaing all intermediate stuff
clean:
rm -f $(ISE_CRAP)
rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
#target for cleaning final files
mrproper:
rm -f *.bit *.bin *.mcs
USER:=$(HDLMAKE_USER)#take the value from the environment
SERVER:=$(HDLMAKE_SERVER)#take the value from the environment
R_NAME:=regtest
__test_for_remote_synthesis_variables:
ifeq (x$(USER),x)
@echo "Remote synthesis user is not set. You can set it by editing variable USER in the makefile." && false
endif
ifeq (x$(SERVER),x)
@echo "Remote synthesis server is not set. You can set it by editing variable SERVER in the makefile." && false
endif
CWD := $(shell pwd)
FILES := ../../top/regtest/regtest.ucf \
../../top/regtest/regtest.vhd \
../../modules/reset_gen.vhd \
../../modules/rtm_detector.vhd \
../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
../../ip_cores/general-cores/modules/common/gc_moving_average.vhd \
../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd \
../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd \
../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd \
../../ip_cores/general-cores/modules/common/gc_reset.vhd \
../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd \
../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd \
../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd \
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd \
../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd \
../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd \
../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd \
../../ip_cores/general-cores/modules/common/gc_word_packer.vhd \
../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd \
../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd \
../../ip_cores/general-cores/modules/common/gc_big_adder.vhd \
../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd \
../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd \
../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd \
../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd \
../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd \
../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd \
../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v \
../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/wb_xil_multiboot.vhd \
../../modules/bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd \
../../modules/bicolor_led_ctrl/bicolor_led_ctrl.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v \
run.tcl \
regtest.xise
#target for running simulation in the remote location
remote: __test_for_remote_synthesis_variables __send __do_synthesis __send_back
__send_back: __do_synthesis
__do_synthesis: __send
__send: __test_for_remote_synthesis_variables
__send:
ssh $(USER)@$(SERVER) 'mkdir -p $(R_NAME)'
rsync -Rav $(foreach file, $(FILES), $(shell readlink -f $(file))) $(USER)@$(SERVER):$(R_NAME)
__do_synthesis:
ssh $(USER)@$(SERVER) 'cd $(R_NAME)$(CWD) && xtclsh run.tcl'
__send_back:
cd .. && rsync -av $(USER)@$(SERVER):$(R_NAME)$(CWD) . && cd $(CWD)
#target for removing stuff from the remote location
cleanremote:
ssh $(USER)@$(SERVER) 'rm -rf $(R_NAME)'
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/syn/regtest/Manifest.py 0000664 0000000 0000000 00000000350 12314554267 0026541 0 ustar 00root root 0000000 0000000 target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "regtest"
syn_project = "regtest.xise"
modules = {
"local" : [
"../../top/regtest"
]
}
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/syn/regtest/regtest.xise 0000664 0000000 0000000 00000163176 12314554267 0027010 0 ustar 00root root 0000000 0000000
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/top/ 0000775 0000000 0000000 00000000000 12314554267 0022737 5 ustar 00root root 0000000 0000000 conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/top/Release/ 0000775 0000000 0000000 00000000000 12314554267 0024317 5 ustar 00root root 0000000 0000000 conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/top/Release/Manifest.py 0000664 0000000 0000000 00000000327 12314554267 0026441 0 ustar 00root root 0000000 0000000 files = [
"conv_ttl_blo.ucf",
"conv_ttl_blo.vhd"
]
modules = {
"local" : [
"../../ip_cores/general-cores",
"../../modules/Release",
"../../modules"
]
}
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/top/Release/conv_ttl_blo.ucf 0000664 0000000 0000000 00000044652 12314554267 0027515 0 ustar 00root root 0000000 0000000 ##--==============================================================================
##-- CERN (BE-CO-HT)
##-- Glitch filter with selectable length
##--==============================================================================
##--
##-- author: Theodor Stana (t.stana@cern.ch)
##-- Carlos-Gil Soriano
##--
##-- date of creation: 2013-04-26
##--
##-- version: 1.0
##--
##-- description:
##-- This file contains the pin definitions for the CONV-TTL-BLO FPGA. The pin
##-- names reflect those of net names at the schematic level. To keep to CERN
##-- coding standards (http://www.ohwr.org/documents/24) and make the code more
##-- readable, the pin names have been lowercased and the pin type is indicated
##-- by its suffix. The suffix "_i" indicates an input pin, "_o" an output pin
##-- and "_b" a bidirectional pin.
##--
##-- An example of net name change is given below:
##-- LED_WR_OWNADDR_I2C -> led_wr_ownaddr_i2c_o
##--
##-- Apart from this, some pins have been renamed completely and do not resemble
##-- the schematics. These pins are:
##-- TTL/INV_TTL_N -> ttl_switch_n_i
##--
##-- dependencies:
##--
##-- references:
##--
##--==============================================================================
##-- GNU LESSER GENERAL PUBLIC LICENSE
##--==============================================================================
##-- This source file is free software; you can redistribute it and/or modify it
##-- under the terms of the GNU Lesser General Public License as published by the
##-- Free Software Foundation; either version 2.1 of the License, or (at your
##-- option) any later version. This source is distributed in the hope that it
##-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
##-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
##-- See the GNU Lesser General Public License for more details. You should have
##-- received a copy of the GNU Lesser General Public License along with this
##-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
##--==============================================================================
##-- last changes:
##-- 2013-04-26 Theodor Stana t.stana@cern.ch File modified
##--==============================================================================
##-- TODO: -
##--==============================================================================
##-----------------------------------------------------------------------------
##-- Default attributes
##--
##-- IOSTANDARD = "LVCMOS25"
##-- SLEW = "SLOW"
##-- DRIVE = "12"
##-----------------------------------------------------------------------------
#NET "rst_i" LOC = N20;
#NET "rst_i" IOSTANDARD = "LVCMOS33";
#NET "fpga_sysreset_n_i" LOC = L20;
NET "mr_n_o" LOC = T22;
NET "mr_n_o" IOSTANDARD = LVCMOS33;
NET "clk_20_vcxo_i" LOC = E16;
NET "clk_20_vcxo_i" TNM_NET = "clk_20_vcxo_i";
TIMESPEC TSCLK20 = PERIOD "clk_20_vcxo_i" 20 MHz HIGH 50 %;
NET "fpga_clk_p_i" LOC = H12;
NET "fpga_clk_n_i" LOC = G11;
NET "fpga_clk_p_i" TNM_NET = "clk_125";
TIMESPEC TSCLK125 = PERIOD "clk_125" 125 MHz HIGH 50 %;
##=============================================================================
##-- FRONT PANEL TTLs
##=============================================================================
##-----------------------------------------------------------------------------
##-- Status LEDs
##-----------------------------------------------------------------------------
NET "led_ctrl0_o" LOC = M18;
NET "led_ctrl0_o" IOSTANDARD = LVCMOS33;
NET "led_ctrl0_oen_o" LOC = T20;
NET "led_ctrl0_oen_o" IOSTANDARD = LVCMOS33;
NET "led_ctrl1_o" LOC = M17;
NET "led_ctrl1_o" IOSTANDARD = LVCMOS33;
NET "led_ctrl1_oen_o" LOC = U19;
NET "led_ctrl1_oen_o" IOSTANDARD = LVCMOS33;
NET "led_multicast_2_0_o" LOC = P16;
NET "led_multicast_2_0_o" IOSTANDARD = LVCMOS33;
NET "led_multicast_3_1_o" LOC = P17;
NET "led_multicast_3_1_o" IOSTANDARD = LVCMOS33;
NET "led_wr_gmt_ttl_ttln_o" LOC = N16;
NET "led_wr_gmt_ttl_ttln_o" IOSTANDARD = LVCMOS33;
NET "led_wr_link_syserror_o" LOC = R15;
NET "led_wr_link_syserror_o" IOSTANDARD = LVCMOS33;
NET "led_wr_ok_syspw_o" LOC = R16;
NET "led_wr_ok_syspw_o" IOSTANDARD = LVCMOS33;
NET "led_wr_ownaddr_i2c_o" LOC = N15;
NET "led_wr_ownaddr_i2c_o" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- Front channel LEDs
##-----------------------------------------------------------------------------
NET "pulse_front_led_n_o[1]" LOC = H5;
NET "pulse_front_led_n_o[1]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[1]" DRIVE = 4;
NET "pulse_front_led_n_o[1]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[2]" LOC = J6;
NET "pulse_front_led_n_o[2]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[2]" DRIVE = 4;
NET "pulse_front_led_n_o[2]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[3]" LOC = K6;
NET "pulse_front_led_n_o[3]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[3]" DRIVE = 4;
NET "pulse_front_led_n_o[3]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[4]" LOC = K5;
NET "pulse_front_led_n_o[4]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[4]" DRIVE = 4;
NET "pulse_front_led_n_o[4]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[5]" LOC = M7;
NET "pulse_front_led_n_o[5]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[5]" DRIVE = 4;
NET "pulse_front_led_n_o[5]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[6]" LOC = M6;
NET "pulse_front_led_n_o[6]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[6]" DRIVE = 4;
NET "pulse_front_led_n_o[6]" SLEW = QUIETIO;
##-----------------------------------------------------------------------------
##-- Rear LEDs
##-----------------------------------------------------------------------------
NET "pulse_rear_led_n_o[1]" LOC = AB17;
NET "pulse_rear_led_n_o[1]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[1]" DRIVE = 4;
NET "pulse_rear_led_n_o[1]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[2]" LOC = AB19;
NET "pulse_rear_led_n_o[2]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[2]" DRIVE = 4;
NET "pulse_rear_led_n_o[2]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[3]" LOC = AA16;
NET "pulse_rear_led_n_o[3]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[3]" DRIVE = 4;
NET "pulse_rear_led_n_o[3]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[4]" LOC = AA18;
NET "pulse_rear_led_n_o[4]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[4]" DRIVE = 4;
NET "pulse_rear_led_n_o[4]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[5]" LOC = AB16;
NET "pulse_rear_led_n_o[5]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[5]" DRIVE = 4;
NET "pulse_rear_led_n_o[5]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[6]" LOC = AB18;
NET "pulse_rear_led_n_o[6]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[6]" DRIVE = 4;
NET "pulse_rear_led_n_o[6]" SLEW = QUIETIO;
##-----------------------------------------------------------------------------
##-- TTL trigger I/O
##-----------------------------------------------------------------------------
NET "fpga_input_ttl_n_i[1]" LOC = T2;
NET "fpga_input_ttl_n_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[1]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[2]" LOC = U3;
NET "fpga_input_ttl_n_i[2]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[2]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[3]" LOC = V5;
NET "fpga_input_ttl_n_i[3]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[3]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[4]" LOC = W4;
NET "fpga_input_ttl_n_i[4]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[4]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[5]" LOC = T6;
NET "fpga_input_ttl_n_i[5]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[5]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[6]" LOC = T3;
NET "fpga_input_ttl_n_i[6]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[6]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_out_ttl_o[1]" LOC = C1;
NET "fpga_out_ttl_o[1]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[2]" LOC = F2;
NET "fpga_out_ttl_o[2]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[3]" LOC = F5;
NET "fpga_out_ttl_o[3]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[4]" LOC = H4;
NET "fpga_out_ttl_o[4]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[5]" LOC = J4;
NET "fpga_out_ttl_o[5]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[6]" LOC = H2;
NET "fpga_out_ttl_o[6]" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- Inverted TTL I/O
##-----------------------------------------------------------------------------
NET "inv_in_n_i[1]" LOC = V2;
NET "inv_in_n_i[1]" IOSTANDARD = LVCMOS33;
NET "inv_in_n_i[1]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "inv_in_n_i[2]" LOC = W3;
NET "inv_in_n_i[2]" IOSTANDARD = LVCMOS33;
NET "inv_in_n_i[2]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "inv_in_n_i[3]" LOC = Y2;
NET "inv_in_n_i[3]" IOSTANDARD = LVCMOS33;
NET "inv_in_n_i[3]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "inv_in_n_i[4]" LOC = AA2;
NET "inv_in_n_i[4]" IOSTANDARD = LVCMOS33;
NET "inv_in_n_i[4]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "inv_out_o[1]" LOC = J3;
NET "inv_out_o[1]" IOSTANDARD = LVCMOS33;
NET "inv_out_o[2]" LOC = L3;
NET "inv_out_o[2]" IOSTANDARD = LVCMOS33;
NET "inv_out_o[3]" LOC = M3;
NET "inv_out_o[3]" IOSTANDARD = LVCMOS33;
NET "inv_out_o[4]" LOC = P2;
NET "inv_out_o[4]" IOSTANDARD = LVCMOS33;
##=============================================================================
##-- RTM signals
##=============================================================================
##-----------------------------------------------------------------------------
##-- Blocking I/O
##-----------------------------------------------------------------------------
NET "fpga_blo_in_i[1]" LOC = Y9;
NET "fpga_blo_in_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_blo_in_i[2]" LOC = AA10;
NET "fpga_blo_in_i[2]" IOSTANDARD = LVCMOS33;
NET "fpga_blo_in_i[3]" LOC = W12;
NET "fpga_blo_in_i[3]" IOSTANDARD = LVCMOS33;
NET "fpga_blo_in_i[4]" LOC = AA6;
NET "fpga_blo_in_i[4]" IOSTANDARD = LVCMOS33;
NET "fpga_blo_in_i[5]" LOC = Y7;
NET "fpga_blo_in_i[5]" IOSTANDARD = LVCMOS33;
NET "fpga_blo_in_i[6]" LOC = AA8;
NET "fpga_blo_in_i[6]" IOSTANDARD = LVCMOS33;
NET "fpga_trig_blo_o[1]" LOC = W9;
NET "fpga_trig_blo_o[1]" IOSTANDARD = LVCMOS33;
NET "fpga_trig_blo_o[2]" LOC = T10;
NET "fpga_trig_blo_o[2]" IOSTANDARD = LVCMOS33;
NET "fpga_trig_blo_o[3]" LOC = V7;
NET "fpga_trig_blo_o[3]" IOSTANDARD = LVCMOS33;
NET "fpga_trig_blo_o[4]" LOC = U9;
NET "fpga_trig_blo_o[4]" IOSTANDARD = LVCMOS33;
NET "fpga_trig_blo_o[5]" LOC = T8;
NET "fpga_trig_blo_o[5]" IOSTANDARD = LVCMOS33;
NET "fpga_trig_blo_o[6]" LOC = R9;
NET "fpga_trig_blo_o[6]" IOSTANDARD = LVCMOS33;
##=============================================================================
##-- VME CONNECTOR SIGNALS
##=============================================================================
##-----------------------------------------------------------------------------
##-- I2C lines
##-----------------------------------------------------------------------------
NET "scl_i" LOC = F19;
NET "scl_i" IOSTANDARD = LVCMOS33;
NET "scl_o" LOC = E20;
NET "scl_o" IOSTANDARD = LVCMOS33;
NET "scl_o" DRIVE = 4;
NET "scl_oe_o" LOC = H18;
NET "scl_oe_o" IOSTANDARD = LVCMOS33;
NET "scl_oe_o" DRIVE = 4;
# NET "scl_oe_o" PULLDOWN;
NET "sda_i" LOC = G20;
NET "sda_i" IOSTANDARD = LVCMOS33;
NET "sda_o" LOC = F20;
NET "sda_o" IOSTANDARD = LVCMOS33;
NET "sda_o" SLEW = FAST;
NET "sda_o" DRIVE = 4;
# NET "sda_o" PULLUP;
NET "sda_oe_o" LOC = J19;
NET "sda_oe_o" IOSTANDARD = LVCMOS33;
NET "sda_oe_o" SLEW = FAST;
NET "sda_oe_o" DRIVE = 4;
# NET "sda_oe_o" PULLDOWN;
##-----------------------------------------------------------------------------
##-- Geographical Address
##-----------------------------------------------------------------------------
NET "fpga_ga_i[0]" LOC = H20;
NET "fpga_ga_i[0]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[1]" LOC = J20;
NET "fpga_ga_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[2]" LOC = K19;
NET "fpga_ga_i[2]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[3]" LOC = K20;
NET "fpga_ga_i[3]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[4]" LOC = L19;
NET "fpga_ga_i[4]" IOSTANDARD = LVCMOS33;
NET "fpga_gap_i" LOC = H19;
NET "fpga_gap_i" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- ROM memory
##-----------------------------------------------------------------------------
NET "fpga_prom_cclk_o" LOC = Y20;
NET "fpga_prom_cclk_o" IOSTANDARD = LVCMOS33;
NET "fpga_prom_cso_b_n_o" LOC = AA3;
NET "fpga_prom_cso_b_n_o" IOSTANDARD = LVCMOS33;
NET "fpga_prom_miso_i" LOC = AA20;
NET "fpga_prom_miso_i" IOSTANDARD = LVCMOS33;
NET "fpga_prom_mosi_o" LOC = AB20;
NET "fpga_prom_mosi_o" IOSTANDARD = LVCMOS33;
##=============================================================================
##-- WHITE RABBIT
##=============================================================================
##-----------------------------------------------------------------------------
##-- Thermo for UID
##-----------------------------------------------------------------------------
NET "thermometer_b" LOC = B1;
NET "thermometer_b" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- DAC control
##-----------------------------------------------------------------------------
NET "fpga_plldac1_din_o" LOC = AB14;
NET "fpga_plldac1_din_o" IOSTANDARD = LVCMOS33;
NET "fpga_plldac1_sclk_o" LOC = AA14;
NET "fpga_plldac1_sclk_o" IOSTANDARD = LVCMOS33;
NET "fpga_plldac1_sync_n_o" LOC = AB15;
NET "fpga_plldac1_sync_n_o" IOSTANDARD = LVCMOS33;
NET "fpga_plldac2_din_o" LOC = W14;
NET "fpga_plldac2_din_o" IOSTANDARD = LVCMOS33;
NET "fpga_plldac2_sclk_o" LOC = Y14;
NET "fpga_plldac2_sclk_o" IOSTANDARD = LVCMOS33;
NET "fpga_plldac2_sync_n_o" LOC = W13;
NET "fpga_plldac2_sync_n_o" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- SFP connection
##-----------------------------------------------------------------------------
NET "fpga_sfp_los_i" LOC = G3;
NET "fpga_sfp_los_i" IOSTANDARD = LVCMOS33;
NET "fpga_sfp_mod_def0_i" LOC = K8;
NET "fpga_sfp_mod_def0_i" IOSTANDARD = LVCMOS33;
NET "fpga_sfp_rate_select_o" LOC = C4;
NET "fpga_sfp_rate_select_o" IOSTANDARD = LVCMOS33;
NET "fpga_sfp_mod_def1_b" LOC = G4;
NET "fpga_sfp_mod_def1_b" IOSTANDARD = LVCMOS33;
NET "fpga_sfp_mod_def2_b" LOC = F3;
NET "fpga_sfp_mod_def2_b" IOSTANDARD = LVCMOS33;
NET "fpga_sfp_tx_disable_o" LOC = E4;
NET "fpga_sfp_tx_disable_o" IOSTANDARD = LVCMOS33;
NET "fpga_sfp_tx_fault_i" LOC = D2;
NET "fpga_sfp_tx_fault_i" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- FPGA MGT lines
##-----------------------------------------------------------------------------
#NET "fpga_mgt_clk0_p_i" LOC = A10;
#NET "fpga_mgt_clk0_n_i" LOC = B10;
#
#NET "mgt_sfp_rx0_p_i" LOC = D7;
#NET "mgt_sfp_rx0_n_i" LOC = C7;
#
#NET "mgt_sfp_tx0_p_o" LOC = B6;
#NET "mgt_sfp_tx0_n_o" LOC = A6;
##=============================================================================
##-- ADDITIONAL PINS
##=============================================================================
NET "fpga_oe_o" LOC = R3;
NET "fpga_oe_o" IOSTANDARD = LVCMOS33;
NET "fpga_oe_o" DRIVE = 4;
NET "fpga_oe_o" SLEW = QUIETIO;
NET "fpga_blo_oe_o" LOC = P5;
NET "fpga_blo_oe_o" IOSTANDARD = LVCMOS33;
NET "fpga_blo_oe_o" DRIVE = 4;
NET "fpga_blo_oe_o" SLEW = QUIETIO;
NET "fpga_trig_ttl_oe_o" LOC = N3;
NET "fpga_trig_ttl_oe_o" IOSTANDARD = LVCMOS33;
NET "fpga_trig_ttl_oe_o" DRIVE = 4;
NET "fpga_trig_ttl_oe_o" SLEW = QUIETIO;
NET "fpga_inv_oe_o" LOC = P6;
NET "fpga_inv_oe_o" IOSTANDARD = LVCMOS33;
NET "fpga_inv_oe_o" DRIVE = 4;
NET "fpga_inv_oe_o" SLEW = QUIETIO;
##-----------------------------------------------------------------------------
##-- Configuration Switches
##-----------------------------------------------------------------------------
NET "extra_switch_n_i[1]" LOC = F22;
NET "extra_switch_n_i[1]" IOSTANDARD = LVCMOS33;
NET "extra_switch_n_i[2]" LOC = G22;
NET "extra_switch_n_i[2]" IOSTANDARD = LVCMOS33;
NET "extra_switch_n_i[3]" LOC = H21;
NET "extra_switch_n_i[3]" IOSTANDARD = LVCMOS33;
NET "extra_switch_n_i[4]" LOC = H22;
NET "extra_switch_n_i[4]" IOSTANDARD = LVCMOS33;
NET "extra_switch_n_i[5]" LOC = J22;
NET "extra_switch_n_i[5]" IOSTANDARD = LVCMOS33;
NET "extra_switch_n_i[6]" LOC = K21;
NET "extra_switch_n_i[6]" IOSTANDARD = LVCMOS33;
NET "extra_switch_n_i[7]" LOC = K22;
NET "extra_switch_n_i[7]" IOSTANDARD = LVCMOS33;
NET "ttl_switch_n_i" LOC = L22;
NET "ttl_switch_n_i" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- Motherboard and piggyback IDs
##-----------------------------------------------------------------------------
NET "fpga_rtmm_n_i[0]" LOC = V21;
NET "fpga_rtmm_n_i[0]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmm_n_i[1]" LOC = V22;
NET "fpga_rtmm_n_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmm_n_i[2]" LOC = U22;
NET "fpga_rtmm_n_i[2]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmp_n_i[0]" LOC = W22;
NET "fpga_rtmp_n_i[0]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmp_n_i[1]" LOC = Y22;
NET "fpga_rtmp_n_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmp_n_i[2]" LOC = Y21;
NET "fpga_rtmp_n_i[2]" IOSTANDARD = LVCMOS33;
###-----------------------------------------------------------------------------
###-- General purpose
###-----------------------------------------------------------------------------
# NET "fpga_header_out_n_o[1]" LOC = F15;
# NET "fpga_header_out_n_o[1]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[2]" LOC = F16;
# NET "fpga_header_out_n_o[2]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[3]" LOC = F17;
# NET "fpga_header_out_n_o[3]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[4]" LOC = F14;
# NET "fpga_header_out_n_o[4]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[5]" LOC = H14;
# NET "fpga_header_out_n_o[5]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[6]" LOC = H13;
# NET "fpga_header_out_n_o[6]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[1]" LOC = A17;
# NET "fpga_header_in_n_i[1]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[2]" LOC = A18;
# NET "fpga_header_in_n_i[2]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[3]" LOC = B18;
# NET "fpga_header_in_n_i[3]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[4]" LOC = A19;
# NET "fpga_header_in_n_i[4]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[5]" LOC = A20;
# NET "fpga_header_in_n_i[5]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[6]" LOC = B20;
# NET "fpga_header_in_n_i[6]" IOSTANDARD = "LVCMOS33";
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/top/Release/conv_ttl_blo.vhd 0000664 0000000 0000000 00000153357 12314554267 0027524 0 ustar 00root root 0000000 0000000 --==============================================================================
-- CERN (BE-CO-HT)
-- Top level entity of CONV-TTL-BLO
-- http://www.ohwr.org/projects/conv-ttl-blo
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
-- Carlos-Gil-Soriano
--
-- version: 1.0
--
-- description:
-- This is the top-level file for the CONV-TTL-BLO board. It instantiates all
-- components needed in the design and generates the necessary logic for
-- pulse conversion to occur on each channel.
--
-- Details about the HDL design can be found by reading the HDL guide of the
-- project in the doc/ folder.
--
-- dependencies:
-- general-cores repository [1]
--
-- references:
-- [1] Platform-independent core collection webpage on OHWR,
-- http://www.ohwr.org/projects/general-cores/repository
-- [2] ELMA, Access to board data using SNMP and I2C
-- http://www.ohwr.org/documents/227
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 26-11-2013 Theodor Stana Changed file header
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
library unisim;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use unisim.vcomponents.all;
use work.bicolor_led_ctrl_pkg.all;
use work.wishbone_pkg.all;
use work.gencores_pkg.all;
use work.genram_pkg.all;
entity conv_ttl_blo is
generic
(
g_nr_ttl_chan : natural := 6;
g_nr_inv_chan : natural := 4;
g_sim : boolean := false
);
port
(
-- Clocks
-- 20 MHz from VCXO
clk_20_vcxo_i : in std_logic;
-- 125 MHz from clock generator
fpga_clk_p_i : in std_logic;
fpga_clk_n_i : in std_logic;
-- LEDs
led_ctrl0_o : out std_logic;
led_ctrl0_oen_o : out std_logic;
led_ctrl1_o : out std_logic;
led_ctrl1_oen_o : out std_logic;
led_multicast_2_0_o : out std_logic;
led_multicast_3_1_o : out std_logic;
led_wr_gmt_ttl_ttln_o : out std_logic;
led_wr_link_syserror_o : out std_logic;
led_wr_ok_syspw_o : out std_logic;
led_wr_ownaddr_i2c_o : out std_logic;
-- I/Os for pulses
pulse_front_led_n_o : out std_logic_vector(g_nr_ttl_chan downto 1);
pulse_rear_led_n_o : out std_logic_vector(g_nr_ttl_chan downto 1);
fpga_input_ttl_n_i : in std_logic_vector(g_nr_ttl_chan downto 1);
fpga_out_ttl_o : out std_logic_vector(g_nr_ttl_chan downto 1);
fpga_blo_in_i : in std_logic_vector(g_nr_ttl_chan downto 1);
fpga_trig_blo_o : out std_logic_vector(g_nr_ttl_chan downto 1);
inv_in_n_i : in std_logic_vector(g_nr_inv_chan downto 1);
inv_out_o : out std_logic_vector(g_nr_inv_chan downto 1);
-- Output enable lines
fpga_oe_o : out std_logic;
fpga_blo_oe_o : out std_logic;
fpga_trig_ttl_oe_o : out std_logic;
fpga_inv_oe_o : out std_logic;
--TTL/INV_TTL_N
ttl_switch_n_i : in std_logic;
extra_switch_n_i : in std_logic_vector(7 downto 1);
-- Lines for the i2c_slave
scl_i : in std_logic;
scl_o : out std_logic;
scl_oe_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
sda_oe_o : out std_logic;
fpga_ga_i : in std_logic_vector(4 downto 0);
fpga_gap_i : in std_logic;
-- Flash memory lines
fpga_prom_cclk_o : out std_logic;
fpga_prom_cso_b_n_o : out std_logic;
fpga_prom_mosi_o : out std_logic;
fpga_prom_miso_i : in std_logic;
-- Blocking power supply reset line
mr_n_o : out std_logic;
-- Thermometer line
thermometer_b : inout std_logic;
-- PLL DACs
-- DAC1: 20 MHz VCXO control
fpga_plldac1_din_o : out std_logic;
fpga_plldac1_sclk_o : out std_logic;
fpga_plldac1_sync_n_o : out std_logic;
-- DAC2: 125 MHz clock generator control
fpga_plldac2_din_o : out std_logic;
fpga_plldac2_sclk_o : out std_logic;
fpga_plldac2_sync_n_o : out std_logic;
-- SFP lines
fpga_sfp_los_i : in std_logic;
fpga_sfp_mod_def0_i : in std_logic;
fpga_sfp_rate_select_o : out std_logic;
fpga_sfp_mod_def1_b : inout std_logic;
fpga_sfp_mod_def2_b : inout std_logic;
fpga_sfp_tx_disable_o : out std_logic;
fpga_sfp_tx_fault_i : in std_logic;
-- RTM identifiers, should match with the expected values
fpga_rtmm_n_i : in std_logic_vector(2 downto 0);
fpga_rtmp_n_i : in std_logic_vector(2 downto 0)
);
end conv_ttl_blo;
architecture behav of conv_ttl_blo is
--============================================================================
-- Type declarations
--============================================================================
type t_ttlbar_nosig_cnt is array (1 to g_nr_ttl_chan) of unsigned(10 downto 0);
type t_pulse_led_cnt is array (1 to g_nr_ttl_chan) of unsigned(18 downto 0);
type t_pulse_cnt is array (1 to g_nr_ttl_chan) of unsigned(31 downto 0);
type t_ch_pcr is array (1 to g_nr_ttl_chan) of std_logic_vector(31 downto 0);
--============================================================================
-- Function and procedure declarations
--============================================================================
function f_reset_width return positive is
variable retval : positive;
begin
retval := 2*(10**6);
if g_sim then
retval := 20;
end if;
assert false report "Reset width: " & integer'image(retval)
& "*50ns" severity Note;
return retval;
end function f_reset_width;
--============================================================================
-- Constant declarations
--============================================================================
-- Board ID - ASCII string "TBLO"
constant c_board_id : std_logic_vector(31 downto 0) := x"54424c4f";
-- Gateware version
-- - format: M.m
-- - M: major version hex number (e.g. 1)
-- - m: minor version hex number (e.g. 13)
-- - example: first major release v1.0 c_gwvers = x"10";
-- next minor release v1.1 c_gwvers = x"11";
-- 13 minor releases later v1.14 c_gwvers = x"1e";
-- next major release v2.0 c_gwvers = x"20";
constant c_gwvers : std_logic_vector(7 downto 0) := x"21";
-- Number of Wishbone masters and slaves, for wb_crossbar
constant c_nr_masters : natural := 1;
constant c_nr_slaves : natural := 3;
------------------------------------------------------------------------------
-- Memory map
-- * all registers are word-addressable
-- * all registers are word-aligned
------------------------------------------------------------------------------
-- CONV_REGS [000-020]
-- MULTIBOOT [040-050]
-- ONEWIRE [080-]
------------------------------------------------------------------------------
-- slave order definitions
constant c_slv_conv_regs : natural := 0;
constant c_slv_multiboot : natural := 1;
constant c_slv_onewire_mst : natural := 2;
-- base address definitions
constant c_addr_conv_regs : t_wishbone_address := x"00000000";
constant c_addr_multiboot : t_wishbone_address := x"00000040";
constant c_addr_onewire_mst : t_wishbone_address := x"00000080";
-- address mask definitions
constant c_mask_conv_regs : t_wishbone_address := x"00000fc0";
constant c_mask_multiboot : t_wishbone_address := x"00000fc0";
constant c_mask_onewire_mst : t_wishbone_address := x"00000fe0";
-- addresses constant for Wishbone crossbar
constant c_addresses : t_wishbone_address_array(c_nr_slaves-1 downto 0)
:= (
c_slv_conv_regs => c_addr_conv_regs,
c_slv_multiboot => c_addr_multiboot,
c_slv_onewire_mst => c_addr_onewire_mst
);
-- masks constant for Wishbone crossbar
constant c_masks : t_wishbone_address_array(c_nr_slaves-1 downto 0)
:= (
c_slv_conv_regs => c_mask_conv_regs,
c_slv_multiboot => c_mask_multiboot,
c_slv_onewire_mst => c_mask_onewire_mst
);
------------------------------------------------------------------------------
-- Pulse generator glitch filter length
------------------------------------------------------------------------------
constant c_pulse_gen_pwidth : positive := 24;
constant c_pulse_gen_duty_cycle_div : positive := 500;
constant c_pulse_gen_gf_len : positive := 1;
------------------------------------------------------------------------------
-- Pulse time-tag ring buffer constants
------------------------------------------------------------------------------
-- data width: 40 -- TAI
-- 28 -- cycles
-- 1 -- WRPRES bit
-- xx -- channel mask
constant c_tb_data_width : positive := 40 + 28 + 1 + g_nr_ttl_chan;
-- size in number of (data width)-sized samples
constant c_tb_size : positive := 128;
-- <<<< NOTE >>>> Also change USEDW size in conv_regs.vhd <<<< NOTE >>>>
-- <<<< NOTE >>>> See README.txt in modules/Release/ <<<< NOTE >>>>
--============================================================================
-- Component declarations
--============================================================================
------------------------------------------------------------------------------
-- Reset generator component
-- (use: global reset generation, output reset generation)
------------------------------------------------------------------------------
component reset_gen is
generic
(
-- Reset time in number of clk_i cycles
g_reset_time : positive := 2_000_000
);
port
(
clk_i : in std_logic;
rst_i : in std_logic;
rst_n_o : out std_logic
);
end component reset_gen;
------------------------------------------------------------------------------
-- Pulse generator component
-- (use: output pulse generation, pulse status LEDs)
------------------------------------------------------------------------------
component ctblo_pulse_gen is
generic
(
-- Pulse width, in number of clk_i cycles
-- Default pulse width (20 MHz clock): 1.2 us
-- Minimum allowable pulse width (20 MHz clock): 1 us
-- Maximum allowable pulse width (20 MHz clock): 2 us
g_pwidth : natural range 20 to 40 := 24;
-- Duty cycle divider: D = 1/g_duty_cycle_div
g_duty_cycle_div : natural := 5
);
port
(
-- Clock and active-low reset inputs
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Glitch filter enable input
-- '1' - Glitch filter disabled (glitch-sensitive, no output jitter)
-- '0' - Glitch filter enabled (glitch-insensitive, with output jitter)
gf_en_n_i : in std_logic;
-- Enable input, pulse generation is enabled when '1'
en_i : in std_logic;
-- Trigger input, has to be '1' to assure pulse output with delay no greater
-- than internal gate delays.
trig_a_i : in std_logic;
-- Pulse output, active-high
-- latency:
-- glitch filter disabled: none
-- glitch filter enabled: glitch filter length + 5 clk_i cycles
pulse_o : out std_logic
);
end component ctblo_pulse_gen;
------------------------------------------------------------------------------
-- RTM detector component
-- (use: detect the presence of an RTM/P module)
------------------------------------------------------------------------------
component rtm_detector is
port
(
rtmm_i : in std_logic_vector(2 downto 0);
rtmp_i : in std_logic_vector(2 downto 0);
rtmm_ok_o : out std_logic;
rtmp_ok_o : out std_logic
);
end component rtm_detector;
------------------------------------------------------------------------------
-- Converter board control registers
------------------------------------------------------------------------------
component conv_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'ID register bits' in reg: 'BIDR'
reg_bidr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Gateware version' in reg: 'SR'
reg_sr_gwvers_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'Status of on-board switches' in reg: 'SR'
reg_sr_switches_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'RTM detection lines~\cite{rtm-det}' in reg: 'SR'
reg_sr_rtm_i : in std_logic_vector(5 downto 0);
-- Ports for BIT field: 'Communication watchdog timer status' in reg: 'SR'
reg_sr_i2c_wdto_o : out std_logic;
reg_sr_i2c_wdto_i : in std_logic;
reg_sr_i2c_wdto_load_o : out std_logic;
-- Port for BIT field: 'White Rabbit present' in reg: 'SR'
reg_sr_wrpres_i : in std_logic;
-- Ports for BIT field: 'Reset unlock bit' in reg: 'CR'
reg_cr_rst_unlock_o : out std_logic;
reg_cr_rst_unlock_i : in std_logic;
reg_cr_rst_unlock_load_o : out std_logic;
-- Ports for BIT field: 'Reset bit' in reg: 'CR'
reg_cr_rst_o : out std_logic;
reg_cr_rst_i : in std_logic;
reg_cr_rst_load_o : out std_logic;
-- Ports for PASS_THROUGH field: 'Manual Pulse Trigger' in reg: 'CR'
reg_cr_mpt_o : out std_logic_vector(7 downto 0);
reg_cr_mpt_wr_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH1PCR'
reg_ch1pcr_o : out std_logic_vector(31 downto 0);
reg_ch1pcr_i : in std_logic_vector(31 downto 0);
reg_ch1pcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH2PCR'
reg_ch2pcr_o : out std_logic_vector(31 downto 0);
reg_ch2pcr_i : in std_logic_vector(31 downto 0);
reg_ch2pcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH3PCR'
reg_ch3pcr_o : out std_logic_vector(31 downto 0);
reg_ch3pcr_i : in std_logic_vector(31 downto 0);
reg_ch3pcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH4PCR'
reg_ch4pcr_o : out std_logic_vector(31 downto 0);
reg_ch4pcr_i : in std_logic_vector(31 downto 0);
reg_ch4pcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH5PCR'
reg_ch5pcr_o : out std_logic_vector(31 downto 0);
reg_ch5pcr_i : in std_logic_vector(31 downto 0);
reg_ch5pcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH6PCR'
reg_ch6pcr_o : out std_logic_vector(31 downto 0);
reg_ch6pcr_i : in std_logic_vector(31 downto 0);
reg_ch6pcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'TAI seconds counter bits 31..0' in reg: 'TVLR'
reg_tvlr_o : out std_logic_vector(31 downto 0);
reg_tvlr_i : in std_logic_vector(31 downto 0);
reg_tvlr_load_o : out std_logic;
-- Port for std_logic_vector field: 'TAI seconds counter bits 39..32' in reg: 'TVHR'
reg_tvhr_o : out std_logic_vector(7 downto 0);
reg_tvhr_i : in std_logic_vector(7 downto 0);
reg_tvhr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Channel mask' in reg: 'TBMR'
reg_tbmr_chan_i : in std_logic_vector(5 downto 0);
-- Port for BIT field: 'White Rabbit present' in reg: 'TBMR'
reg_tbmr_wrtag_i : in std_logic;
-- Tag buffer read request, asserted when reading from TBMR
reg_tb_rd_req_p_o : out std_logic;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'TBCYR'
reg_tbcyr_i : in std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'TBTLR'
reg_tbtlr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'TBTHR'
reg_tbthr_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'Buffer counter' in reg: 'TBCSR'
reg_tbcsr_usedw_i : in std_logic_vector(6 downto 0);
-- Port for BIT field: 'Buffer full' in reg: 'TBCSR'
reg_tbcsr_full_i : in std_logic;
-- Port for BIT field: 'Buffer empty' in reg: 'TBCSR'
reg_tbcsr_empty_i : in std_logic;
-- Ports for BIT field: 'Clear tag buffer' in reg: 'TBCSR'
reg_tbcsr_clr_o : out std_logic;
reg_tbcsr_clr_i : in std_logic;
reg_tbcsr_clr_load_o : out std_logic
);
end component conv_regs;
------------------------------------------------------------------------------
-- MultiBoot component
-- use: remotely reprogram the FPGA
------------------------------------------------------------------------------
component wb_xil_multiboot is
port
(
-- Clock and reset input ports
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone ports
wbs_i : in t_wishbone_slave_in;
wbs_o : out t_wishbone_slave_out;
-- SPI ports
spi_cs_n_o : out std_logic;
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic
);
end component wb_xil_multiboot;
------------------------------------------------------------------------------
-- Manual pulse trigger component
------------------------------------------------------------------------------
component conv_man_trig is
generic
(
-- Number of conversion channels
g_nr_chan : positive := 6;
-- Length of pulse generator glitch filter, needed to generate a long
-- enough pulse
g_gf_len : positive := 1
);
port
(
-- Clock, active-low inputs
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Control inputs from conv_regs
reg_ld_i : in std_logic;
reg_i : in std_logic_vector(7 downto 0);
-- One-clock pulse output
trig_o : out std_logic_vector(g_nr_chan downto 1)
);
end component conv_man_trig;
------------------------------------------------------------------------------
-- Pulse time-tagging component
------------------------------------------------------------------------------
component conv_pulse_timetag is
generic
(
-- Frequency in Hz of the clk_i signal
g_clk_rate : positive := 125000000;
-- Number of repetition channels
g_nr_chan : positive := 6
);
port
(
-- Clock and active-low reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Asynchronous pulse input
pulse_a_i : in std_logic_vector(g_nr_chan downto 1);
-- Time inputs from White Rabbit
wr_tm_cycles_i : in std_logic_vector(27 downto 0);
wr_tm_tai_i : in std_logic_vector(39 downto 0);
wr_tm_valid_i : in std_logic;
-- Timing inputs from Wishbone-mapped registers
wb_tm_tai_l_i : in std_logic_vector(31 downto 0);
wb_tm_tai_l_ld_i : in std_logic;
wb_tm_tai_h_i : in std_logic_vector( 7 downto 0);
wb_tm_tai_h_ld_i : in std_logic;
-- Timing outputs
tm_cycles_o : out std_logic_vector(27 downto 0);
tm_tai_o : out std_logic_vector(39 downto 0);
tm_wrpres_o : out std_logic;
chan_o : out std_logic_vector(g_nr_chan downto 1);
-- Ring buffer I/O
buf_wr_req_p_o : out std_logic
);
end component conv_pulse_timetag;
------------------------------------------------------------------------------
-- Ring buffer component
-- use: buffer time stamps generated by the conv_pulse_timetag component
------------------------------------------------------------------------------
component conv_ring_buf is
generic
(
g_data_width : positive;
g_size : positive
);
port
(
-- Clocks and reset
clk_rd_i : in std_logic;
clk_wr_i : in std_logic;
rst_n_a_i : in std_logic;
-- Buffer inputs
buf_dat_i : in std_logic_vector(g_data_width-1 downto 0);
buf_rd_req_i : in std_logic;
buf_wr_req_i : in std_logic;
buf_clr_i : in std_logic;
-- Buffer outputs
buf_dat_o : out std_logic_vector(g_data_width-1 downto 0);
buf_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
buf_full_o : out std_logic;
buf_empty_o : out std_logic
);
end component conv_ring_buf;
--============================================================================
-- Signal declarations
--============================================================================
-- Internal clock signals
signal clk_125 : std_logic;
-- Reset signals
signal rst_20_n : std_logic;
signal rst_unlock : std_logic;
signal rst_unlock_bit : std_logic;
signal rst_unlock_bit_ld : std_logic;
signal rst_bit : std_logic;
signal rst_bit_ld : std_logic;
signal rst_fr_reg : std_logic;
signal rst_125_n : std_logic;
-- RTM detection signals
signal rtmm, rtmp : std_logic_vector(2 downto 0);
signal rtmm_ok, rtmp_ok : std_logic;
-- Wishbone crossbar signals
signal xbar_slave_in : t_wishbone_slave_in_array (c_nr_masters - 1 downto 0);
signal xbar_slave_out : t_wishbone_slave_out_array (c_nr_masters - 1 downto 0);
signal xbar_master_in : t_wishbone_master_in_array (c_nr_slaves - 1 downto 0);
signal xbar_master_out : t_wishbone_master_out_array(c_nr_slaves - 1 downto 0);
-- Signals to/from converter system registers component
signal rtm_lines : std_logic_vector(5 downto 0);
signal switches_n : std_logic_vector(7 downto 0);
signal wdto_bit : std_logic;
signal wdto_bit_rst : std_logic;
signal wdto_bit_rst_ld : std_logic;
signal pulse_cnt : t_pulse_cnt;
signal ch_pcr : t_ch_pcr;
signal ch_pcr_ld : std_logic_vector(g_nr_ttl_chan downto 1);
signal mpt_ld : std_logic;
signal mpt : std_logic_vector( 7 downto 0);
signal tvlr : std_logic_vector(31 downto 0);
signal tvlr_ld : std_logic;
signal tvhr : std_logic_vector( 7 downto 0);
signal tvhr_ld : std_logic;
signal wrpres : std_logic;
-- Signals for pulse generation triggers
signal trig_a : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_ttl_a : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_blo_a : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_synced : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_degl : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_chan : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_man : std_logic_vector(g_nr_ttl_chan downto 1);
signal pgen_trig : std_logic_vector(g_nr_ttl_chan downto 1);
signal pcnt_trig_p : std_logic_vector(g_nr_ttl_chan downto 1);
-- TTL-BAR lack of signal counter
signal ttlbar_nosig_cnt : t_ttlbar_nosig_cnt;
signal ttlbar_nosig_n : std_logic_vector(g_nr_ttl_chan downto 1);
-- Temporary signals for blocking and TTL pulse outputs
signal pulse_outp : std_logic_vector(g_nr_ttl_chan downto 1);
signal pulse_outp_d0 : std_logic_vector(g_nr_ttl_chan downto 1);
signal pulse_outp_r_edge_p : std_logic_vector(g_nr_ttl_chan downto 1);
signal blo_ch_en : std_logic_vector(g_nr_ttl_chan downto 1);
-- Pulse status LED signals
signal pulse_leds : std_logic_vector(g_nr_ttl_chan downto 1);
signal pulse_led_cnt : t_pulse_led_cnt;
-- Output enable signals
signal oe, ttl_oe : std_logic;
signal blo_oe, inv_oe : std_logic;
-- Signal for controlling the bicolor LED matrix
signal bicolor_led_state : std_logic_vector(23 downto 0);
-- I2C bridge signals
signal i2c_tip : std_logic;
signal i2c_err_p : std_logic;
signal i2c_wdto_p : std_logic;
signal i2c_addr : std_logic_vector(6 downto 0);
signal led_i2c_err : std_logic;
signal led_i2c : std_logic;
signal led_i2c_clkdiv : unsigned(18 downto 0);
signal led_i2c_cnt : unsigned( 2 downto 0);
signal led_i2c_blink : std_logic;
-- One-wire master signals
signal owr_en : std_logic_vector(0 downto 0);
signal owr_in : std_logic_vector(0 downto 0);
-- Time-tagging component signals
signal tm_cycles : std_logic_vector(27 downto 0);
signal tm_tai : std_logic_vector(39 downto 0);
signal buf_wr_req_p : std_logic;
signal buf_rd_req_p : std_logic;
signal buf_count : std_logic_vector(f_log2_size(c_tb_size)-1 downto 0);
signal buf_full : std_logic;
signal buf_empty : std_logic;
signal buf_chan : std_logic_vector(g_nr_ttl_chan downto 1);
signal buf_wrtag : std_logic;
signal buf_clr_bit : std_logic;
signal buf_clr_bit_ld : std_logic;
signal buf_clr_p : std_logic;
signal buf_dat_in : std_logic_vector(c_tb_data_width-1 downto 0);
signal buf_dat_out : std_logic_vector(c_tb_data_width-1 downto 0);
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Differential input buffer for 125 MHz clock
--============================================================================
cmp_clk_125_buf : IBUFGDS
generic map (
DIFF_TERM => true, -- Differential Termination
IBUF_LOW_PWR => true, -- Low power (TRUE) vs. performance (FALSE) setting
-- for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => clk_125,
I => fpga_clk_p_i,
IB => fpga_clk_n_i
);
--============================================================================
-- Internal and external reset generation
--============================================================================
-- Configure reset generator for 100ms power-on reset
cmp_reset_gen : reset_gen
generic map
(
-- Reset time: 50ns * 2 * (10**6) = 100 ms
g_reset_time => f_reset_width
)
port map
(
clk_i => clk_20_vcxo_i,
rst_i => rst_fr_reg,
rst_n_o => rst_20_n
);
-- Set the blocking power supply reset output with this reset
mr_n_o <= rst_20_n;
-- And synchronize the 20 MHz domain reset into the 125 MHz domain
cmp_sync_rst : gc_sync_ffs
generic map
(
g_sync_edge => "positive"
)
port map
(
clk_i => clk_125,
rst_n_i => '1',
data_i => rst_20_n,
synced_o => rst_125_n
);
--============================================================================
-- I2C bridge logic
--============================================================================
-- Set the I2C address signal according to ELMA protocol [1]
i2c_addr <= "10" & fpga_ga_i;
-- Instantiate VBCP bridge component
cmp_i2c_bridge : wb_i2c_bridge
port map
(
-- Clock, reset
clk_i => clk_20_vcxo_i,
rst_n_i => rst_20_n,
-- I2C lines
scl_i => scl_i,
scl_o => scl_o,
scl_en_o => scl_oe_o,
sda_i => sda_i,
sda_o => sda_o,
sda_en_o => sda_oe_o,
-- I2C address and status
i2c_addr_i => i2c_addr,
-- TIP and ERR outputs
tip_o => i2c_tip,
err_p_o => i2c_err_p,
wdto_p_o => i2c_wdto_p,
-- Wishbone master signals
wbm_stb_o => xbar_slave_in(0).stb,
wbm_cyc_o => xbar_slave_in(0).cyc,
wbm_sel_o => xbar_slave_in(0).sel,
wbm_we_o => xbar_slave_in(0).we,
wbm_dat_i => xbar_slave_out(0).dat,
wbm_dat_o => xbar_slave_in(0).dat,
wbm_adr_o => xbar_slave_in(0).adr,
wbm_ack_i => xbar_slave_out(0).ack,
wbm_rty_i => xbar_slave_out(0).rty,
wbm_err_i => xbar_slave_out(0).err
);
-- Process to blink the LED when an I2C transfer is in progress
-- blinks four times per transfer
-- blink width : 20 ms
-- blink period: 40 ms
p_i2c_blink : process(clk_20_vcxo_i)
begin
if rising_edge(clk_20_vcxo_i) then
if (rst_20_n = '0') then
led_i2c_clkdiv <= (others => '0');
led_i2c_cnt <= (others => '0');
led_i2c <= '0';
led_i2c_blink <= '0';
else
case led_i2c_blink is
when '0' =>
led_i2c <= '0';
if (i2c_tip = '1') then
led_i2c_blink <= '1';
end if;
when '1' =>
led_i2c_clkdiv <= led_i2c_clkdiv + 1;
if (led_i2c_clkdiv = 399999) then
led_i2c_clkdiv <= (others => '0');
led_i2c_cnt <= led_i2c_cnt + 1;
led_i2c <= not led_i2c;
if (led_i2c_cnt = 7) then
led_i2c_cnt <= (others => '0');
led_i2c_blink <= '0';
end if;
end if;
when others =>
led_i2c_blink <= '0';
end case;
end if;
end if;
end process p_i2c_blink;
-- Process to set the I2C error LED signal for display on the front panel
-- of the front module. The I2C error LED signal is permanently set once an
-- error is detected from the bridge module.
p_i2c_err_led : process (clk_20_vcxo_i) is
begin
if rising_edge(clk_20_vcxo_i) then
if (rst_20_n = '0') then
led_i2c_err <= '0';
elsif (i2c_err_p = '1') then
led_i2c_err <= '1';
end if;
end if;
end process p_i2c_err_led;
-- Register for the WDTO bit in the SR, cleared by writing a '1'
p_sr_wdto_bit : process (clk_20_vcxo_i)
begin
if rising_edge(clk_20_vcxo_i) then
if (rst_20_n = '0') then
wdto_bit <= '0';
elsif (i2c_wdto_p = '1') then
wdto_bit <= '1';
elsif (wdto_bit_rst_ld = '1') and (wdto_bit_rst = '1') then
wdto_bit <= '0';
end if;
end if;
end process p_sr_wdto_bit;
--============================================================================
-- Instantiation and connection of the main Wishbone crossbar
--============================================================================
cmp_wb_crossbar : xwb_crossbar
generic map
(
g_num_masters => c_nr_masters,
g_num_slaves => c_nr_slaves,
g_registered => false,
g_address => c_addresses,
g_mask => c_masks
)
port map
(
clk_sys_i => clk_20_vcxo_i,
rst_n_i => rst_20_n,
slave_i => xbar_slave_in,
slave_o => xbar_slave_out,
master_i => xbar_master_in,
master_o => xbar_master_out
);
--============================================================================
-- Converter board registers
--============================================================================
-- Set SWITCH and RTM fields
switches_n <= ttl_switch_n_i & extra_switch_n_i(7 downto 1);
rtm_lines <= rtmp & rtmm;
-- Then, instantiate the component
cmp_conv_regs : conv_regs
port map (
rst_n_i => rst_20_n,
clk_sys_i => clk_20_vcxo_i,
wb_adr_i => xbar_master_out(c_slv_conv_regs).adr(5 downto 2),
wb_dat_i => xbar_master_out(c_slv_conv_regs).dat,
wb_dat_o => xbar_master_in (c_slv_conv_regs).dat,
wb_cyc_i => xbar_master_out(c_slv_conv_regs).cyc,
wb_sel_i => xbar_master_out(c_slv_conv_regs).sel,
wb_stb_i => xbar_master_out(c_slv_conv_regs).stb,
wb_we_i => xbar_master_out(c_slv_conv_regs).we,
wb_ack_o => xbar_master_in (c_slv_conv_regs).ack,
wb_stall_o => xbar_master_in (c_slv_conv_regs).stall,
reg_bidr_i => c_board_id,
reg_sr_gwvers_i => c_gwvers,
reg_sr_switches_i => switches_n,
reg_sr_rtm_i => rtm_lines,
reg_sr_i2c_wdto_o => wdto_bit_rst,
reg_sr_i2c_wdto_i => wdto_bit,
reg_sr_i2c_wdto_load_o => wdto_bit_rst_ld,
reg_sr_wrpres_i => wrpres,
reg_cr_rst_unlock_o => rst_unlock_bit,
reg_cr_rst_unlock_i => rst_unlock,
reg_cr_rst_unlock_load_o => rst_unlock_bit_ld,
reg_cr_rst_o => rst_bit,
reg_cr_rst_i => rst_fr_reg,
reg_cr_rst_load_o => rst_bit_ld,
reg_cr_mpt_o => mpt,
reg_cr_mpt_wr_o => mpt_ld,
reg_ch1pcr_o => ch_pcr(1),
reg_ch1pcr_i => std_logic_vector(pulse_cnt(1)),
reg_ch1pcr_load_o => ch_pcr_ld(1),
reg_ch2pcr_o => ch_pcr(2),
reg_ch2pcr_i => std_logic_vector(pulse_cnt(2)),
reg_ch2pcr_load_o => ch_pcr_ld(2),
reg_ch3pcr_o => ch_pcr(3),
reg_ch3pcr_i => std_logic_vector(pulse_cnt(3)),
reg_ch3pcr_load_o => ch_pcr_ld(3),
reg_ch4pcr_o => ch_pcr(4),
reg_ch4pcr_i => std_logic_vector(pulse_cnt(4)),
reg_ch4pcr_load_o => ch_pcr_ld(4),
reg_ch5pcr_o => ch_pcr(5),
reg_ch5pcr_i => std_logic_vector(pulse_cnt(5)),
reg_ch5pcr_load_o => ch_pcr_ld(5),
reg_ch6pcr_o => ch_pcr(6),
reg_ch6pcr_i => std_logic_vector(pulse_cnt(6)),
reg_ch6pcr_load_o => ch_pcr_ld(6),
reg_tvlr_o => tvlr,
reg_tvlr_i => tm_tai(31 downto 0),
reg_tvlr_load_o => tvlr_ld,
reg_tvhr_o => tvhr,
reg_tvhr_i => tm_tai(39 downto 32),
reg_tvhr_load_o => tvhr_ld,
reg_tbmr_chan_i => buf_dat_out( 5 downto 0),
reg_tbmr_wrtag_i => buf_dat_out( 6),
reg_tb_rd_req_p_o => buf_rd_req_p,
reg_tbcyr_i => buf_dat_out(34 downto 7),
reg_tbtlr_i => buf_dat_out(66 downto 35),
reg_tbthr_i => buf_dat_out(74 downto 67),
reg_tbcsr_clr_o => buf_clr_bit,
reg_tbcsr_clr_i => '0',
reg_tbcsr_clr_load_o => buf_clr_bit_ld,
reg_tbcsr_usedw_i => buf_count,
reg_tbcsr_full_i => buf_full,
reg_tbcsr_empty_i => buf_empty
);
-- Implement the RST_UNLOCK bit
p_rst_unlock : process (clk_20_vcxo_i)
begin
if rising_edge(clk_20_vcxo_i) then
if (rst_20_n = '0') then
rst_unlock <= '0';
elsif (rst_unlock_bit_ld = '1') then
if (rst_unlock_bit = '1') then
rst_unlock <= '1';
else
rst_unlock <= '0';
end if;
end if;
end if;
end process p_rst_unlock;
-- Implement the reset bit register
-- The register can only be set when the RST_UNLOCK bit is '1'.
p_rst_fr_reg : process (clk_20_vcxo_i)
begin
if rising_edge(clk_20_vcxo_i) then
if (rst_20_n = '0') then
rst_fr_reg <= '0';
elsif (rst_bit_ld = '1') and (rst_bit = '1') and (rst_unlock = '1') then
rst_fr_reg <= '1';
else
rst_fr_reg <= '0';
end if;
end if;
end process p_rst_fr_reg;
-- Synchronize WR valid signal to implement the WRPRES bit
cmp_wrpres_sync : gc_sync_ffs
generic map
(
g_sync_edge => "positive"
)
port map
(
clk_i => clk_20_vcxo_i,
rst_n_i => rst_20_n,
data_i => buf_wrtag,
synced_o => wrpres
);
-- Implement the TBCSR.CLR bit
p_tbcsr_clr : process (clk_20_vcxo_i)
begin
if rising_edge(clk_20_vcxo_i) then
if (rst_20_n = '0') then
buf_clr_p <= '0';
else
buf_clr_p <= '0';
if (buf_clr_bit_ld = '1') and (buf_clr_bit = '1') then
buf_clr_p <= '1';
end if;
end if;
end if;
end process p_tbcsr_clr;
--============================================================================
-- Output enable logic
--============================================================================
fpga_oe_o <= '1';
fpga_blo_oe_o <= '1';
fpga_trig_ttl_oe_o <= '1';
fpga_inv_oe_o <= '1';
--============================================================================
-- TTL and blocking pulse generation logic
--============================================================================
------------------------------------------------------------------------------
-- Pulse time-tagging logic after input channel MUX
------------------------------------------------------------------------------
cmp_pulse_timetag : conv_pulse_timetag
generic map
(
-- Frequency in Hz of the clk_i signal
g_clk_rate => 125000000,
-- Number of repetition channels
g_nr_chan => g_nr_ttl_chan
)
port map
(
-- Clock and active-low reset
clk_i => clk_125,
rst_n_i => rst_125_n,
-- Asynchronous pulse input
pulse_a_i => trig_chan,
-- Time inputs from White Rabbit
wr_tm_cycles_i => (others => '0'),
wr_tm_tai_i => (others => '0'),
wr_tm_valid_i => '0',
-- Timing inputs from Wishbone-mapped registers
wb_tm_tai_l_i => tvlr,
wb_tm_tai_l_ld_i => tvlr_ld,
wb_tm_tai_h_i => tvhr,
wb_tm_tai_h_ld_i => tvhr_ld,
-- Timing outputs
tm_cycles_o => tm_cycles,
tm_tai_o => tm_tai,
tm_wrpres_o => buf_wrtag,
chan_o => buf_chan,
-- Ring buffer I/O
buf_wr_req_p_o => buf_wr_req_p
);
-- Assign ring buffer component inputs
buf_dat_in( 5 downto 0) <= buf_chan;
buf_dat_in( 6) <= buf_wrtag;
buf_dat_in(34 downto 7) <= tm_cycles;
buf_dat_in(74 downto 35) <= tm_tai;
-- Instantiate the ring buffer
cmp_ring_buf : conv_ring_buf
generic map
(
g_data_width => c_tb_data_width,
g_size => c_tb_size
)
port map
(
-- Clocks and reset
clk_rd_i => clk_20_vcxo_i,
clk_wr_i => clk_125,
rst_n_a_i => rst_20_n,
-- Buffer inputs
buf_dat_i => buf_dat_in,
buf_rd_req_i => buf_rd_req_p,
buf_wr_req_i => buf_wr_req_p,
buf_clr_i => buf_clr_p,
-- Buffer outputs
buf_dat_o => buf_dat_out,
buf_full_o => buf_full,
buf_empty_o => buf_empty,
buf_count_o => buf_count
);
------------------------------------------------------------------------------
-- Manual trigger
------------------------------------------------------------------------------
cmp_man_trig : conv_man_trig
generic map
(
g_nr_chan => g_nr_ttl_chan,
g_gf_len => c_pulse_gen_gf_len
)
port map
(
-- Clock, active-low inputs
clk_i => clk_20_vcxo_i,
rst_n_i => rst_20_n,
-- Control inputs from conv_regs
reg_ld_i => mpt_ld,
reg_i => mpt,
-- One-clock pulse output
trig_o => trig_man
);
------------------------------------------------------------------------------
-- Generate pulse repetition logic
------------------------------------------------------------------------------
gen_pulse_logic : for i in 1 to g_nr_ttl_chan generate
-- First, the "no signal detect" blocks
--
-- If the signal line is high for 100 us, the ttlbar_nosig_n lines disable
-- the input to the TTL side MUX and the OR gate.
--
-- The counter is disabled if the switch is set for TTL signals, to avoid
-- unnecessary power consumption by the counter.
p_ttlbar_nosig : process(clk_20_vcxo_i)
begin
if rising_edge(clk_20_vcxo_i) then
if (rst_20_n = '0') or (fpga_input_ttl_n_i(i) = '0') then
ttlbar_nosig_n(i) <= '1';
ttlbar_nosig_cnt(i) <= (others => '0');
elsif (ttl_switch_n_i = '1') then
ttlbar_nosig_cnt(i) <= ttlbar_nosig_cnt(i) + 1;
if (ttlbar_nosig_cnt(i) = 1999) then
ttlbar_nosig_n(i) <= '0';
ttlbar_nosig_cnt(i) <= (others => '0');
end if;
end if;
end if;
end process p_ttlbar_nosig;
-- The first OR gate at the channel inputs
trig_ttl_a(i) <= not fpga_input_ttl_n_i(i) when (ttl_switch_n_i = '0') else
fpga_input_ttl_n_i(i) and ttlbar_nosig_n(i);
trig_blo_a(i) <= fpga_blo_in_i(i);
trig_a(i) <= trig_ttl_a(i) or trig_blo_a(i);
-- Then, synchronize the asynchronous trigger input into the 20 MHz clock
-- domain before passing it to the glitch filter
--
-- Reset value is '1' to avoid pulses being counted by pulse counter on
-- startup, when the board is in TTL-BAR repetition mode.
cmp_trig_sync : gc_sync_ffs
generic map
(
g_sync_edge => "positive"
)
port map
(
clk_i => clk_20_vcxo_i,
rst_n_i => '1',
data_i => trig_a(i),
synced_o => trig_synced(i)
);
-- Deglitch synchronized trigger signal
--
-- Reset value is '1' to avoid pulses being counted by pulse counter on
-- startup, when the board is in TTL-BAR repetition mode.
cmp_inp_glitch_filt : gc_glitch_filt
generic map
(
g_len => c_pulse_gen_gf_len
)
port map
(
clk_i => clk_20_vcxo_i,
rst_n_i => '1',
dat_i => trig_synced(i),
dat_o => trig_degl(i)
);
-- Now that we have a deglitched signal, generate the MUX to select between
-- deglitched and direct channel input
trig_chan(i) <= trig_a(i) when extra_switch_n_i(1) = '1' else
trig_degl(i);
-- Now, sync this channel trigger signal before passing it to the counters
--
-- Reset value is '1' to avoid pulses being counted by pulse counter on
-- startup, when the board is in TTL-BAR repetition mode.
--
-- NOTE: glitch-filtered signal is also synced in 20MHz clock domain, but
-- another sync chain here avoids extra logic complication and has no
-- influence on the correctness of the pulse counter value considering the
-- max expected pulse frequency
cmp_sync_ffs : gc_sync_ffs
port map
(
clk_i => clk_20_vcxo_i,
rst_n_i => '1',
data_i => trig_chan(i),
ppulse_o => pcnt_trig_p(i)
);
-- Then, generate the input pulse counters
p_pulse_cnt : process (clk_20_vcxo_i)
begin
if rising_edge(clk_20_vcxo_i) then
if (rst_20_n = '0') then
pulse_cnt(i) <= (others => '0');
elsif (ch_pcr_ld(i) = '1') then
pulse_cnt(i) <= unsigned(ch_pcr(i));
elsif (pcnt_trig_p(i) = '1') then
pulse_cnt(i) <= pulse_cnt(i) + 1;
end if;
end if;
end process p_pulse_cnt;
-- FINALLY, the trigger input to the pulse generator block
pgen_trig(i) <= trig_chan(i) or trig_man(i);
-- Output pulse generators
cmp_pulse_gen : ctblo_pulse_gen
generic map
(
g_pwidth => c_pulse_gen_pwidth,
g_duty_cycle_div => c_pulse_gen_duty_cycle_div
)
port map
(
clk_i => clk_20_vcxo_i,
rst_n_i => rst_20_n,
en_i => '1',
gf_en_n_i => extra_switch_n_i(1),
trig_a_i => pgen_trig(i),
pulse_o => pulse_outp(i)
);
-- Process to flash pulse LED when a pulse is output
-- LED flash length: 26 ms
p_pulse_led : process (clk_20_vcxo_i) is
begin
if rising_edge(clk_20_vcxo_i) then
if (rst_20_n = '0') then
pulse_outp_d0(i) <= '0';
pulse_outp_r_edge_p(i) <= '0';
pulse_led_cnt(i) <= (others => '0');
pulse_leds(i) <= '0';
else
pulse_outp_d0(i) <= pulse_outp(i);
pulse_outp_r_edge_p(i) <= pulse_outp(i) and (not pulse_outp_d0(i));
case pulse_leds(i) is
when '0' =>
if (pulse_outp_r_edge_p(i) = '1') then
pulse_leds(i) <= '1';
end if;
when '1' =>
pulse_led_cnt(i) <= pulse_led_cnt(i) + 1;
if (pulse_led_cnt(i) = (pulse_led_cnt(i)'range => '1')) then
pulse_leds(i) <= '0';
end if;
when others =>
pulse_leds(i) <= '0';
end case;
end if;
end if;
end process;
end generate gen_pulse_logic;
------------------------------------------------------------------------------
-- Pulse and LED outputs assignment
------------------------------------------------------------------------------
-- TTL and blocking outputs
fpga_out_ttl_o <= pulse_outp when (ttl_switch_n_i = '0') else
not pulse_outp;
fpga_trig_blo_o <= pulse_outp;
-- General-purpose INV-TTL outputs
inv_out_o <= inv_in_n_i;
-- Pulse status LED output assignments
pulse_front_led_n_o <= not pulse_leds;
pulse_rear_led_n_o <= not pulse_leds;
--============================================================================
-- MultiBoot logic
--============================================================================
cmp_multiboot : wb_xil_multiboot
port map
(
clk_i => clk_20_vcxo_i,
rst_n_i => rst_20_n,
wbs_i => xbar_master_out(c_slv_multiboot),
wbs_o => xbar_master_in(c_slv_multiboot),
spi_cs_n_o => fpga_prom_cso_b_n_o,
spi_sclk_o => fpga_prom_cclk_o,
spi_mosi_o => fpga_prom_mosi_o,
spi_miso_i => fpga_prom_miso_i
);
--============================================================================
-- On-board DS18B20 Thermometer logic
--============================================================================
-- The one-wire master component is used to control the on-board DS18B20
-- thermometer
cmp_onewire_master : wb_onewire_master
generic map
(
g_interface_mode => CLASSIC,
g_address_granularity => WORD,
g_num_ports => 1,
g_ow_btp_normal => "5.0",
g_ow_btp_overdrive => "1.0"
)
port map
(
clk_sys_i => clk_20_vcxo_i,
rst_n_i => rst_20_n,
wb_cyc_i => xbar_master_out(c_slv_onewire_mst).cyc,
wb_sel_i => xbar_master_out(c_slv_onewire_mst).sel,
wb_stb_i => xbar_master_out(c_slv_onewire_mst).stb,
wb_we_i => xbar_master_out(c_slv_onewire_mst).we,
wb_adr_i => xbar_master_out(c_slv_onewire_mst).adr(4 downto 2),
wb_dat_i => xbar_master_out(c_slv_onewire_mst).dat,
wb_dat_o => xbar_master_in(c_slv_onewire_mst).dat,
wb_ack_o => xbar_master_in(c_slv_onewire_mst).ack,
wb_int_o => open,
wb_stall_o => xbar_master_in(c_slv_onewire_mst).stall,
owr_pwren_o => open,
owr_en_o => owr_en,
owr_i => owr_in
);
-- Generate tri-state buffer for thermometer
thermometer_b <= '0' when (owr_en(0) = '1') else
'Z';
owr_in(0) <= thermometer_b;
--============================================================================
-- Bicolor LED matrix logic
--============================================================================
-- Bicolor LED controls, corresponding to the column orders on the
-- bicolor_led_ctrl unit.
-- WR address
bicolor_led_state( 1 downto 0) <= c_LED_OFF;
-- WR GMT
bicolor_led_state( 3 downto 2) <= c_LED_OFF;
-- WR link
bicolor_led_state( 5 downto 4) <= c_LED_OFF;
-- WR OK
bicolor_led_state( 7 downto 6) <= c_LED_OFF;
-- MULTICAST 0
bicolor_led_state( 9 downto 8) <= c_LED_OFF;
-- MULTICAST 1
bicolor_led_state(11 downto 10) <= c_LED_OFF;
-- I2C
bicolor_led_state(13 downto 12) <= c_LED_GREEN when (led_i2c = '1') else
c_LED_RED when (led_i2c_err = '1') else
c_LED_OFF;
-- State of TTL/TTL_N switch
bicolor_led_state(15 downto 14) <= c_LED_GREEN when (ttl_switch_n_i = '0') else
c_LED_OFF;
-- System error
bicolor_led_state(17 downto 16) <= c_LED_RED when (rtmm_ok = '0') and (rtmp_ok = '0') else
c_LED_OFF;
-- System power
bicolor_led_state(19 downto 18) <= c_LED_GREEN;
-- MULTICAST 2
bicolor_led_state(21 downto 20) <= c_LED_OFF;
-- MULTICAST 3
bicolor_led_state(23 downto 22) <= c_LED_OFF;
cmp_bicolor_led_ctrl : bicolor_led_ctrl
generic map
(
g_NB_COLUMN => 6,
g_NB_LINE => 2,
g_clk_freq => 20000000,
g_refresh_rate => 250
)
port map
(
clk_i => clk_20_vcxo_i,
rst_n_i => rst_20_n,
led_intensity_i => "1111111",
led_state_i => bicolor_led_state,
column_o(0) => led_wr_ownaddr_i2c_o,
column_o(1) => led_wr_gmt_ttl_ttln_o,
column_o(2) => led_wr_link_syserror_o,
column_o(3) => led_wr_ok_syspw_o,
column_o(4) => led_multicast_2_0_o,
column_o(5) => led_multicast_3_1_o,
line_o(0) => led_ctrl0_o,
line_o(1) => led_ctrl1_o,
line_oen_o(0) => led_ctrl0_oen_o,
line_oen_o(1) => led_ctrl1_oen_o
);
--============================================================================
-- RTM detection logic
--============================================================================
rtmm <= not fpga_rtmm_n_i;
rtmp <= not fpga_rtmp_n_i;
cmp_rtm_detector : rtm_detector
port map
(
rtmm_i => rtmm,
rtmp_i => rtmp,
rtmm_ok_o => rtmm_ok,
rtmp_ok_o => rtmp_ok
);
--============================================================================
-- Drive unused outputs with safe values
--============================================================================
-- DAC outputs: enables to '1' (disable DAC comm interface) and SCK, DIN to '0'
fpga_plldac1_sync_n_o <= '1';
fpga_plldac1_din_o <= '0';
fpga_plldac1_sclk_o <= '0';
fpga_plldac2_sync_n_o <= '1';
fpga_plldac2_din_o <= '0';
fpga_plldac2_sclk_o <= '0';
-- SFP lines all open-drain, set to high-impedance
fpga_sfp_rate_select_o <= 'Z';
fpga_sfp_mod_def1_b <= 'Z';
fpga_sfp_mod_def2_b <= 'Z';
fpga_sfp_tx_disable_o <= 'Z';
end behav;
--==============================================================================
-- architecture end
--==============================================================================
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/top/pulsetest/ 0000775 0000000 0000000 00000000000 12314554267 0024767 5 ustar 00root root 0000000 0000000 conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/top/pulsetest/Manifest.py 0000664 0000000 0000000 00000000325 12314554267 0027107 0 ustar 00root root 0000000 0000000 files = [
"pulsetest.ucf",
"pulsetest.vhd"
]
modules = {
"local" : [
"../../ip_cores/general-cores",
"../../modules/pulsetest",
"../../modules"
]
}
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/top/pulsetest/pulsetest.ucf 0000664 0000000 0000000 00000045054 12314554267 0027526 0 ustar 00root root 0000000 0000000 ##--==============================================================================
##-- CERN (BE-CO-HT)
##-- Glitch filter with selectable length
##--==============================================================================
##--
##-- author: Theodor Stana (t.stana@cern.ch)
##-- Carlos-Gil Soriano
##--
##-- date of creation: 2013-04-26
##--
##-- version: 1.0
##--
##-- description:
##-- This file contains the pin definitions for the CONV-TTL-BLO FPGA. The pin
##-- names reflect those of net names at the schematic level. To keep to CERN
##-- coding standards (http://www.ohwr.org/documents/24) and make the code more
##-- readable, the pin names have been lowercased and the pin type is indicated
##-- by its suffix. The suffix "_i" indicates an input pin, "_o" an output pin
##-- and "_b" a bidirectional pin.
##--
##-- An example of net name change is given below:
##-- LED_WR_OWNADDR_I2C -> led_wr_ownaddr_i2c_o
##--
##-- Apart from this, some pins have been renamed completely and do not resemble
##-- the schematics. These pins are:
##-- TTL/INV_TTL_N -> ttl_switch_n_i
##--
##-- dependencies:
##--
##-- references:
##--
##--==============================================================================
##-- GNU LESSER GENERAL PUBLIC LICENSE
##--==============================================================================
##-- This source file is free software; you can redistribute it and/or modify it
##-- under the terms of the GNU Lesser General Public License as published by the
##-- Free Software Foundation; either version 2.1 of the License, or (at your
##-- option) any later version. This source is distributed in the hope that it
##-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
##-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
##-- See the GNU Lesser General Public License for more details. You should have
##-- received a copy of the GNU Lesser General Public License along with this
##-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
##--==============================================================================
##-- last changes:
##-- 2013-04-26 Theodor Stana t.stana@cern.ch File modified
##--==============================================================================
##-- TODO: -
##--==============================================================================
##-----------------------------------------------------------------------------
##-- Default attributes
##--
##-- IOSTANDARD = "LVCMOS25"
##-- SLEW = "SLOW"
##-- DRIVE = "12"
##-----------------------------------------------------------------------------
#NET "rst_i" LOC = N20;
#NET "rst_i" IOSTANDARD = "LVCMOS33";
#NET "fpga_sysreset_n_i" LOC = L20;
NET "mr_n_o" LOC = T22;
NET "mr_n_o" IOSTANDARD = LVCMOS33;
NET "clk20_vcxo_i" LOC = E16;
NET "clk20_vcxo_i" TNM_NET=clk20_vcxo_i;
TIMESPEC TSCLK20 = PERIOD "clk20_vcxo_i" 20 MHz HIGH 50 %;
NET "fpga_clk_p_i" LOC = H12;
NET "fpga_clk_n_i" LOC = G11;
NET "fpga_clk_p_i" TNM_NET = "clk125";
TIMESPEC TSCLK125 = PERIOD "clk125" 125 MHz HIGH 50%;
##=============================================================================
##-- FRONT PANEL TTLs
##=============================================================================
##-----------------------------------------------------------------------------
##-- Status LEDs
##-----------------------------------------------------------------------------
NET "led_ctrl0_o" LOC = M18;
NET "led_ctrl0_o" IOSTANDARD = LVCMOS33;
NET "led_ctrl0_oen_o" LOC = T20;
NET "led_ctrl0_oen_o" IOSTANDARD = LVCMOS33;
NET "led_ctrl1_o" LOC = M17;
NET "led_ctrl1_o" IOSTANDARD = LVCMOS33;
NET "led_ctrl1_oen_o" LOC = U19;
NET "led_ctrl1_oen_o" IOSTANDARD = LVCMOS33;
NET "led_multicast_2_0_o" LOC = P16;
NET "led_multicast_2_0_o" IOSTANDARD = LVCMOS33;
NET "led_multicast_3_1_o" LOC = P17;
NET "led_multicast_3_1_o" IOSTANDARD = LVCMOS33;
NET "led_wr_gmt_ttl_ttln_o" LOC = N16;
NET "led_wr_gmt_ttl_ttln_o" IOSTANDARD = LVCMOS33;
NET "led_wr_link_syserror_o" LOC = R15;
NET "led_wr_link_syserror_o" IOSTANDARD = LVCMOS33;
NET "led_wr_ok_syspw_o" LOC = R16;
NET "led_wr_ok_syspw_o" IOSTANDARD = LVCMOS33;
NET "led_wr_ownaddr_i2c_o" LOC = N15;
NET "led_wr_ownaddr_i2c_o" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- Front channel LEDs
##-----------------------------------------------------------------------------
NET "pulse_front_led_n_o[1]" LOC = H5;
NET "pulse_front_led_n_o[1]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[1]" DRIVE = 4;
NET "pulse_front_led_n_o[1]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[2]" LOC = J6;
NET "pulse_front_led_n_o[2]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[2]" DRIVE = 4;
NET "pulse_front_led_n_o[2]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[3]" LOC = K6;
NET "pulse_front_led_n_o[3]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[3]" DRIVE = 4;
NET "pulse_front_led_n_o[3]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[4]" LOC = K5;
NET "pulse_front_led_n_o[4]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[4]" DRIVE = 4;
NET "pulse_front_led_n_o[4]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[5]" LOC = M7;
NET "pulse_front_led_n_o[5]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[5]" DRIVE = 4;
NET "pulse_front_led_n_o[5]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[6]" LOC = M6;
NET "pulse_front_led_n_o[6]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[6]" DRIVE = 4;
NET "pulse_front_led_n_o[6]" SLEW = QUIETIO;
##-----------------------------------------------------------------------------
##-- Rear LEDs
##-----------------------------------------------------------------------------
NET "pulse_rear_led_n_o[1]" LOC = AB17;
NET "pulse_rear_led_n_o[1]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[1]" DRIVE = 4;
NET "pulse_rear_led_n_o[1]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[2]" LOC = AB19;
NET "pulse_rear_led_n_o[2]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[2]" DRIVE = 4;
NET "pulse_rear_led_n_o[2]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[3]" LOC = AA16;
NET "pulse_rear_led_n_o[3]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[3]" DRIVE = 4;
NET "pulse_rear_led_n_o[3]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[4]" LOC = AA18;
NET "pulse_rear_led_n_o[4]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[4]" DRIVE = 4;
NET "pulse_rear_led_n_o[4]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[5]" LOC = AB16;
NET "pulse_rear_led_n_o[5]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[5]" DRIVE = 4;
NET "pulse_rear_led_n_o[5]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[6]" LOC = AB18;
NET "pulse_rear_led_n_o[6]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[6]" DRIVE = 4;
NET "pulse_rear_led_n_o[6]" SLEW = QUIETIO;
##-----------------------------------------------------------------------------
##-- TTL trigger I/O
##-----------------------------------------------------------------------------
NET "fpga_input_ttl_n_i[1]" LOC = T2;
NET "fpga_input_ttl_n_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[1]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[2]" LOC = U3;
NET "fpga_input_ttl_n_i[2]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[2]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[3]" LOC = V5;
NET "fpga_input_ttl_n_i[3]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[3]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[4]" LOC = W4;
NET "fpga_input_ttl_n_i[4]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[4]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[5]" LOC = T6;
NET "fpga_input_ttl_n_i[5]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[5]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[6]" LOC = T3;
NET "fpga_input_ttl_n_i[6]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[6]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_out_ttl_o[1]" LOC = C1;
NET "fpga_out_ttl_o[1]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[2]" LOC = F2;
NET "fpga_out_ttl_o[2]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[3]" LOC = F5;
NET "fpga_out_ttl_o[3]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[4]" LOC = H4;
NET "fpga_out_ttl_o[4]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[5]" LOC = J4;
NET "fpga_out_ttl_o[5]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[6]" LOC = H2;
NET "fpga_out_ttl_o[6]" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- Inverted TTL I/O
##-----------------------------------------------------------------------------
NET "inv_in_n_i[1]" LOC = V2;
NET "inv_in_n_i[1]" IOSTANDARD = LVCMOS33;
NET "inv_in_n_i[1]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "inv_in_n_i[2]" LOC = W3;
NET "inv_in_n_i[2]" IOSTANDARD = LVCMOS33;
NET "inv_in_n_i[2]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "inv_in_n_i[3]" LOC = Y2;
NET "inv_in_n_i[3]" IOSTANDARD = LVCMOS33;
NET "inv_in_n_i[3]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "inv_in_n_i[4]" LOC = AA2;
NET "inv_in_n_i[4]" IOSTANDARD = LVCMOS33;
NET "inv_in_n_i[4]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "inv_out_o[1]" LOC = J3;
NET "inv_out_o[1]" IOSTANDARD = LVCMOS33;
NET "inv_out_o[2]" LOC = L3;
NET "inv_out_o[2]" IOSTANDARD = LVCMOS33;
NET "inv_out_o[3]" LOC = M3;
NET "inv_out_o[3]" IOSTANDARD = LVCMOS33;
NET "inv_out_o[4]" LOC = P2;
NET "inv_out_o[4]" IOSTANDARD = LVCMOS33;
##=============================================================================
##-- RTM signals
##=============================================================================
##-----------------------------------------------------------------------------
##-- Blocking I/O
##-----------------------------------------------------------------------------
NET "fpga_blo_in_i[1]" LOC = Y9;
NET "fpga_blo_in_i[1]" IOSTANDARD = "LVCMOS33";
NET "fpga_blo_in_i[2]" LOC = AA10;
NET "fpga_blo_in_i[2]" IOSTANDARD = "LVCMOS33";
NET "fpga_blo_in_i[3]" LOC = W12;
NET "fpga_blo_in_i[3]" IOSTANDARD = "LVCMOS33";
NET "fpga_blo_in_i[4]" LOC = AA6;
NET "fpga_blo_in_i[4]" IOSTANDARD = "LVCMOS33";
NET "fpga_blo_in_i[5]" LOC = Y7;
NET "fpga_blo_in_i[5]" IOSTANDARD = "LVCMOS33";
NET "fpga_blo_in_i[6]" LOC = AA8;
NET "fpga_blo_in_i[6]" IOSTANDARD = "LVCMOS33";
NET "fpga_trig_blo_o[1]" LOC = W9;
NET "fpga_trig_blo_o[1]" IOSTANDARD = "LVCMOS33";
NET "fpga_trig_blo_o[2]" LOC = T10;
NET "fpga_trig_blo_o[2]" IOSTANDARD = "LVCMOS33";
NET "fpga_trig_blo_o[3]" LOC = V7;
NET "fpga_trig_blo_o[3]" IOSTANDARD = "LVCMOS33";
NET "fpga_trig_blo_o[4]" LOC = U9;
NET "fpga_trig_blo_o[4]" IOSTANDARD = "LVCMOS33";
NET "fpga_trig_blo_o[5]" LOC = T8;
NET "fpga_trig_blo_o[5]" IOSTANDARD = "LVCMOS33";
NET "fpga_trig_blo_o[6]" LOC = R9;
NET "fpga_trig_blo_o[6]" IOSTANDARD = "LVCMOS33";
##=============================================================================
##-- VME CONNECTOR SIGNALS
##=============================================================================
##-----------------------------------------------------------------------------
##-- I2C lines
##-----------------------------------------------------------------------------
NET "scl_i" LOC = F19;
NET "scl_i" IOSTANDARD = LVCMOS33;
NET "scl_o" LOC = E20;
NET "scl_o" IOSTANDARD = LVCMOS33;
NET "scl_o" DRIVE = 4;
NET "scl_oe_o" LOC = H18;
NET "scl_oe_o" IOSTANDARD = LVCMOS33;
NET "scl_oe_o" DRIVE = 4;
# NET "scl_oe_o" PULLDOWN;
NET "sda_i" LOC = G20;
NET "sda_i" IOSTANDARD = LVCMOS33;
NET "sda_o" LOC = F20;
NET "sda_o" IOSTANDARD = LVCMOS33;
NET "sda_o" SLEW = FAST;
NET "sda_o" DRIVE = 4;
# NET "sda_o" PULLUP;
NET "sda_oe_o" LOC = J19;
NET "sda_oe_o" IOSTANDARD = LVCMOS33;
NET "sda_oe_o" SLEW = FAST;
NET "sda_oe_o" DRIVE = 4;
# NET "sda_oe_o" PULLDOWN;
##-----------------------------------------------------------------------------
##-- Geographical Address
##-----------------------------------------------------------------------------
NET "fpga_ga_i[0]" LOC = H20;
NET "fpga_ga_i[0]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[1]" LOC = J20;
NET "fpga_ga_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[2]" LOC = K19;
NET "fpga_ga_i[2]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[3]" LOC = K20;
NET "fpga_ga_i[3]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[4]" LOC = L19;
NET "fpga_ga_i[4]" IOSTANDARD = LVCMOS33;
NET "fpga_gap_i" LOC = H19;
NET "fpga_gap_i" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- ROM memory
##-----------------------------------------------------------------------------
NET "fpga_prom_cclk_o" LOC = Y20;
NET "fpga_prom_cclk_o" IOSTANDARD = "LVCMOS33";
NET "fpga_prom_cso_b_n_o" LOC = AA3;
NET "fpga_prom_cso_b_n_o" IOSTANDARD = "LVCMOS33";
NET "fpga_prom_miso_i" LOC = AA20;
NET "fpga_prom_miso_i" IOSTANDARD = "LVCMOS33";
NET "fpga_prom_mosi_o" LOC = AB20;
NET "fpga_prom_mosi_o" IOSTANDARD = "LVCMOS33";
##=============================================================================
##-- WHITE RABBIT
##=============================================================================
##-----------------------------------------------------------------------------
##-- Thermo for UID
##-----------------------------------------------------------------------------
NET "thermometer_b" LOC = B1;
NET "thermometer_b" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- DAC control
##-----------------------------------------------------------------------------
NET "fpga_plldac1_din_o" LOC = AB14;
NET "fpga_plldac1_din_o" IOSTANDARD = LVCMOS33;
NET "fpga_plldac1_sclk_o" LOC = AA14;
NET "fpga_plldac1_sclk_o" IOSTANDARD = LVCMOS33;
NET "fpga_plldac1_sync_n_o" LOC = AB15;
NET "fpga_plldac1_sync_n_o" IOSTANDARD = LVCMOS33;
NET "fpga_plldac2_din_o" LOC = W14;
NET "fpga_plldac2_din_o" IOSTANDARD = LVCMOS33;
NET "fpga_plldac2_sclk_o" LOC = Y14;
NET "fpga_plldac2_sclk_o" IOSTANDARD = LVCMOS33;
NET "fpga_plldac2_sync_n_o" LOC = W13;
NET "fpga_plldac2_sync_n_o" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- SFP connection
##-----------------------------------------------------------------------------
NET "fpga_sfp_los_i" LOC = G3;
NET "fpga_sfp_los_i" IOSTANDARD = "LVCMOS33";
NET "fpga_sfp_mod_def0_i" LOC = K8;
NET "fpga_sfp_mod_def0_i" IOSTANDARD = "LVCMOS33";
NET "fpga_sfp_rate_select_o" LOC = C4;
NET "fpga_sfp_rate_select_o" IOSTANDARD = "LVCMOS33";
NET "fpga_sfp_mod_def1_b" LOC = G4;
NET "fpga_sfp_mod_def1_b" IOSTANDARD = LVCMOS33;
NET "fpga_sfp_mod_def2_b" LOC = F3;
NET "fpga_sfp_mod_def2_b" IOSTANDARD = LVCMOS33;
NET "fpga_sfp_tx_disable_o" LOC = E4;
NET "fpga_sfp_tx_disable_o" IOSTANDARD = "LVCMOS33";
NET "fpga_sfp_tx_fault_i" LOC = D2;
NET "fpga_sfp_tx_fault_i" IOSTANDARD = "LVCMOS33";
###-----------------------------------------------------------------------------
###-- FPGA MGT lines
###-----------------------------------------------------------------------------
#NET "fpga_mgt_clk0_p_i" LOC = A10;
#NET "fpga_mgt_clk0_n_i" LOC = B10;
#
#NET "mgt_sfp_rx0_p_i" LOC = D7;
#NET "mgt_sfp_rx0_n_i" LOC = C7;
#
#NET "mgt_sfp_tx0_p_o" LOC = B6;
#NET "mgt_sfp_tx0_n_o" LOC = A6;
###=============================================================================
###-- ADDITIONAL PINS
###=============================================================================
NET "fpga_oe_o" LOC = R3;
NET "fpga_oe_o" IOSTANDARD = LVCMOS33;
NET "fpga_oe_o" DRIVE = 4;
NET "fpga_oe_o" SLEW = QUIETIO;
NET "fpga_blo_oe_o" LOC = P5;
NET "fpga_blo_oe_o" IOSTANDARD = LVCMOS33;
NET "fpga_blo_oe_o" DRIVE = 4;
NET "fpga_blo_oe_o" SLEW = QUIETIO;
NET "fpga_trig_ttl_oe_o" LOC = N3;
NET "fpga_trig_ttl_oe_o" IOSTANDARD = LVCMOS33;
NET "fpga_trig_ttl_oe_o" DRIVE = 4;
NET "fpga_trig_ttl_oe_o" SLEW = QUIETIO;
NET "fpga_inv_oe_o" LOC = P6;
NET "fpga_inv_oe_o" IOSTANDARD = LVCMOS33;
NET "fpga_inv_oe_o" DRIVE = 4;
NET "fpga_inv_oe_o" SLEW = QUIETIO;
##-----------------------------------------------------------------------------
##-- Configuration Switches
##-----------------------------------------------------------------------------
NET "extra_switch_n_i[1]" LOC = F22;
NET "extra_switch_n_i[1]" IOSTANDARD = "LVCMOS33";
NET "extra_switch_n_i[2]" LOC = G22;
NET "extra_switch_n_i[2]" IOSTANDARD = "LVCMOS33";
NET "extra_switch_n_i[3]" LOC = H21;
NET "extra_switch_n_i[3]" IOSTANDARD = "LVCMOS33";
NET "extra_switch_n_i[4]" LOC = H22;
NET "extra_switch_n_i[4]" IOSTANDARD = "LVCMOS33";
NET "extra_switch_n_i[5]" LOC = J22;
NET "extra_switch_n_i[5]" IOSTANDARD = "LVCMOS33";
NET "extra_switch_n_i[6]" LOC = K21;
NET "extra_switch_n_i[6]" IOSTANDARD = "LVCMOS33";
NET "extra_switch_n_i[7]" LOC = K22;
NET "extra_switch_n_i[7]" IOSTANDARD = "LVCMOS33";
NET "ttl_switch_n_i" LOC = L22;
NET "ttl_switch_n_i" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- Motherboard and piggyback IDs
##-----------------------------------------------------------------------------
# NET "fpga_rtmm_n_i[0]" LOC = V21;
# NET "fpga_rtmm_n_i[0]" IOSTANDARD = LVCMOS33;
# NET "fpga_rtmm_n_i[1]" LOC = V22;
# NET "fpga_rtmm_n_i[1]" IOSTANDARD = LVCMOS33;
# NET "fpga_rtmm_n_i[2]" LOC = U22;
# NET "fpga_rtmm_n_i[2]" IOSTANDARD = LVCMOS33;
# NET "fpga_rtmp_n_i[0]" LOC = W22;
# NET "fpga_rtmp_n_i[0]" IOSTANDARD = LVCMOS33;
# NET "fpga_rtmp_n_i[1]" LOC = Y22;
# NET "fpga_rtmp_n_i[1]" IOSTANDARD = LVCMOS33;
# NET "fpga_rtmp_n_i[2]" LOC = Y21;
# NET "fpga_rtmp_n_i[2]" IOSTANDARD = LVCMOS33;
###-----------------------------------------------------------------------------
###-- General purpose
###-----------------------------------------------------------------------------
# NET "fpga_header_out_n_o[1]" LOC = F15;
# NET "fpga_header_out_n_o[1]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[2]" LOC = F16;
# NET "fpga_header_out_n_o[2]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[3]" LOC = F17;
# NET "fpga_header_out_n_o[3]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[4]" LOC = F14;
# NET "fpga_header_out_n_o[4]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[5]" LOC = H14;
# NET "fpga_header_out_n_o[5]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[6]" LOC = H13;
# NET "fpga_header_out_n_o[6]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[1]" LOC = A17;
# NET "fpga_header_in_n_i[1]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[2]" LOC = A18;
# NET "fpga_header_in_n_i[2]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[3]" LOC = B18;
# NET "fpga_header_in_n_i[3]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[4]" LOC = A19;
# NET "fpga_header_in_n_i[4]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[5]" LOC = A20;
# NET "fpga_header_in_n_i[5]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[6]" LOC = B20;
# NET "fpga_header_in_n_i[6]" IOSTANDARD = "LVCMOS33";
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/top/pulsetest/pulsetest.vhd 0000664 0000000 0000000 00000130023 12314554267 0027521 0 ustar 00root root 0000000 0000000 --==============================================================================
-- CERN (BE-CO-HT)
-- Long-term pulse test for CONV-TTL-* boards
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- version: 1.0
--
-- description:
-- This is the top-level file for the long-term pulse repetition test for TTL
-- pulse converter boards. All the top-level logic generation and component
-- instantiation is done here.
--
-- A general-purpose pulse generator component (pulse_gen_gp) is used to
-- generate the output pulses on the converter board output channels. One
-- such pulse generator is instantiated per channel and external logic is
-- used to adapt these pulses for TTL or TTL-BAR signals.
--
-- The characteristics of pulses generated by the generators can be
-- controlled by means of registers accessible over the I2C bus on the
-- VME backplanes. To access the registers, the protocol defined together
-- with ELMA [2] is used and the wb_i2c_bridge component handles translating
-- this protocol into the Wishbone protocol, which is then used to access
-- the registers controlling the pulse generators.
--
-- An example test script can be used to run the long-term pulse repetition
-- test. The test script can be found in the software/pulsetest/ folder in
-- the conv-ttl-blo repository [3]. More information on what the script does
-- can be found on the CONV-TTL-BLO Testing webpage [4].
--
-- dependencies:
-- general-cores repository [1]
--
-- references:
-- [1] Platform-independent core collection webpage on OHWR,
-- http://www.ohwr.org/projects/general-cores/repository
-- [2] ELMA, Access to board data using SNMP and I2C
-- http://www.ohwr.org/documents/227
-- [3] CONV-TTL-BLO project repository on OHWR,
-- http://www.ohwr.org/projects/conv-ttl-blo/repository
-- [4] CONV-TTL-BLO Test page on OHWR,
-- http://www.ohwr.org/projects/conv-ttl-blo/wiki/Testing
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 26-11-2013 Theodor Stana Changed file header
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
library unisim;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use unisim.vcomponents.all;
use work.bicolor_led_ctrl_pkg.all;
use work.wishbone_pkg.all;
use work.gencores_pkg.all;
use work.genram_pkg.all;
entity pulsetest is
generic
(
g_nr_ttl_chan : natural := 6;
g_nr_inv_chan : natural := 4
);
port
(
-- Clocks
-- 20 MHz from VCXO
clk20_vcxo_i : in std_logic;
-- 125 MHz from clock generator
fpga_clk_p_i : in std_logic;
fpga_clk_n_i : in std_logic;
-- LEDs
led_ctrl0_o : out std_logic;
led_ctrl0_oen_o : out std_logic;
led_ctrl1_o : out std_logic;
led_ctrl1_oen_o : out std_logic;
led_multicast_2_0_o : out std_logic;
led_multicast_3_1_o : out std_logic;
led_wr_gmt_ttl_ttln_o : out std_logic;
led_wr_link_syserror_o : out std_logic;
led_wr_ok_syspw_o : out std_logic;
led_wr_ownaddr_i2c_o : out std_logic;
-- I/Os for pulses
pulse_front_led_n_o : out std_logic_vector(g_nr_ttl_chan downto 1);
pulse_rear_led_n_o : out std_logic_vector(g_nr_ttl_chan downto 1);
fpga_input_ttl_n_i : in std_logic_vector(g_nr_ttl_chan downto 1);
fpga_out_ttl_o : out std_logic_vector(g_nr_ttl_chan downto 1);
fpga_blo_in_i : in std_logic_vector(g_nr_ttl_chan downto 1);
fpga_trig_blo_o : out std_logic_vector(g_nr_ttl_chan downto 1);
inv_in_n_i : in std_logic_vector(g_nr_inv_chan downto 1);
inv_out_o : out std_logic_vector(g_nr_inv_chan downto 1);
-- Output enable lines
fpga_oe_o : out std_logic;
fpga_blo_oe_o : out std_logic;
fpga_trig_ttl_oe_o : out std_logic;
fpga_inv_oe_o : out std_logic;
--TTL/INV_TTL_N
ttl_switch_n_i : in std_logic;
extra_switch_n_i : in std_logic_vector(7 downto 1);
-- Lines for the i2c_slave
scl_i : in std_logic;
scl_o : out std_logic;
scl_oe_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
sda_oe_o : out std_logic;
fpga_ga_i : in std_logic_vector(4 downto 0);
fpga_gap_i : in std_logic;
-- Flash memory lines
fpga_prom_cclk_o : out std_logic;
fpga_prom_cso_b_n_o : out std_logic;
fpga_prom_mosi_o : out std_logic;
fpga_prom_miso_i : in std_logic;
-- Blocking power supply reset line
mr_n_o : out std_logic;
-- Thermometer line
thermometer_b : inout std_logic;
-- PLL DACs
-- DAC1: 20 MHz VCXO control
fpga_plldac1_din_o : out std_logic;
fpga_plldac1_sclk_o : out std_logic;
fpga_plldac1_sync_n_o : out std_logic;
-- DAC2: 125 MHz clock generator control
fpga_plldac2_din_o : out std_logic;
fpga_plldac2_sclk_o : out std_logic;
fpga_plldac2_sync_n_o : out std_logic;
-- SFP lines
fpga_sfp_los_i : in std_logic;
fpga_sfp_mod_def0_i : in std_logic;
fpga_sfp_rate_select_o : out std_logic;
fpga_sfp_mod_def1_b : inout std_logic;
fpga_sfp_mod_def2_b : inout std_logic;
fpga_sfp_tx_disable_o : out std_logic;
fpga_sfp_tx_fault_i : in std_logic;
-- RTM identifiers, should match with the expected values
fpga_rtmm_n_i : in std_logic_vector(2 downto 0);
fpga_rtmp_n_i : in std_logic_vector(2 downto 0)
);
end pulsetest;
architecture behav of pulsetest is
--============================================================================
-- Type declarations
--============================================================================
type t_pulse_counter is array(1 to g_nr_ttl_chan) of unsigned(31 downto 0);
type t_pulse_led_cnt is array (1 to g_nr_ttl_chan) of unsigned(18 downto 0);
type t_pgen_ctrl_reg is array (1 to 6) of std_logic_vector(31 downto 0);
--============================================================================
-- Constant declarations
--============================================================================
-- Board ID - ASCII string "TBLO"
constant c_board_id : std_logic_vector(31 downto 0) := x"54424c4f";
-- Firmware version
-- - format: M.m
-- - M: major version hex number (e.g. 1)
-- - m: minor version hex number (e.g. 13)
-- - example: first major release v1.0 c_fwvers = x"10";
-- next minor release v1.1 c_fwvers = x"11";
-- 13 minor releases later v1.12 c_fwvers = x"1e";
-- next major release v2.0 c_fwvers = x"20";
-- Test firmware gets numbered from v9.9 downward
-- The pulse test firmware is v9.9
constant c_fwvers : std_logic_vector(7 downto 0) := x"ff";
-- Number of Wishbone masters and slaves, for wb_crossbar
constant c_nr_masters : natural := 1;
constant c_nr_slaves : natural := 4;
-----------------------------------------
-- Memory map
-- * all registers are word-addressable
-- * all registers are word-aligned
-----------------------------------------
-- CONV_REGS [0x000-0x004]
-- PULSE_CNT [0x100-0x13F]
-- PGEN_CTRL [0x200-0x24F]
-- MULTIBOOT [0x300-0x31F]
-----------------------------------------
-- slave order definitions
constant c_slv_conv_regs : natural := 0;
constant c_slv_pulse_cnt : natural := 1;
constant c_slv_pgen_ctrl : natural := 2;
constant c_slv_multiboot : natural := 3;
-- base address definitions
constant c_addr_conv_regs : t_wishbone_address := x"00000000";
constant c_addr_pulse_cnt : t_wishbone_address := x"00000100";
constant c_addr_pgen_ctrl : t_wishbone_address := x"00000200";
constant c_addr_multiboot : t_wishbone_address := x"00000300";
-- address mask definitions
constant c_mask_conv_regs : t_wishbone_address := x"00000F00";
constant c_mask_pulse_cnt : t_wishbone_address := x"00000F00";
constant c_mask_pgen_ctrl : t_wishbone_address := x"00000F00";
constant c_mask_multiboot : t_wishbone_address := x"00000F00";
-- addresses constant for Wishbone crossbar
constant c_addresses : t_wishbone_address_array(c_nr_slaves-1 downto 0)
:= (
c_slv_conv_regs => c_addr_conv_regs,
c_slv_pulse_cnt => c_addr_pulse_cnt,
c_slv_pgen_ctrl => c_addr_pgen_ctrl,
c_slv_multiboot => c_addr_multiboot
);
-- masks constant for Wishbone crossbar
constant c_masks : t_wishbone_address_array(c_nr_slaves-1 downto 0)
:= (
c_slv_conv_regs => c_mask_conv_regs,
c_slv_pulse_cnt => c_mask_pulse_cnt,
c_slv_pgen_ctrl => c_mask_pgen_ctrl,
c_slv_multiboot => c_addr_multiboot
);
--============================================================================
-- Component declarations
--============================================================================
-- Reset generator component
-- (use: global reset generation, output reset generation)
component reset_gen is
generic
(
-- Reset time in number of clk_i cycles
g_reset_time : positive := 2_000_000
);
port
(
clk_i : in std_logic;
rst_i : in std_logic;
rst_n_o : out std_logic
);
end component reset_gen;
-- Converter registers
-- (use: ID, firmware version)
component conv_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'bits' in reg: 'Board ID Register'
reg_id_bits_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'fwvers' in reg: 'Status Register'
reg_sr_fwvers_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'switches' in reg: 'Status Register'
reg_sr_switches_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'RTM detection' in reg: 'Status Register'
reg_sr_rtm_i : in std_logic_vector(5 downto 0);
-- Ports for BIT field: 'I2C Watchdog Timeout' in reg: 'Status Register'
reg_sr_i2c_wdto_o : out std_logic;
reg_sr_i2c_wdto_i : in std_logic;
reg_sr_i2c_wdto_load_o : out std_logic;
-- Port for BIT field: 'Reset unlock bit' in reg: 'Control Register'
reg_cr_rst_unlock_o : out std_logic;
reg_cr_rst_unlock_i : in std_logic;
reg_cr_rst_unlock_load_o : out std_logic;
-- Ports for BIT field: 'Reset bit' in reg: 'Control Register'
reg_cr_rst_o : out std_logic;
reg_cr_rst_i : in std_logic;
reg_cr_rst_load_o : out std_logic
);
end component conv_regs;
-- General-purpose pulse generator component
-- (usage: generate pulses on each channel output)
component pulse_gen_gp is
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
en_i : in std_logic;
delay_i : in std_logic_vector(31 downto 0);
pwidth_i : in std_logic_vector(31 downto 0);
freq_i : in std_logic_vector(31 downto 0);
pulse_o : out std_logic
);
end component pulse_gen_gp;
-- Pulse generator control registers component
-- (usage: contains bits and values to control the pulse_gen_gp component)
component pgen_ctrl_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'channel enable' in reg: 'Enable register'
pgen_ctrl_regs_en_ch_o : out std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH1 delay register'
pgen_ctrl_regs_ch1_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH2 delay register'
pgen_ctrl_regs_ch2_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH3 delay register'
pgen_ctrl_regs_ch3_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH4 delay register'
pgen_ctrl_regs_ch4_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH5 delay register'
pgen_ctrl_regs_ch5_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH6 delay register'
pgen_ctrl_regs_ch6_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH1 pulse width register'
pgen_ctrl_regs_ch1_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH2 pulse width register'
pgen_ctrl_regs_ch2_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH3 pulse width register'
pgen_ctrl_regs_ch3_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH4 pulse width register'
pgen_ctrl_regs_ch4_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH5 pulse width register'
pgen_ctrl_regs_ch5_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH6 pulse width register'
pgen_ctrl_regs_ch6_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH1 frequency register'
pgen_ctrl_regs_ch1_freq_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH2 frequency register'
pgen_ctrl_regs_ch2_freq_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH3 frequency register'
pgen_ctrl_regs_ch3_freq_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH4 frequency register'
pgen_ctrl_regs_ch4_freq_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH5 frequency register'
pgen_ctrl_regs_ch5_freq_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH6 frequency register'
pgen_ctrl_regs_ch6_freq_bits_o : out std_logic_vector(31 downto 0)
);
end component pgen_ctrl_regs;
-- Pulse counter registers component
-- (usage: store values of pulse counters)
component pulse_cnt_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH1 input'
pulse_cnt_ch1i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH1 output'
pulse_cnt_ch1o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH2 input'
pulse_cnt_ch2i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH2 output'
pulse_cnt_ch2o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH3 input'
pulse_cnt_ch3i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH3 output'
pulse_cnt_ch3o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH4 input'
pulse_cnt_ch4i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH4 output'
pulse_cnt_ch4o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH5 input'
pulse_cnt_ch5i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH5 output'
pulse_cnt_ch5o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH6 input'
pulse_cnt_ch6i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH6 output'
pulse_cnt_ch6o_val_i : in std_logic_vector(31 downto 0);
-- Port for BIT field: 'reset' in reg: 'Counter reset'
pulse_cnt_rst_bit_o : out std_logic
);
end component pulse_cnt_regs;
-- MultiBoot component
-- use: remotely reprogram the FPGA
component wb_xil_multiboot is
port
(
-- Clock and reset input ports
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone ports
wbs_i : in t_wishbone_slave_in;
wbs_o : out t_wishbone_slave_out;
-- SPI ports
spi_cs_n_o : out std_logic;
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic
);
end component wb_xil_multiboot;
-- RTM detector component
-- (use: detect the presence of an RTM/P module)
component rtm_detector is
port
(
rtmm_i : in std_logic_vector(2 downto 0);
rtmp_i : in std_logic_vector(2 downto 0);
rtmm_ok_o : out std_logic;
rtmp_ok_o : out std_logic
);
end component rtm_detector;
--============================================================================
-- Signal declarations
--============================================================================
-- Reset signals
signal rst_n : std_logic;
signal rst_unlock : std_logic;
signal rst_unlock_bit : std_logic;
signal rst_unlock_bit_ld : std_logic;
signal rst_bit : std_logic;
signal rst_bit_ld : std_logic;
signal rst_fr_reg : std_logic;
-- RTM detection signals
signal rtmm, rtmp : std_logic_vector(2 downto 0);
signal rtmm_ok, rtmp_ok : std_logic;
-- Wishbone crossbar signals
signal xbar_slave_in : t_wishbone_slave_in_array (c_nr_masters - 1 downto 0);
signal xbar_slave_out : t_wishbone_slave_out_array (c_nr_masters - 1 downto 0);
signal xbar_master_in : t_wishbone_master_in_array (c_nr_slaves - 1 downto 0);
signal xbar_master_out : t_wishbone_master_out_array(c_nr_slaves - 1 downto 0);
-- Signals to/from converter system registers component
signal rtm_lines : std_logic_vector(5 downto 0);
signal switches_n : std_logic_vector(7 downto 0);
signal wdto_bit : std_logic;
signal wdto_bit_rst : std_logic;
signal wdto_bit_rst_ld : std_logic;
-- Signal for controlling the bicolor LED matrix
signal bicolor_led_state : std_logic_vector(23 downto 0);
-- VBCP bridge signals
signal i2c_tip : std_logic;
signal i2c_err_p : std_logic;
signal i2c_wdto_p : std_logic;
signal i2c_addr : std_logic_vector(6 downto 0);
signal led_i2c : std_logic;
signal led_i2c_clkdiv : unsigned(18 downto 0);
signal led_i2c_cnt : unsigned( 2 downto 0);
signal led_i2c_blink : std_logic;
signal led_i2c_err : std_logic;
-- Pulse enable signals
signal oe, ttl_oe : std_logic;
signal blo_oe, inv_oe : std_logic;
signal ch_en : std_logic_vector(g_nr_ttl_chan downto 1);
-- Pulse generation signals
signal trig_ttl_a : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_blo_a : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_a : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_synced : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_synced_edge : std_logic_vector(g_nr_ttl_chan downto 1);
signal pulse, pulse_d0 : std_logic_vector(g_nr_ttl_chan downto 1);
signal pulse_r_edge_p : std_logic_vector(g_nr_ttl_chan downto 1);
-- Pulse LED signals
signal pulse_leds : std_logic_vector(g_nr_ttl_chan downto 1);
signal pulse_led_cnt : t_pulse_led_cnt;
-- Pulse generator and counter register signals
signal cnt_in, cnt_out : t_pulse_counter;
signal cntrst : std_logic;
signal delay_reg : t_pgen_ctrl_reg;
signal pwidth_reg : t_pgen_ctrl_reg;
signal freq_reg : t_pgen_ctrl_reg;
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Internal and external reset generation
--============================================================================
-- Configure reset generator for 96ms power-on reset
cmp_reset_gen : reset_gen
generic map
(
-- Reset time: 50ns * 2 * (10**6) = 100 ms
g_reset_time => 2*(10**6)
)
port map
(
clk_i => clk20_vcxo_i,
rst_i => rst_fr_reg,
rst_n_o => rst_n
);
mr_n_o <= rst_n;
--============================================================================
-- I2C bridge logic
--============================================================================
-- Set the I2C address signal according to ELMA protocol [1]
i2c_addr <= "10" & fpga_ga_i;
-- Instantiate VBCP bridge component
cmp_i2c_bridge : wb_i2c_bridge
port map
(
-- Clock, reset
clk_i => clk20_vcxo_i,
rst_n_i => rst_n,
-- I2C lines
scl_i => scl_i,
scl_o => scl_o,
scl_en_o => scl_oe_o,
sda_i => sda_i,
sda_o => sda_o,
sda_en_o => sda_oe_o,
-- I2C address and status
i2c_addr_i => i2c_addr,
tip_o => i2c_tip,
err_p_o => i2c_err_p,
wdto_p_o => i2c_wdto_p,
-- Wishbone master signals
wbm_stb_o => xbar_slave_in(0).stb,
wbm_cyc_o => xbar_slave_in(0).cyc,
wbm_sel_o => xbar_slave_in(0).sel,
wbm_we_o => xbar_slave_in(0).we,
wbm_dat_i => xbar_slave_out(0).dat,
wbm_dat_o => xbar_slave_in(0).dat,
wbm_adr_o => xbar_slave_in(0).adr,
wbm_ack_i => xbar_slave_out(0).ack,
wbm_rty_i => xbar_slave_out(0).rty,
wbm_err_i => xbar_slave_out(0).err
);
-- Process to blink the LED when an I2C transfer is in progress
-- blinks four times per transfer
-- blink width : 20 ms
-- blink period: 40 ms
p_i2c_blink : process(clk20_vcxo_i)
begin
if rising_edge(clk20_vcxo_i) then
if (rst_n = '0') then
led_i2c_clkdiv <= (others => '0');
led_i2c_cnt <= (others => '0');
led_i2c <= '0';
led_i2c_blink <= '0';
else
case led_i2c_blink is
when '0' =>
led_i2c <= '0';
if (i2c_tip = '1') then
led_i2c_blink <= '1';
end if;
when '1' =>
led_i2c_clkdiv <= led_i2c_clkdiv + 1;
if (led_i2c_clkdiv = 399999) then
led_i2c_clkdiv <= (others => '0');
led_i2c_cnt <= led_i2c_cnt + 1;
led_i2c <= not led_i2c;
if (led_i2c_cnt = 7) then
led_i2c_cnt <= (others => '0');
led_i2c_blink <= '0';
end if;
end if;
when others =>
led_i2c_blink <= '0';
end case;
end if;
end if;
end process p_i2c_blink;
-- Process to set the I2C error LED signal for display on the front panel
-- of the front module. The I2C error signal is permanently set once an
-- error is detected from the bridge module.
p_i2c_err_led : process (clk20_vcxo_i) is
begin
if rising_edge(clk20_vcxo_i) then
if (rst_n = '0') then
led_i2c_err <= '0';
elsif (i2c_err_p = '1') then
led_i2c_err <= '1';
end if;
end if;
end process p_i2c_err_led;
-- Register for the WDTO bit in the SR, cleared by writing a '1'
p_sr_wdto_bit : process (clk20_vcxo_i)
begin
if rising_edge(clk20_vcxo_i) then
if (rst_n = '0') then
wdto_bit <= '0';
elsif (i2c_wdto_p = '1') then
wdto_bit <= '1';
elsif (wdto_bit_rst_ld = '1') and (wdto_bit_rst = '1') then
wdto_bit <= '0';
end if;
end if;
end process p_sr_wdto_bit;
--============================================================================
-- Instantiation and connection of the main Wishbone crossbar
--============================================================================
xbar_master_in(0).int <= '0';
xbar_master_in(0).err <= '0';
cmp_wb_crossbar : xwb_crossbar
generic map
(
g_num_masters => c_nr_masters,
g_num_slaves => c_nr_slaves,
g_registered => false,
g_address => c_addresses,
g_mask => c_masks
)
port map
(
clk_sys_i => clk20_vcxo_i,
rst_n_i => rst_n,
slave_i => xbar_slave_in,
slave_o => xbar_slave_out,
master_i => xbar_master_in,
master_o => xbar_master_out
);
--============================================================================
-- Converter board registers
--============================================================================
-- Set SWITCH and RTM fields
switches_n <= ttl_switch_n_i & extra_switch_n_i(7 downto 1);
rtm_lines <= rtmp & rtmm;
-- Then, instantiate the component
cmp_conv_regs : conv_regs
port map (
rst_n_i => rst_n,
clk_sys_i => clk20_vcxo_i,
wb_adr_i => xbar_master_out(c_slv_conv_regs).adr(3 downto 2),
wb_dat_i => xbar_master_out(c_slv_conv_regs).dat,
wb_dat_o => xbar_master_in (c_slv_conv_regs).dat,
wb_cyc_i => xbar_master_out(c_slv_conv_regs).cyc,
wb_sel_i => xbar_master_out(c_slv_conv_regs).sel,
wb_stb_i => xbar_master_out(c_slv_conv_regs).stb,
wb_we_i => xbar_master_out(c_slv_conv_regs).we,
wb_ack_o => xbar_master_in (c_slv_conv_regs).ack,
wb_stall_o => xbar_master_in (c_slv_conv_regs).stall,
reg_id_bits_i => c_board_id,
reg_sr_fwvers_i => c_fwvers,
reg_sr_switches_i => switches_n,
reg_sr_rtm_i => rtm_lines,
reg_sr_i2c_wdto_o => wdto_bit_rst,
reg_sr_i2c_wdto_i => wdto_bit,
reg_sr_i2c_wdto_load_o => wdto_bit_rst_ld,
reg_cr_rst_unlock_o => rst_unlock_bit,
reg_cr_rst_unlock_i => rst_unlock,
reg_cr_rst_unlock_load_o => rst_unlock_bit_ld,
reg_cr_rst_o => rst_bit,
reg_cr_rst_i => rst_fr_reg,
reg_cr_rst_load_o => rst_bit_ld
);
-- Implement the RST_UNLOCK bit
p_rst_unlock : process (clk20_vcxo_i)
begin
if rising_edge(clk20_vcxo_i) then
if (rst_n = '0') then
rst_unlock <= '0';
elsif (rst_unlock_bit_ld = '1') then
if (rst_unlock_bit = '1') then
rst_unlock <= '1';
else
rst_unlock <= '0';
end if;
end if;
end if;
end process p_rst_unlock;
-- And implement the reset bit register
p_rst_fr_reg : process (clk20_vcxo_i)
begin
if rising_edge(clk20_vcxo_i) then
if (rst_n = '0') then
rst_fr_reg <= '0';
elsif (rst_bit_ld = '1') and (rst_bit = '1') and (rst_unlock = '1') then
rst_fr_reg <= '1';
end if;
end if;
end process p_rst_fr_reg;
--============================================================================
-- Pulse generation control registers instantiation
--============================================================================
cmp_pulse_gen_ctrl_regs : pgen_ctrl_regs
port map
(
rst_n_i => rst_n,
clk_sys_i => clk20_vcxo_i,
wb_adr_i => xbar_master_out(c_slv_pgen_ctrl).adr(6 downto 2),
wb_dat_i => xbar_master_out(c_slv_pgen_ctrl).dat,
wb_dat_o => xbar_master_in(c_slv_pgen_ctrl).dat,
wb_cyc_i => xbar_master_out(c_slv_pgen_ctrl).cyc,
wb_sel_i => xbar_master_out(c_slv_pgen_ctrl).sel,
wb_stb_i => xbar_master_out(c_slv_pgen_ctrl).stb,
wb_we_i => xbar_master_out(c_slv_pgen_ctrl).we,
wb_ack_o => xbar_master_in(c_slv_pgen_ctrl).ack,
wb_stall_o => xbar_master_in(c_slv_pgen_ctrl).stall,
pgen_ctrl_regs_en_ch_o => ch_en,
pgen_ctrl_regs_ch1_delay_bits_o => delay_reg(1),
pgen_ctrl_regs_ch2_delay_bits_o => delay_reg(2),
pgen_ctrl_regs_ch3_delay_bits_o => delay_reg(3),
pgen_ctrl_regs_ch4_delay_bits_o => delay_reg(4),
pgen_ctrl_regs_ch5_delay_bits_o => delay_reg(5),
pgen_ctrl_regs_ch6_delay_bits_o => delay_reg(6),
pgen_ctrl_regs_ch1_pwidth_bits_o => pwidth_reg(1),
pgen_ctrl_regs_ch2_pwidth_bits_o => pwidth_reg(2),
pgen_ctrl_regs_ch3_pwidth_bits_o => pwidth_reg(3),
pgen_ctrl_regs_ch4_pwidth_bits_o => pwidth_reg(4),
pgen_ctrl_regs_ch5_pwidth_bits_o => pwidth_reg(5),
pgen_ctrl_regs_ch6_pwidth_bits_o => pwidth_reg(6),
pgen_ctrl_regs_ch1_freq_bits_o => freq_reg(1),
pgen_ctrl_regs_ch2_freq_bits_o => freq_reg(2),
pgen_ctrl_regs_ch3_freq_bits_o => freq_reg(3),
pgen_ctrl_regs_ch4_freq_bits_o => freq_reg(4),
pgen_ctrl_regs_ch5_freq_bits_o => freq_reg(5),
pgen_ctrl_regs_ch6_freq_bits_o => freq_reg(6)
);
--============================================================================
-- Output enable logic
--============================================================================
-- The general output enable is set first and the blocking, TTL
-- and INV output enable signals are set one clock cycle later.
p_oe : process(clk20_vcxo_i)
begin
if rising_edge(clk20_vcxo_i) then
if (rst_n = '0') then
oe <= '0';
blo_oe <= '0';
ttl_oe <= '0';
inv_oe <= '0';
else
oe <= '1';
if (oe = '1') then
blo_oe <= '1';
ttl_oe <= '1';
inv_oe <= '1';
end if;
end if;
end if;
end process p_oe;
fpga_oe_o <= oe;
fpga_blo_oe_o <= blo_oe;
fpga_trig_ttl_oe_o <= ttl_oe;
fpga_inv_oe_o <= inv_oe;
--============================================================================
-- Pulse generation logic
--============================================================================
-- First, the TTL trigger mux, selected via the TTL switch; ttlbar_nosig_n is
-- controlled in the process below
trig_ttl_a <= not fpga_input_ttl_n_i when (ttl_switch_n_i = '0') else
fpga_input_ttl_n_i;
-- Then, the blocking trigger
trig_blo_a <= fpga_blo_in_i;
-- And now the OR gate at the inputs of the pulse generator blocks
trig_a <= trig_ttl_a or trig_blo_a;
-----------------------------------------------------------------------------
-- Generate logic for each channel
-----------------------------------------------------------------------------
gen_chan_logic : for i in 1 to g_nr_ttl_chan generate
-- First, resync the trigger signal into clk20_vcxo_i domain
--
-- Reset value is '1' to avoid pulses being counted by pulse counter on
-- startup, when the board is in TTL-BAR repetition mode.
cmp_sync_ffs: gc_sync_ffs
port map
(
clk_i => clk20_vcxo_i,
rst_n_i => '1',
data_i => trig_a(i),
synced_o => trig_synced(i),
ppulse_o => trig_synced_edge(i)
);
-- Instantiate output pulse generators
cmp_pulse_gen : pulse_gen_gp
port map
(
clk_i => clk20_vcxo_i,
rst_n_i => rst_n,
en_i => ch_en(i),
delay_i => delay_reg(i),
pwidth_i => pwidth_reg(i),
freq_i => freq_reg(i),
pulse_o => pulse(i)
);
-- Delay reg for output pulses
p_delay_pulse : process (clk20_vcxo_i) is
begin
if rising_edge(clk20_vcxo_i) then
if (rst_n = '0') then
pulse_d0(i) <= '0';
pulse_r_edge_p(i) <= '0';
else
pulse_d0(i) <= pulse(i);
pulse_r_edge_p(i) <= pulse(i) and (not pulse_d0(i));
end if;
end if;
end process p_delay_pulse;
-- Pulse counting logic
p_cnt_pulses : process(clk20_vcxo_i) is
begin
if rising_edge(clk20_vcxo_i) then
if (rst_n = '0') or (cntrst = '1') then
cnt_in(i) <= (others => '0');
cnt_out(i) <= (others => '0');
else
if (pulse_r_edge_p(i) = '1') then
cnt_out(i) <= cnt_out(i) + 1;
end if;
if (trig_synced_edge(i) = '1') then
cnt_in(i) <= cnt_in(i) + 1;
end if;
end if;
end if;
end process p_cnt_pulses;
-- Process to flash pulse LED on pulse reception
-- LED flash length: 26 ms
p_pulse_led : process (clk20_vcxo_i, rst_n) is
begin
if rising_edge(clk20_vcxo_i) then
if (rst_n = '0') then
pulse_led_cnt(i) <= (others => '0');
pulse_leds(i) <= '0';
else
case pulse_leds(i) is
when '0' =>
if (pulse_r_edge_p(i) = '1') then
pulse_leds(i) <= '1';
end if;
when '1' =>
pulse_led_cnt(i) <= pulse_led_cnt(i) + 1;
if (pulse_led_cnt(i) = (pulse_led_cnt(i)'range => '1')) then
pulse_leds(i) <= '0';
end if;
when others =>
pulse_leds(i) <= '0';
end case;
end if;
end if;
end process;
-- Set the pulse status LED for the channel
pulse_front_led_n_o(i) <= (not pulse_leds(i)) when (ch_en(i) = '1') else '1';
pulse_rear_led_n_o(i) <= (not pulse_leds(i)) when (ch_en(i) = '1') else '1';
end generate gen_chan_logic;
-----------------------------------------------------------------------------
-- Pulse outputs assignment
fpga_out_ttl_o <= pulse when (ttl_switch_n_i = '0') else
not pulse;
fpga_trig_blo_o <= pulse; --(others => '0');
--============================================================================
-- Pulse counter registers instantiation
--============================================================================
cmp_pulse_cnt_regs : pulse_cnt_regs
port map
(
rst_n_i => rst_n,
clk_sys_i => clk20_vcxo_i,
wb_adr_i => xbar_master_out(c_slv_pulse_cnt).adr(5 downto 2),
wb_dat_i => xbar_master_out(c_slv_pulse_cnt).dat,
wb_dat_o => xbar_master_in(c_slv_pulse_cnt).dat,
wb_cyc_i => xbar_master_out(c_slv_pulse_cnt).cyc,
wb_sel_i => xbar_master_out(c_slv_pulse_cnt).sel,
wb_stb_i => xbar_master_out(c_slv_pulse_cnt).stb,
wb_we_i => xbar_master_out(c_slv_pulse_cnt).we,
wb_ack_o => xbar_master_in(c_slv_pulse_cnt).ack,
wb_stall_o => xbar_master_in(c_slv_pulse_cnt).stall,
pulse_cnt_ch1i_val_i => std_logic_vector(cnt_in(1)),
pulse_cnt_ch1o_val_i => std_logic_vector(cnt_out(1)),
pulse_cnt_ch2i_val_i => std_logic_vector(cnt_in(2)),
pulse_cnt_ch2o_val_i => std_logic_vector(cnt_out(2)),
pulse_cnt_ch3i_val_i => std_logic_vector(cnt_in(3)),
pulse_cnt_ch3o_val_i => std_logic_vector(cnt_out(3)),
pulse_cnt_ch4i_val_i => std_logic_vector(cnt_in(4)),
pulse_cnt_ch4o_val_i => std_logic_vector(cnt_out(4)),
pulse_cnt_ch5i_val_i => std_logic_vector(cnt_in(5)),
pulse_cnt_ch5o_val_i => std_logic_vector(cnt_out(5)),
pulse_cnt_ch6i_val_i => std_logic_vector(cnt_in(6)),
pulse_cnt_ch6o_val_i => std_logic_vector(cnt_out(6)),
pulse_cnt_rst_bit_o => cntrst
);
--============================================================================
-- Inverter outputs assignment
--============================================================================
inv_out_o <= inv_in_n_i;
--============================================================================
-- MultiBoot logic
--============================================================================
xbar_master_in(c_slv_multiboot).int <= '0';
xbar_master_in(c_slv_multiboot).rty <= '0';
xbar_master_in(c_slv_multiboot).err <= '0';
cmp_multiboot : wb_xil_multiboot
port map
(
clk_i => clk20_vcxo_i,
rst_n_i => rst_n,
wbs_i => xbar_master_out(c_slv_multiboot),
wbs_o => xbar_master_in(c_slv_multiboot),
spi_cs_n_o => fpga_prom_cso_b_n_o,
spi_sclk_o => fpga_prom_cclk_o,
spi_mosi_o => fpga_prom_mosi_o,
spi_miso_i => fpga_prom_miso_i
);
--============================================================================
-- Bicolor LED matrix logic
--============================================================================
-- Bicolor LED controls, corresponding to the column orders on the
-- bicolor_led_ctrl unit.
-- WR address
bicolor_led_state( 1 downto 0) <= c_LED_OFF;
-- WR GMT
bicolor_led_state( 3 downto 2) <= c_LED_OFF;
-- WR link
bicolor_led_state( 5 downto 4) <= c_LED_OFF;
-- WR OK
bicolor_led_state( 7 downto 6) <= c_LED_OFF;
-- MULTICAST 0
bicolor_led_state( 9 downto 8) <= c_LED_OFF;
-- MULTICAST 1
bicolor_led_state(11 downto 10) <= c_LED_OFF;
-- I2C
bicolor_led_state(13 downto 12) <= c_LED_GREEN when (led_i2c = '1') else
c_LED_RED when (led_i2c_err = '1') else
c_LED_OFF;
-- State of TTL/TTL_N switch
bicolor_led_state(15 downto 14) <= c_LED_GREEN when (ttl_switch_n_i = '0') else
c_LED_OFF;
-- System error
bicolor_led_state(17 downto 16) <= c_LED_RED when (rtmm_ok = '0') and (rtmp_ok = '0') else
c_LED_OFF;
-- System power
bicolor_led_state(19 downto 18) <= c_LED_GREEN;
-- MULTICAST 2
bicolor_led_state(21 downto 20) <= c_LED_OFF;
-- MULTICAST 3
bicolor_led_state(23 downto 22) <= c_LED_OFF;
cmp_bicolor_led_ctrl : bicolor_led_ctrl
generic map
(
g_NB_COLUMN => 6,
g_NB_LINE => 2,
g_clk_freq => 20000000,
g_refresh_rate => 250
)
port map
(
clk_i => clk20_vcxo_i,
rst_n_i => rst_n,
led_intensity_i => "1111111",
led_state_i => bicolor_led_state,
column_o(0) => led_wr_ownaddr_i2c_o,
column_o(1) => led_wr_gmt_ttl_ttln_o,
column_o(2) => led_wr_link_syserror_o,
column_o(3) => led_wr_ok_syspw_o,
column_o(4) => led_multicast_2_0_o,
column_o(5) => led_multicast_3_1_o,
line_o(0) => led_ctrl0_o,
line_o(1) => led_ctrl1_o,
line_oen_o(0) => led_ctrl0_oen_o,
line_oen_o(1) => led_ctrl1_oen_o
);
--============================================================================
-- RTM detection logic
--============================================================================
rtmm <= not fpga_rtmm_n_i;
rtmp <= not fpga_rtmp_n_i;
cmp_rtm_detector : rtm_detector
port map
(
rtmm_i => rtmm,
rtmp_i => rtmp,
rtmm_ok_o => rtmm_ok,
rtmp_ok_o => rtmp_ok
);
--============================================================================
-- Drive unused outputs with safe values
--============================================================================
-- Theremometer output to high-impedance
thermometer_b <= 'Z';
-- DAC outputs: enables to '1' (disable DAC comm interface) and SCK, DIN to '0'
fpga_plldac1_sync_n_o <= '1';
fpga_plldac1_din_o <= '0';
fpga_plldac1_sclk_o <= '0';
fpga_plldac2_sync_n_o <= '1';
fpga_plldac2_din_o <= '0';
fpga_plldac2_sclk_o <= '0';
-- SFP lines all open-drain, set to high-impedance
fpga_sfp_rate_select_o <= 'Z';
fpga_sfp_mod_def1_b <= 'Z';
fpga_sfp_mod_def2_b <= 'Z';
fpga_sfp_tx_disable_o <= 'Z';
end behav;
--==============================================================================
-- architecture end
--==============================================================================
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/top/regtest/ 0000775 0000000 0000000 00000000000 12314554267 0024414 5 ustar 00root root 0000000 0000000 conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/top/regtest/Manifest.py 0000664 0000000 0000000 00000000256 12314554267 0026537 0 ustar 00root root 0000000 0000000 files = [
"regtest.ucf",
"regtest.vhd"
]
modules = {
"local" : [
"../../ip_cores/general-cores",
"../../modules/"
],
}
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/top/regtest/regtest.ucf 0000664 0000000 0000000 00000044420 12314554267 0026574 0 ustar 00root root 0000000 0000000 ##--==============================================================================
##-- CERN (BE-CO-HT)
##-- Glitch filter with selectable length
##--==============================================================================
##--
##-- author: Theodor Stana (t.stana@cern.ch)
##-- Carlos-Gil Soriano
##--
##-- date of creation: 2013-04-26
##--
##-- version: 1.0
##--
##-- description:
##-- This file contains the pin definitions for the CONV-TTL-BLO FPGA. The pin
##-- names reflect those of net names at the schematic level. To keep to CERN
##-- coding standards (http://www.ohwr.org/documents/24) and make the code more
##-- readable, the pin names have been lowercased and the pin type is indicated
##-- by its suffix. The suffix "_i" indicates an input pin, "_o" an output pin
##-- and "_b" a bidirectional pin.
##--
##-- An example of net name change is given below:
##-- LED_WR_OWNADDR_I2C -> led_wr_ownaddr_i2c_o
##--
##-- Apart from this, some pins have been renamed completely and do not resemble
##-- the schematics. These pins are:
##-- TTL/INV_TTL_N -> ttl_switch_n_i
##--
##-- dependencies:
##--
##-- references:
##--
##--==============================================================================
##-- GNU LESSER GENERAL PUBLIC LICENSE
##--==============================================================================
##-- This source file is free software; you can redistribute it and/or modify it
##-- under the terms of the GNU Lesser General Public License as published by the
##-- Free Software Foundation; either version 2.1 of the License, or (at your
##-- option) any later version. This source is distributed in the hope that it
##-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
##-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
##-- See the GNU Lesser General Public License for more details. You should have
##-- received a copy of the GNU Lesser General Public License along with this
##-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
##--==============================================================================
##-- last changes:
##-- 2013-04-26 Theodor Stana t.stana@cern.ch File modified
##--==============================================================================
##-- TODO: -
##--==============================================================================
##-----------------------------------------------------------------------------
##-- Default attributes
##--
##-- IOSTANDARD = "LVCMOS25"
##-- SLEW = "SLOW"
##-- DRIVE = "12"
##-----------------------------------------------------------------------------
#NET "rst_i" LOC = N20;
#NET "rst_i" IOSTANDARD = "LVCMOS33";
#NET "fpga_sysreset_n_i" LOC = L20;
NET "mr_n_o" LOC = T22;
NET "mr_n_o" IOSTANDARD = LVCMOS33;
NET "clk20_vcxo_i" LOC = E16;
NET "clk20_vcxo_i" TNM_NET = "clk20_vcxo_i";
TIMESPEC TSCLK20 = PERIOD "clk20_vcxo_i" 20 MHz HIGH 50 %;
##=============================================================================
##-- FRONT PANEL TTLs
##=============================================================================
##-----------------------------------------------------------------------------
##-- Status LEDs
##-----------------------------------------------------------------------------
NET "led_ctrl0_o" LOC = M18;
NET "led_ctrl0_o" IOSTANDARD = LVCMOS33;
NET "led_ctrl0_oen_o" LOC = T20;
NET "led_ctrl0_oen_o" IOSTANDARD = LVCMOS33;
NET "led_ctrl1_o" LOC = M17;
NET "led_ctrl1_o" IOSTANDARD = LVCMOS33;
NET "led_ctrl1_oen_o" LOC = U19;
NET "led_ctrl1_oen_o" IOSTANDARD = LVCMOS33;
NET "led_multicast_2_0_o" LOC = P16;
NET "led_multicast_2_0_o" IOSTANDARD = LVCMOS33;
NET "led_multicast_3_1_o" LOC = P17;
NET "led_multicast_3_1_o" IOSTANDARD = LVCMOS33;
NET "led_wr_gmt_ttl_ttln_o" LOC = N16;
NET "led_wr_gmt_ttl_ttln_o" IOSTANDARD = LVCMOS33;
NET "led_wr_link_syserror_o" LOC = R15;
NET "led_wr_link_syserror_o" IOSTANDARD = LVCMOS33;
NET "led_wr_ok_syspw_o" LOC = R16;
NET "led_wr_ok_syspw_o" IOSTANDARD = LVCMOS33;
NET "led_wr_ownaddr_i2c_o" LOC = N15;
NET "led_wr_ownaddr_i2c_o" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- Front channel LEDs
##-----------------------------------------------------------------------------
NET "pulse_front_led_n_o[1]" LOC = H5;
NET "pulse_front_led_n_o[1]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[1]" DRIVE = 4;
NET "pulse_front_led_n_o[1]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[2]" LOC = J6;
NET "pulse_front_led_n_o[2]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[2]" DRIVE = 4;
NET "pulse_front_led_n_o[2]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[3]" LOC = K6;
NET "pulse_front_led_n_o[3]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[3]" DRIVE = 4;
NET "pulse_front_led_n_o[3]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[4]" LOC = K5;
NET "pulse_front_led_n_o[4]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[4]" DRIVE = 4;
NET "pulse_front_led_n_o[4]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[5]" LOC = M7;
NET "pulse_front_led_n_o[5]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[5]" DRIVE = 4;
NET "pulse_front_led_n_o[5]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[6]" LOC = M6;
NET "pulse_front_led_n_o[6]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[6]" DRIVE = 4;
NET "pulse_front_led_n_o[6]" SLEW = QUIETIO;
##-----------------------------------------------------------------------------
##-- Rear LEDs
##-----------------------------------------------------------------------------
NET "pulse_rear_led_n_o[1]" LOC = AB17;
NET "pulse_rear_led_n_o[1]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[1]" DRIVE = 4;
NET "pulse_rear_led_n_o[1]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[2]" LOC = AB19;
NET "pulse_rear_led_n_o[2]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[2]" DRIVE = 4;
NET "pulse_rear_led_n_o[2]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[3]" LOC = AA16;
NET "pulse_rear_led_n_o[3]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[3]" DRIVE = 4;
NET "pulse_rear_led_n_o[3]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[4]" LOC = AA18;
NET "pulse_rear_led_n_o[4]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[4]" DRIVE = 4;
NET "pulse_rear_led_n_o[4]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[5]" LOC = AB16;
NET "pulse_rear_led_n_o[5]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[5]" DRIVE = 4;
NET "pulse_rear_led_n_o[5]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[6]" LOC = AB18;
NET "pulse_rear_led_n_o[6]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[6]" DRIVE = 4;
NET "pulse_rear_led_n_o[6]" SLEW = QUIETIO;
##-----------------------------------------------------------------------------
##-- TTL trigger I/O
##-----------------------------------------------------------------------------
NET "fpga_input_ttl_n_i[1]" LOC = T2;
NET "fpga_input_ttl_n_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[1]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[2]" LOC = U3;
NET "fpga_input_ttl_n_i[2]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[2]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[3]" LOC = V5;
NET "fpga_input_ttl_n_i[3]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[3]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[4]" LOC = W4;
NET "fpga_input_ttl_n_i[4]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[4]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[5]" LOC = T6;
NET "fpga_input_ttl_n_i[5]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[5]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[6]" LOC = T3;
NET "fpga_input_ttl_n_i[6]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[6]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_out_ttl_o[1]" LOC = C1;
NET "fpga_out_ttl_o[1]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[2]" LOC = F2;
NET "fpga_out_ttl_o[2]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[3]" LOC = F5;
NET "fpga_out_ttl_o[3]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[4]" LOC = H4;
NET "fpga_out_ttl_o[4]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[5]" LOC = J4;
NET "fpga_out_ttl_o[5]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[6]" LOC = H2;
NET "fpga_out_ttl_o[6]" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- Inverted TTL I/O
##-----------------------------------------------------------------------------
NET "inv_in_n_i[1]" LOC = V2;
NET "inv_in_n_i[1]" IOSTANDARD = LVCMOS33;
NET "inv_in_n_i[1]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "inv_in_n_i[2]" LOC = W3;
NET "inv_in_n_i[2]" IOSTANDARD = LVCMOS33;
NET "inv_in_n_i[2]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "inv_in_n_i[3]" LOC = Y2;
NET "inv_in_n_i[3]" IOSTANDARD = LVCMOS33;
NET "inv_in_n_i[3]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "inv_in_n_i[4]" LOC = AA2;
NET "inv_in_n_i[4]" IOSTANDARD = LVCMOS33;
NET "inv_in_n_i[4]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "inv_out_o[1]" LOC = J3;
NET "inv_out_o[1]" IOSTANDARD = LVCMOS33;
NET "inv_out_o[2]" LOC = L3;
NET "inv_out_o[2]" IOSTANDARD = LVCMOS33;
NET "inv_out_o[3]" LOC = M3;
NET "inv_out_o[3]" IOSTANDARD = LVCMOS33;
NET "inv_out_o[4]" LOC = P2;
NET "inv_out_o[4]" IOSTANDARD = LVCMOS33;
##=============================================================================
##-- RTM signals
##=============================================================================
##-----------------------------------------------------------------------------
##-- Blocking I/O
##-----------------------------------------------------------------------------
NET "fpga_blo_in_i[1]" LOC = Y9;
NET "fpga_blo_in_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_blo_in_i[2]" LOC = AA10;
NET "fpga_blo_in_i[2]" IOSTANDARD = LVCMOS33;
NET "fpga_blo_in_i[3]" LOC = W12;
NET "fpga_blo_in_i[3]" IOSTANDARD = LVCMOS33;
NET "fpga_blo_in_i[4]" LOC = AA6;
NET "fpga_blo_in_i[4]" IOSTANDARD = LVCMOS33;
NET "fpga_blo_in_i[5]" LOC = Y7;
NET "fpga_blo_in_i[5]" IOSTANDARD = LVCMOS33;
NET "fpga_blo_in_i[6]" LOC = AA8;
NET "fpga_blo_in_i[6]" IOSTANDARD = LVCMOS33;
NET "fpga_trig_blo_o[1]" LOC = W9;
NET "fpga_trig_blo_o[1]" IOSTANDARD = LVCMOS33;
NET "fpga_trig_blo_o[2]" LOC = T10;
NET "fpga_trig_blo_o[2]" IOSTANDARD = LVCMOS33;
NET "fpga_trig_blo_o[3]" LOC = V7;
NET "fpga_trig_blo_o[3]" IOSTANDARD = LVCMOS33;
NET "fpga_trig_blo_o[4]" LOC = U9;
NET "fpga_trig_blo_o[4]" IOSTANDARD = LVCMOS33;
NET "fpga_trig_blo_o[5]" LOC = T8;
NET "fpga_trig_blo_o[5]" IOSTANDARD = LVCMOS33;
NET "fpga_trig_blo_o[6]" LOC = R9;
NET "fpga_trig_blo_o[6]" IOSTANDARD = LVCMOS33;
##=============================================================================
##-- VME CONNECTOR SIGNALS
##=============================================================================
##-----------------------------------------------------------------------------
##-- I2C lines
##-----------------------------------------------------------------------------
NET "scl_i" LOC = F19;
NET "scl_i" IOSTANDARD = LVCMOS33;
NET "scl_o" LOC = E20;
NET "scl_o" IOSTANDARD = LVCMOS33;
NET "scl_o" DRIVE = 4;
NET "scl_oe_o" LOC = H18;
NET "scl_oe_o" IOSTANDARD = LVCMOS33;
NET "scl_oe_o" DRIVE = 4;
# NET "scl_oe_o" PULLDOWN;
NET "sda_i" LOC = G20;
NET "sda_i" IOSTANDARD = LVCMOS33;
NET "sda_o" LOC = F20;
NET "sda_o" IOSTANDARD = LVCMOS33;
NET "sda_o" SLEW = FAST;
NET "sda_o" DRIVE = 4;
# NET "sda_o" PULLUP;
NET "sda_oe_o" LOC = J19;
NET "sda_oe_o" IOSTANDARD = LVCMOS33;
NET "sda_oe_o" SLEW = FAST;
NET "sda_oe_o" DRIVE = 4;
# NET "sda_oe_o" PULLDOWN;
##-----------------------------------------------------------------------------
##-- Geographical Address
##-----------------------------------------------------------------------------
NET "fpga_ga_i[0]" LOC = H20;
NET "fpga_ga_i[0]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[1]" LOC = J20;
NET "fpga_ga_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[2]" LOC = K19;
NET "fpga_ga_i[2]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[3]" LOC = K20;
NET "fpga_ga_i[3]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[4]" LOC = L19;
NET "fpga_ga_i[4]" IOSTANDARD = LVCMOS33;
NET "fpga_gap_i" LOC = H19;
NET "fpga_gap_i" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- ROM memory
##-----------------------------------------------------------------------------
NET "fpga_prom_cclk_o" LOC = Y20;
NET "fpga_prom_cclk_o" IOSTANDARD = LVCMOS33;
NET "fpga_prom_cso_b_n_o" LOC = AA3;
NET "fpga_prom_cso_b_n_o" IOSTANDARD = LVCMOS33;
NET "fpga_prom_miso_i" LOC = AA20;
NET "fpga_prom_miso_i" IOSTANDARD = LVCMOS33;
NET "fpga_prom_mosi_o" LOC = AB20;
NET "fpga_prom_mosi_o" IOSTANDARD = LVCMOS33;
##=============================================================================
##-- WHITE RABBIT
##=============================================================================
##-----------------------------------------------------------------------------
##-- Thermo for UID
##-----------------------------------------------------------------------------
NET "thermometer_b" LOC = B1;
NET "thermometer_b" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- DAC control
##-----------------------------------------------------------------------------
NET "fpga_plldac1_din_o" LOC = AB14;
NET "fpga_plldac1_din_o" IOSTANDARD = LVCMOS33;
NET "fpga_plldac1_sclk_o" LOC = AA14;
NET "fpga_plldac1_sclk_o" IOSTANDARD = LVCMOS33;
NET "fpga_plldac1_sync_n_o" LOC = AB15;
NET "fpga_plldac1_sync_n_o" IOSTANDARD = LVCMOS33;
NET "fpga_plldac2_din_o" LOC = W14;
NET "fpga_plldac2_din_o" IOSTANDARD = LVCMOS33;
NET "fpga_plldac2_sclk_o" LOC = Y14;
NET "fpga_plldac2_sclk_o" IOSTANDARD = LVCMOS33;
NET "fpga_plldac2_sync_n_o" LOC = W13;
NET "fpga_plldac2_sync_n_o" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- SFP connection
##-----------------------------------------------------------------------------
NET "fpga_sfp_los_i" LOC = G3;
NET "fpga_sfp_los_i" IOSTANDARD = LVCMOS33;
NET "fpga_sfp_mod_def0_i" LOC = K8;
NET "fpga_sfp_mod_def0_i" IOSTANDARD = LVCMOS33;
NET "fpga_sfp_rate_select_o" LOC = C4;
NET "fpga_sfp_rate_select_o" IOSTANDARD = LVCMOS33;
NET "fpga_sfp_mod_def1_b" LOC = G4;
NET "fpga_sfp_mod_def1_b" IOSTANDARD = LVCMOS33;
NET "fpga_sfp_mod_def2_b" LOC = F3;
NET "fpga_sfp_mod_def2_b" IOSTANDARD = LVCMOS33;
NET "fpga_sfp_tx_disable_o" LOC = E4;
NET "fpga_sfp_tx_disable_o" IOSTANDARD = LVCMOS33;
NET "fpga_sfp_tx_fault_i" LOC = D2;
NET "fpga_sfp_tx_fault_i" IOSTANDARD = LVCMOS33;
###-----------------------------------------------------------------------------
###-- FPGA MGT lines
###-----------------------------------------------------------------------------
#NET "fpga_mgt_clk0_p_i" LOC = A10;
#NET "fpga_mgt_clk0_n_i" LOC = B10;
#
#NET "mgt_sfp_rx0_p_i" LOC = D7;
#NET "mgt_sfp_rx0_n_i" LOC = C7;
#
#NET "mgt_sfp_tx0_p_o" LOC = B6;
#NET "mgt_sfp_tx0_n_o" LOC = A6;
###=============================================================================
###-- ADDITIONAL PINS
###=============================================================================
NET "fpga_oe_o" LOC = R3;
NET "fpga_oe_o" IOSTANDARD = LVCMOS33;
NET "fpga_oe_o" DRIVE = 4;
NET "fpga_oe_o" SLEW = QUIETIO;
NET "fpga_blo_oe_o" LOC = P5;
NET "fpga_blo_oe_o" IOSTANDARD = LVCMOS33;
NET "fpga_blo_oe_o" DRIVE = 4;
NET "fpga_blo_oe_o" SLEW = QUIETIO;
NET "fpga_trig_ttl_oe_o" LOC = N3;
NET "fpga_trig_ttl_oe_o" IOSTANDARD = LVCMOS33;
NET "fpga_trig_ttl_oe_o" DRIVE = 4;
NET "fpga_trig_ttl_oe_o" SLEW = QUIETIO;
NET "fpga_inv_oe_o" LOC = P6;
NET "fpga_inv_oe_o" IOSTANDARD = LVCMOS33;
NET "fpga_inv_oe_o" DRIVE = 4;
NET "fpga_inv_oe_o" SLEW = QUIETIO;
##-----------------------------------------------------------------------------
##-- Configuration Switches
##-----------------------------------------------------------------------------
NET "extra_switch_n_i[1]" LOC = F22;
NET "extra_switch_n_i[1]" IOSTANDARD = LVCMOS33;
NET "extra_switch_n_i[2]" LOC = G22;
NET "extra_switch_n_i[2]" IOSTANDARD = LVCMOS33;
NET "extra_switch_n_i[3]" LOC = H21;
NET "extra_switch_n_i[3]" IOSTANDARD = LVCMOS33;
NET "extra_switch_n_i[4]" LOC = H22;
NET "extra_switch_n_i[4]" IOSTANDARD = LVCMOS33;
NET "extra_switch_n_i[5]" LOC = J22;
NET "extra_switch_n_i[5]" IOSTANDARD = LVCMOS33;
NET "extra_switch_n_i[6]" LOC = K21;
NET "extra_switch_n_i[6]" IOSTANDARD = LVCMOS33;
NET "extra_switch_n_i[7]" LOC = K22;
NET "extra_switch_n_i[7]" IOSTANDARD = LVCMOS33;
NET "ttl_switch_n_i" LOC = L22;
NET "ttl_switch_n_i" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- Motherboard and piggyback IDs
##-----------------------------------------------------------------------------
NET "fpga_rtmm_n_i[0]" LOC = V21;
NET "fpga_rtmm_n_i[0]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmm_n_i[1]" LOC = V22;
NET "fpga_rtmm_n_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmm_n_i[2]" LOC = U22;
NET "fpga_rtmm_n_i[2]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmp_n_i[0]" LOC = W22;
NET "fpga_rtmp_n_i[0]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmp_n_i[1]" LOC = Y22;
NET "fpga_rtmp_n_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmp_n_i[2]" LOC = Y21;
NET "fpga_rtmp_n_i[2]" IOSTANDARD = LVCMOS33;
###-----------------------------------------------------------------------------
###-- General purpose
###-----------------------------------------------------------------------------
# NET "fpga_header_out_n_o[1]" LOC = F15;
# NET "fpga_header_out_n_o[1]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[2]" LOC = F16;
# NET "fpga_header_out_n_o[2]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[3]" LOC = F17;
# NET "fpga_header_out_n_o[3]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[4]" LOC = F14;
# NET "fpga_header_out_n_o[4]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[5]" LOC = H14;
# NET "fpga_header_out_n_o[5]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[6]" LOC = H13;
# NET "fpga_header_out_n_o[6]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[1]" LOC = A17;
# NET "fpga_header_in_n_i[1]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[2]" LOC = A18;
# NET "fpga_header_in_n_i[2]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[3]" LOC = B18;
# NET "fpga_header_in_n_i[3]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[4]" LOC = A19;
# NET "fpga_header_in_n_i[4]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[5]" LOC = A20;
# NET "fpga_header_in_n_i[5]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[6]" LOC = B20;
# NET "fpga_header_in_n_i[6]" IOSTANDARD = "LVCMOS33";
conv-ttl-blo-gw-cc71e6a067afafcef42a5be4a3f837fad8777f7c/top/regtest/regtest.vhd 0000664 0000000 0000000 00000046102 12314554267 0026577 0 ustar 00root root 0000000 0000000 --==============================================================================
-- CERN (BE-CO-HT)
-- Long-term register test for CONV-TTL-* boards
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- version: 1.0
--
-- description:
-- This is the top-level file for the register test for TTL pulse converter
-- boards. It instantiates a single-port RAM from the general-cores OHWR
-- repository and connects this RAM via an xwb_crossbar (also from
-- general-cores) to the i2c_bridge component.
--
-- An external program on the PC should send commands according to the I2C
-- protocol established with ELMA [2], to write and read from the single-port
-- RAM. The CONV-TTL-BLO is plugged into this ELMA crate. The wb_i2c_bridge
-- translates these commands into wishbone accesses to the RAM.
--
-- An example program can be found in the conv-ttl-blo repository [3], under
-- the software/regtest/ folder. This Python script writes to and reads back
-- all data from the RAM and checks for correct reading.
--
-- dependencies:
-- general-cores repository [1]
--
-- references:
-- [1] Platform-independent core collection webpage on OHWR,
-- http://www.ohwr.org/projects/general-cores/repository
-- [2] ELMA, Access to board data using SNMP and I2C
-- http://www.ohwr.org/documents/227
-- [3] CONV-TTL-BLO project repository on OHWR,
-- http://www.ohwr.org/projects/conv-ttl-blo/repository
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 26-11-2013 Theodor Stana Changed file header
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
library unisim;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use unisim.vcomponents.all;
use work.bicolor_led_ctrl_pkg.all;
use work.wishbone_pkg.all;
use work.gencores_pkg.all;
use work.genram_pkg.all;
entity regtest is
generic
(
g_nr_ttl_chan : natural := 6;
g_nr_inv_chan : natural := 4
);
port
(
-- Clocks
-- 20 MHz from VCXO
clk20_vcxo_i : in std_logic;
-- 125 MHz from clock generator
fpga_clk_p_i : in std_logic;
fpga_clk_n_i : in std_logic;
-- LEDs
led_ctrl0_o : out std_logic;
led_ctrl0_oen_o : out std_logic;
led_ctrl1_o : out std_logic;
led_ctrl1_oen_o : out std_logic;
led_multicast_2_0_o : out std_logic;
led_multicast_3_1_o : out std_logic;
led_wr_gmt_ttl_ttln_o : out std_logic;
led_wr_link_syserror_o : out std_logic;
led_wr_ok_syspw_o : out std_logic;
led_wr_ownaddr_i2c_o : out std_logic;
-- I/Os for pulses
pulse_front_led_n_o : out std_logic_vector(g_nr_ttl_chan downto 1);
pulse_rear_led_n_o : out std_logic_vector(g_nr_ttl_chan downto 1);
fpga_input_ttl_n_i : in std_logic_vector(g_nr_ttl_chan downto 1);
fpga_out_ttl_o : out std_logic_vector(g_nr_ttl_chan downto 1);
fpga_blo_in_i : in std_logic_vector(g_nr_ttl_chan downto 1);
fpga_trig_blo_o : out std_logic_vector(g_nr_ttl_chan downto 1);
inv_in_n_i : in std_logic_vector(g_nr_inv_chan downto 1);
inv_out_o : out std_logic_vector(g_nr_inv_chan downto 1);
-- Output enable lines
fpga_oe_o : out std_logic;
fpga_blo_oe_o : out std_logic;
fpga_trig_ttl_oe_o : out std_logic;
fpga_inv_oe_o : out std_logic;
--TTL/INV_TTL_N
ttl_switch_n_i : in std_logic;
extra_switch_n_i : in std_logic_vector(7 downto 1);
-- Lines for the i2c_slave
scl_i : in std_logic;
scl_o : out std_logic;
scl_oe_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
sda_oe_o : out std_logic;
fpga_ga_i : in std_logic_vector(4 downto 0);
fpga_gap_i : in std_logic;
-- Flash memory lines
fpga_prom_cclk_o : out std_logic;
fpga_prom_cso_b_n_o : out std_logic;
fpga_prom_mosi_o : out std_logic;
fpga_prom_miso_i : in std_logic;
-- Blocking power supply reset line
mr_n_o : out std_logic;
-- Thermometer line
thermometer_b : inout std_logic;
-- PLL DACs
-- DAC1: 20 MHz VCXO control
fpga_plldac1_din_o : out std_logic;
fpga_plldac1_sclk_o : out std_logic;
fpga_plldac1_sync_n_o : out std_logic;
-- DAC2: 125 MHz clock generator control
fpga_plldac2_din_o : out std_logic;
fpga_plldac2_sclk_o : out std_logic;
fpga_plldac2_sync_n_o : out std_logic;
-- SFP lines
fpga_sfp_los_i : in std_logic;
fpga_sfp_mod_def0_i : in std_logic;
fpga_sfp_rate_select_o : out std_logic;
fpga_sfp_mod_def1_b : inout std_logic;
fpga_sfp_mod_def2_b : inout std_logic;
fpga_sfp_tx_disable_o : out std_logic;
fpga_sfp_tx_fault_i : in std_logic;
-- RTM identifiers, should match with the expected values
fpga_rtmm_n_i : in std_logic_vector(2 downto 0);
fpga_rtmp_n_i : in std_logic_vector(2 downto 0)
);
end regtest;
architecture behav of regtest is
--============================================================================
-- Constant declarations
--============================================================================
-- Number of Wishbone masters and slaves, for wb_crossbar
constant c_nr_masters : natural := 1;
constant c_nr_slaves : natural := 1;
-----------------------------------------
-- Memory map
-- * all registers are word-addressable
-- * all registers are word-aligned
-----------------------------------------
-- MEM [000-FFF]
-----------------------------------------
-- slave order definitions
constant c_slv_mem : natural := 0;
-- base address definitions
constant c_addr_mem : t_wishbone_address := x"00000000";
-- address mask definitions
constant c_mask_mem : t_wishbone_address := x"00000000";
-- addresses constant for Wishbone crossbar
constant c_addresses : t_wishbone_address_array(c_nr_slaves-1 downto 0)
:= (
c_slv_mem => c_addr_mem
);
-- masks constant for Wishbone crossbar
constant c_masks : t_wishbone_address_array(c_nr_slaves-1 downto 0)
:= (
c_slv_mem => c_mask_mem
);
--============================================================================
-- Component declarations
--============================================================================
-- Reset generator component
-- (use: global reset generation, output reset generation)
component reset_gen is
generic
(
-- Reset time in number of clk_i cycles
g_reset_time : positive := 2_000_000
);
port
(
clk_i : in std_logic;
rst_i : in std_logic;
rst_n_o : out std_logic
);
end component reset_gen;
--============================================================================
-- Signal declarations
--============================================================================
-- Reset signals
signal rst_n : std_logic;
-- Wishbone crossbar signals
signal xbar_slave_in : t_wishbone_slave_in_array (c_nr_masters - 1 downto 0);
signal xbar_slave_out : t_wishbone_slave_out_array (c_nr_masters - 1 downto 0);
signal xbar_master_in : t_wishbone_master_in_array (c_nr_slaves - 1 downto 0);
signal xbar_master_out : t_wishbone_master_out_array(c_nr_slaves - 1 downto 0);
-- RAM signals
signal ram_we : std_logic;
signal ram_ack : std_logic;
-- Signal for controlling the bicolor LED matrix
signal bicolor_led_state : std_logic_vector(23 downto 0);
-- I2C bridge signals
signal i2c_tip : std_logic;
signal i2c_tip_d0 : std_logic;
signal i2c_err_p : std_logic;
signal i2c_up : std_logic;
signal i2c_wdto_p : std_logic;
signal i2c_addr : std_logic_vector(6 downto 0);
signal led_i2c : std_logic;
signal led_i2c_clkdiv : unsigned(22 downto 0);
signal led_i2c_cnt : unsigned( 2 downto 0);
signal led_i2c_err : std_logic;
signal led_i2c_blink : std_logic;
signal led_wdto : std_logic;
-- Transfer trigger for oscilloscope
signal trig_p : std_logic;
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Internal and external reset generation
--============================================================================
-- Configure reset generator for 96ms power-on reset
cmp_reset_gen : reset_gen
generic map
(
-- Reset time: 12 * 8ns * (10**6) = 96 ms
g_reset_time => 12*(10**6)
)
port map
(
clk_i => clk20_vcxo_i,
rst_i => '0',
rst_n_o => rst_n
);
-- rst <= not rst_n;
mr_n_o <= rst_n;
--============================================================================
-- I2C bridge logic
--============================================================================
-- Set the I2C address signal according to ELMA protocol [1]
i2c_addr <= "10" & fpga_ga_i;
-- Instantiate VBCP bridge component
cmp_i2c_bridge : wb_i2c_bridge
port map
(
-- Clock, reset
clk_i => clk20_vcxo_i,
rst_n_i => rst_n,
-- I2C lines
scl_i => scl_i,
scl_o => scl_o,
scl_en_o => scl_oe_o,
sda_i => sda_i,
sda_o => sda_o,
sda_en_o => sda_oe_o,
-- I2C address and status
i2c_addr_i => i2c_addr,
tip_o => i2c_tip,
err_p_o => i2c_err_p,
wdto_p_o => i2c_wdto_p,
-- Wishbone master signals
wbm_stb_o => xbar_slave_in(0).stb,
wbm_cyc_o => xbar_slave_in(0).cyc,
wbm_sel_o => xbar_slave_in(0).sel,
wbm_we_o => xbar_slave_in(0).we,
wbm_dat_i => xbar_slave_out(0).dat,
wbm_dat_o => xbar_slave_in(0).dat,
wbm_adr_o => xbar_slave_in(0).adr,
wbm_ack_i => xbar_slave_out(0).ack,
wbm_rty_i => xbar_slave_out(0).rty,
wbm_err_i => xbar_slave_out(0).err
);
-- Process to blink the LED when an I2C transfer is in progress
-- blinks four times per transfer
-- blink width : 20 ms
-- blink period: 40 ms
p_i2c_blink : process(clk20_vcxo_i)
begin
if rising_edge(clk20_vcxo_i) then
if (rst_n = '0') then
led_i2c_clkdiv <= (others => '0');
led_i2c_cnt <= (others => '0');
led_i2c <= '0';
led_i2c_blink <= '0';
else
case led_i2c_blink is
when '0' =>
led_i2c <= '0';
if (i2c_tip = '1') then
led_i2c_blink <= '1';
end if;
when '1' =>
led_i2c_clkdiv <= led_i2c_clkdiv + 1;
if (led_i2c_clkdiv = 399999) then
led_i2c_clkdiv <= (others => '0');
led_i2c_cnt <= led_i2c_cnt + 1;
led_i2c <= not led_i2c;
if (led_i2c_cnt = 7) then
led_i2c_cnt <= (others => '0');
led_i2c_blink <= '0';
end if;
end if;
when others =>
led_i2c_blink <= '0';
end case;
end if;
end if;
end process p_i2c_blink;
-- Process to set the I2C error LED signal for display on the front panel
-- of the front module. The I2C error signal is permanently set once an
-- error is detected from the bridge module.
p_i2c_err_led : process (clk20_vcxo_i) is
begin
if rising_edge(clk20_vcxo_i) then
if (rst_n = '0') then
led_i2c_err <= '0';
elsif (i2c_err_p = '1') then
led_i2c_err <= '1';
end if;
end if;
end process p_i2c_err_led;
-- Process to light a LED in case of WDTO error
p_wdto_led : process (clk20_vcxo_i)
begin
if rising_edge(clk20_vcxo_i) then
if (rst_n = '0') then
led_wdto <= '0';
elsif (i2c_wdto_p = '1') then
led_wdto <= '1';
end if;
end if;
end process p_wdto_led;
-- Pulse the first LEMO output on the card's front panel when a transfer is
-- finished. This is used to scope the bus in case of error
p_trig_oscilloscope : process (clk20_vcxo_i)
begin
if rising_edge(clk20_vcxo_i) then
if (rst_n = '0') then
i2c_tip_d0 <= '0';
trig_p <= '0';
else
i2c_tip_d0 <= i2c_tip;
trig_p <= (not i2c_tip) and (i2c_tip_d0);
end if;
end if;
end process p_trig_oscilloscope;
fpga_out_ttl_o(1) <= trig_p;
--============================================================================
-- Instantiation and connection of the main Wishbone crossbar
--============================================================================
xbar_master_in(0).int <= '0';
xbar_master_in(0).err <= '0';
cmp_wb_crossbar : xwb_crossbar
generic map
(
g_num_masters => c_nr_masters,
g_num_slaves => c_nr_slaves,
g_registered => false,
g_address => c_addresses,
g_mask => c_masks
)
port map
(
clk_sys_i => clk20_vcxo_i,
rst_n_i => rst_n,
slave_i => xbar_slave_in,
slave_o => xbar_slave_out,
master_i => xbar_master_in,
master_o => xbar_master_out
);
--============================================================================
-- Instantiate single-port RAM
--============================================================================
cmp_memory: generic_spram
generic map (
g_data_width => 32,
g_size => 2**12
)
port map (
rst_n_i => rst_n,
clk_i => clk20_vcxo_i,
bwe_i => (others => '0'),
we_i => ram_we,
a_i => xbar_master_out(c_slv_mem).adr(11 downto 0),
d_i => xbar_master_out(c_slv_mem).dat,
q_o => xbar_master_in(c_slv_mem).dat
);
ram_we <= xbar_master_out(c_slv_mem).we and xbar_master_out(c_slv_mem).stb and
xbar_master_out(c_slv_mem).cyc;
xbar_master_in(c_slv_mem).ack <= ram_ack;
xbar_master_in(c_slv_mem).err <= '0';
p_ram_ack : process (clk20_vcxo_i) is
begin
if rising_edge(clk20_vcxo_i) then
if (rst_n = '0') then
ram_ack <= '0';
else
ram_ack <= '0';
if (xbar_master_out(c_slv_mem).stb = '1') and
(xbar_master_out(c_slv_mem).cyc = '1') then
ram_ack <= '1';
end if;
end if;
end if;
end process p_ram_ack;
--============================================================================
-- Bicolor LED matrix logic
--============================================================================
-- Bicolor LED controls, corresponding to the column orders on the
-- bicolor_led_ctrl unit.
-- WR address
bicolor_led_state( 1 downto 0) <= c_LED_OFF;
-- WR GMT
bicolor_led_state( 3 downto 2) <= c_LED_OFF;
-- WR link
bicolor_led_state( 5 downto 4) <= c_LED_OFF;
-- WR OK
bicolor_led_state( 7 downto 6) <= c_LED_OFF;
-- MULTICAST 0
bicolor_led_state( 9 downto 8) <= c_LED_RED when led_wdto = '1' else
c_LED_OFF;
-- MULTICAST 1
bicolor_led_state(11 downto 10) <= c_LED_OFF;
-- I2C
bicolor_led_state(13 downto 12) <= c_LED_GREEN when (led_i2c = '1') else
c_LED_RED when (led_i2c_err = '1') else
c_LED_OFF;
-- State of TTL/TTL_N switch
bicolor_led_state(15 downto 14) <= c_LED_OFF;
-- System error
bicolor_led_state(17 downto 16) <= c_LED_OFF;
-- System power
bicolor_led_state(19 downto 18) <= c_LED_GREEN;
-- MULTICAST 2
bicolor_led_state(21 downto 20) <= c_LED_OFF;
-- MULTICAST 3
bicolor_led_state(23 downto 22) <= c_LED_OFF;
cmp_bicolor_led_ctrl : bicolor_led_ctrl
generic map
(
g_NB_COLUMN => 6,
g_NB_LINE => 2,
g_clk_freq => 20000000,
g_refresh_rate => 250
)
port map
(
clk_i => clk20_vcxo_i,
rst_n_i => rst_n,
led_intensity_i => "1111111",
led_state_i => bicolor_led_state,
column_o(0) => led_wr_ownaddr_i2c_o,
column_o(1) => led_wr_gmt_ttl_ttln_o,
column_o(2) => led_wr_link_syserror_o,
column_o(3) => led_wr_ok_syspw_o,
column_o(4) => led_multicast_2_0_o,
column_o(5) => led_multicast_3_1_o,
line_o(0) => led_ctrl0_o,
line_o(1) => led_ctrl1_o,
line_oen_o(0) => led_ctrl0_oen_o,
line_oen_o(1) => led_ctrl1_oen_o
);
--============================================================================
-- Drive unused outputs with safe values
--============================================================================
-- Theremometer output to high-impedance
thermometer_b <= 'Z';
-- DAC outputs: enables to '1' (disable DAC comm interface) and SCK, DIN to '0'
fpga_plldac1_sync_n_o <= '1';
fpga_plldac1_din_o <= '0';
fpga_plldac1_sclk_o <= '0';
fpga_plldac2_sync_n_o <= '1';
fpga_plldac2_din_o <= '0';
fpga_plldac2_sclk_o <= '0';
-- SFP lines all open-drain, set to high-impedance
fpga_sfp_rate_select_o <= 'Z';
fpga_sfp_mod_def1_b <= 'Z';
fpga_sfp_mod_def2_b <= 'Z';
fpga_sfp_tx_disable_o <= 'Z';
-- Pulse outputs and pulse LEDs
fpga_oe_o <= '1';
fpga_blo_oe_o <= '0';
fpga_trig_ttl_oe_o <= '1';
fpga_inv_oe_o <= '0';
pulse_front_led_n_o <= (others => '1');
pulse_rear_led_n_o <= (others => '1');
fpga_out_ttl_o(6 downto 2) <= (others => '0');
fpga_trig_blo_o <= (others => '0');
inv_out_o <= (others => '0');
-- Flash outputs
fpga_prom_cclk_o <= '0';
fpga_prom_cso_b_n_o <= '1';
fpga_prom_mosi_o <= '0';
end behav;
--==============================================================================
-- architecture end
--==============================================================================