--==============================================================================
-- CERN (BE-CO-HT)
-- Converter board registers wbgen2 description file (pulsetest gateware)
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation:
--
-- version: 1.0
--
-- description:
--    This file contains the register description for the converter board
--    registers and is to be used as input to the wbgen2 tool for generating
--    an appropriate VHDL file.
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
--    03-05-2014   Theodor Stana     Added GPL header
--==============================================================================
-- TODO: -
--==============================================================================

peripheral {
  name = "Converter board registers";
  hdl_entity = "conv_regs";
  prefix = "reg";

  reg {
    name = "Board ID Register";
    description = "Bits of ID register, defaulting to ASCII string TBLO";
    prefix = "id";
    field {
      name = "bits";
      prefix = "bits";
      type = SLV;
      size = 32;
      access_dev = WRITE_ONLY;
      access_bus = READ_ONLY;
    };
  };

  reg {
    name = "Status Register";
    description = "Contains various board status information";
    prefix = "sr";
    field {
      name = "fwvers";
      prefix = "fwvers";
      type = SLV;
      size = 8;
      access_dev = WRITE_ONLY;
      access_bus = READ_ONLY;
    };
    field {
      name = "switches";
      prefix = "switches";
      type = SLV;
      size = 8;
      access_dev = WRITE_ONLY;
      access_bus = READ_ONLY;
    };
    field {
      name = "RTM detection";
      prefix = "rtm";
      type = SLV;
      size = 6;
      access_dev = WRITE_ONLY;
      access_bus = READ_ONLY;
    };
    field {
      name       = "I2C Watchdog Timeout";
      prefix     = "i2c_wdto";
      type       = BIT;
      size       = 1;
      access_dev = READ_WRITE;
      access_bus = READ_WRITE;
      load       = LOAD_EXT;
    };
  };
  reg {
    name = "Control Register";
    description = "Contains bits that control operation of the converter modules";
    prefix = "cr";
--    field {
--      name = "blocking chan 1 enable";
--      prefix = "bch1_en";
--      type = BIT;
--      access_bus = READ_WRITE;
--      access_dev = READ_ONLY;
--    };
--    field {
--      name = "blocking chan 2 enable";
--      prefix = "bch2_en";
--      type = BIT;
--      access_bus = READ_WRITE;
--      access_dev = READ_ONLY;
--    };
--    field {
--      name = "blocking chan 3 enable";
--      prefix = "bch3_en";
--      type = BIT;
--      access_bus = READ_WRITE;
--      access_dev = READ_ONLY;
--    };
--    field {
--      name = "blocking chan 4 enable";
--      prefix = "bch4_en";
--      type = BIT;
--      access_bus = READ_WRITE;
--      access_dev = READ_ONLY;
--    };
--    field {
--      name = "blocking chan 5 enable";
--      prefix = "bch5_en";
--      type = BIT;
--      access_bus = READ_WRITE;
--      access_dev = READ_ONLY;
--    };
--    field {
--      name = "blocking chan 6 enable";
--      prefix = "bch6_en";
--      type = BIT;
--      access_bus = READ_WRITE;
--      access_dev = READ_ONLY;
--    };
    field {
      name = "Reset unlock bit";
      prefix = "rst_unlock";
      description = "1 - Reset bit unlocked\
                     0 - Reset bit locked";
      type = BIT;
      access_dev = READ_WRITE;
      access_bus = READ_WRITE;
      load = LOAD_EXT;
    };
    field {
      name = "Reset bit";
      prefix = "rst";
      description = "1 - initiate logic reset\
                     0 - no reset";
      type = BIT;
      access_bus = READ_WRITE;
      access_dev = READ_WRITE;
      load = LOAD_EXT;
    };
  };
};
