--==============================================================================
-- CERN (BE-CO-HT)
-- Pulse generator registers wbgen2 description file (pulsetest gateware)
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation:
--
-- version: 1.0
--
-- description:
--    This file contains the register description for the pulse generator
--    registers and is to be used as input to the wbgen2 tool for generating
--    an appropriate VHDL file.
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
--    03-05-2014   Theodor Stana     Added GPL header
--==============================================================================
-- TODO: -
--==============================================================================

peripheral {
  name = "Pulse generation control registers";
  description = "Registers containing control signals for the general-purpose pulse generator blocks";
  hdl_entity  = "pgen_ctrl_regs";
  prefix = "pgen_ctrl_regs";

  reg {
    name = "Enable register";
    prefix = "en";
    field {
      name = "channel enable";
      prefix = "ch";
      type = SLV;
      size = 6;
    };
  };

  reg {
    name = "CH1 delay register";
    prefix = "ch1_delay";
    field {
      name = "bits";
      prefix = "bits";
      type = SLV;
      size = 32;
    };
  };

  reg {
    name = "CH2 delay register";
    prefix = "ch2_delay";
    field {
      name = "bits";
      prefix = "bits";
      type = SLV;
      size = 32;
    };
  };

  reg {
    name = "CH3 delay register";
    prefix = "ch3_delay";
    field {
      name = "bits";
      prefix = "bits";
      type = SLV;
      size = 32;
    };
  };

  reg {
    name = "CH4 delay register";
    prefix = "ch4_delay";
    field {
      name = "bits";
      prefix = "bits";
      type = SLV;
      size = 32;
    };
  };

  reg {
    name = "CH5 delay register";
    prefix = "ch5_delay";
    field {
      name = "bits";
      prefix = "bits";
      type = SLV;
      size = 32;
    };
  };

  reg {
    name = "CH6 delay register";
    prefix = "ch6_delay";
    field {
      name = "bits";
      prefix = "bits";
      type = SLV;
      size = 32;
    };
  };

  reg {
    name = "CH1 pulse width register";
    prefix = "ch1_pwidth";
    field {
      name = "bits";
      prefix = "bits";
      type = SLV;
      size = 32;
    };
  };

  reg {
    name = "CH2 pulse width register";
    prefix = "ch2_pwidth";
    field {
      name = "bits";
      prefix = "bits";
      type = SLV;
      size = 32;
    };
  };

  reg {
    name = "CH3 pulse width register";
    prefix = "ch3_pwidth";
    field {
      name = "bits";
      prefix = "bits";
      type = SLV;
      size = 32;
    };
  };

  reg {
    name = "CH4 pulse width register";
    prefix = "ch4_pwidth";
    field {
      name = "bits";
      prefix = "bits";
      type = SLV;
      size = 32;
    };
  };

  reg {
    name = "CH5 pulse width register";
    prefix = "ch5_pwidth";
    field {
      name = "bits";
      prefix = "bits";
      type = SLV;
      size = 32;
    };
  };

  reg {
    name = "CH6 pulse width register";
    prefix = "ch6_pwidth";
    field {
      name = "bits";
      prefix = "bits";
      type = SLV;
      size = 32;
    };
  };

  reg {
    name = "CH1 frequency register";
    prefix = "ch1_freq";
    field {
      name = "bits";
      prefix = "bits";
      type = SLV;
      size = 32;
    };
  };

  reg {
    name = "CH2 frequency register";
    prefix = "ch2_freq";
    field {
      name = "bits";
      prefix = "bits";
      type = SLV;
      size = 32;
    };
  };

  reg {
    name = "CH3 frequency register";
    prefix = "ch3_freq";
    field {
      name = "bits";
      prefix = "bits";
      type = SLV;
      size = 32;
    };
  };

  reg {
    name = "CH4 frequency register";
    prefix = "ch4_freq";
    field {
      name = "bits";
      prefix = "bits";
      type = SLV;
      size = 32;
    };
  };

  reg {
    name = "CH5 frequency register";
    prefix = "ch5_freq";
    field {
      name = "bits";
      prefix = "bits";
      type = SLV;
      size = 32;
    };
  };

  reg {
    name = "CH6 frequency register";
    prefix = "ch6_freq";
    field {
      name = "bits";
      prefix = "bits";
      type = SLV;
      size = 32;
    };
  };

};
