##--==============================================================================
##-- CERN (BE-CO-HT)
##-- Glitch filter with selectable length
##--==============================================================================
##--
##-- author: Theodor Stana (t.stana@cern.ch)
##--         Carlos-Gil Soriano
##--
##-- date of creation: 2013-04-26
##--
##-- version: 1.0
##--
##-- description:
##--    This file contains the pin definitions for the CONV-TTL-BLO FPGA. The pin
##--    names reflect those of net names at the schematic level. To keep to CERN
##--    coding standards (http://www.ohwr.org/documents/24) and make the code more
##--    readable, the pin names have been lowercased and the pin type is indicated
##--    by its suffix. The suffix "_i" indicates an input pin, "_o" an output pin
##--    and "_b" a bidirectional pin.
##--
##--    An example of net name change is given below:
##--        LED_WR_OWNADDR_I2C -> led_wr_ownaddr_i2c_o
##--
##--    Apart from this, some pins have been renamed completely and do not resemble
##--    the schematics. These pins are:
##--        TTL/INV_TTL_N -> ttl_switch_n_i
##--
##-- dependencies:
##--
##-- references:
##--
##--==============================================================================
##-- GNU LESSER GENERAL PUBLIC LICENSE
##--==============================================================================
##-- This source file is free software; you can redistribute it and/or modify it
##-- under the terms of the GNU Lesser General Public License as published by the
##-- Free Software Foundation; either version 2.1 of the License, or (at your
##-- option) any later version. This source is distributed in the hope that it
##-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
##-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
##-- See the GNU Lesser General Public License for more details. You should have
##-- received a copy of the GNU Lesser General Public License along with this
##-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
##--==============================================================================
##-- last changes:
##--    2013-04-26   Theodor Stana     t.stana@cern.ch     File modified
##--==============================================================================
##-- TODO: -
##--==============================================================================
##-----------------------------------------------------------------------------
##-- Default attributes
##--
##-- IOSTANDARD = "LVCMOS25"
##-- SLEW       = "SLOW"
##-- DRIVE      = "12"
##-----------------------------------------------------------------------------

#NET "rst_i" LOC = N20;
#NET "rst_i" IOSTANDARD = "LVCMOS33";
#NET "fpga_sysreset_n_i"  LOC = L20;
NET "mr_n_o" LOC = T22;
NET "mr_n_o" IOSTANDARD = LVCMOS33;

NET "clk20_vcxo_i" LOC = E16;
NET "clk20_vcxo_i" TNM_NET = "clk20_vcxo_i";
TIMESPEC TSCLK20 = PERIOD "clk20_vcxo_i" 20 MHz HIGH 50 %;

##=============================================================================
##--        FRONT PANEL TTLs
##=============================================================================
##-----------------------------------------------------------------------------
##-- Status LEDs
##-----------------------------------------------------------------------------
NET "led_ctrl0_o" LOC = M18;
NET "led_ctrl0_o" IOSTANDARD = LVCMOS33;

NET "led_ctrl0_oen_o" LOC = T20;
NET "led_ctrl0_oen_o" IOSTANDARD = LVCMOS33;

NET "led_ctrl1_o" LOC = M17;
NET "led_ctrl1_o" IOSTANDARD = LVCMOS33;

NET "led_ctrl1_oen_o" LOC = U19;
NET "led_ctrl1_oen_o" IOSTANDARD = LVCMOS33;

NET "led_multicast_2_0_o" LOC = P16;
NET "led_multicast_2_0_o" IOSTANDARD = LVCMOS33;

NET "led_multicast_3_1_o" LOC = P17;
NET "led_multicast_3_1_o" IOSTANDARD = LVCMOS33;

NET "led_wr_gmt_ttl_ttln_o" LOC = N16;
NET "led_wr_gmt_ttl_ttln_o" IOSTANDARD = LVCMOS33;

NET "led_wr_link_syserror_o" LOC = R15;
NET "led_wr_link_syserror_o" IOSTANDARD = LVCMOS33;

NET "led_wr_ok_syspw_o" LOC = R16;
NET "led_wr_ok_syspw_o" IOSTANDARD = LVCMOS33;

NET "led_wr_ownaddr_i2c_o" LOC = N15;
NET "led_wr_ownaddr_i2c_o" IOSTANDARD = LVCMOS33;

##-----------------------------------------------------------------------------
##-- Front channel LEDs
##-----------------------------------------------------------------------------
NET "pulse_front_led_n_o[1]" LOC = H5;
NET "pulse_front_led_n_o[1]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[1]" DRIVE = 4;
NET "pulse_front_led_n_o[1]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[2]" LOC = J6;
NET "pulse_front_led_n_o[2]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[2]" DRIVE = 4;
NET "pulse_front_led_n_o[2]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[3]" LOC = K6;
NET "pulse_front_led_n_o[3]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[3]" DRIVE = 4;
NET "pulse_front_led_n_o[3]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[4]" LOC = K5;
NET "pulse_front_led_n_o[4]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[4]" DRIVE = 4;
NET "pulse_front_led_n_o[4]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[5]" LOC = M7;
NET "pulse_front_led_n_o[5]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[5]" DRIVE = 4;
NET "pulse_front_led_n_o[5]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[6]" LOC = M6;
NET "pulse_front_led_n_o[6]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[6]" DRIVE = 4;
NET "pulse_front_led_n_o[6]" SLEW = QUIETIO;

##-----------------------------------------------------------------------------
##-- Rear LEDs
##-----------------------------------------------------------------------------
NET "pulse_rear_led_n_o[1]" LOC = AB17;
NET "pulse_rear_led_n_o[1]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[1]" DRIVE = 4;
NET "pulse_rear_led_n_o[1]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[2]" LOC = AB19;
NET "pulse_rear_led_n_o[2]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[2]" DRIVE = 4;
NET "pulse_rear_led_n_o[2]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[3]" LOC = AA16;
NET "pulse_rear_led_n_o[3]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[3]" DRIVE = 4;
NET "pulse_rear_led_n_o[3]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[4]" LOC = AA18;
NET "pulse_rear_led_n_o[4]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[4]" DRIVE = 4;
NET "pulse_rear_led_n_o[4]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[5]" LOC = AB16;
NET "pulse_rear_led_n_o[5]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[5]" DRIVE = 4;
NET "pulse_rear_led_n_o[5]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[6]" LOC = AB18;
NET "pulse_rear_led_n_o[6]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[6]" DRIVE = 4;
NET "pulse_rear_led_n_o[6]" SLEW = QUIETIO;

##-----------------------------------------------------------------------------
##-- TTL trigger I/O
##-----------------------------------------------------------------------------
NET "fpga_input_ttl_n_i[1]" LOC = T2;
NET "fpga_input_ttl_n_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[1]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[2]" LOC = U3;
NET "fpga_input_ttl_n_i[2]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[2]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[3]" LOC = V5;
NET "fpga_input_ttl_n_i[3]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[3]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[4]" LOC = W4;
NET "fpga_input_ttl_n_i[4]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[4]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[5]" LOC = T6;
NET "fpga_input_ttl_n_i[5]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[5]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[6]" LOC = T3;
NET "fpga_input_ttl_n_i[6]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[6]" CLOCK_DEDICATED_ROUTE = FALSE;

NET "fpga_out_ttl_o[1]" LOC = C1;
NET "fpga_out_ttl_o[1]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[2]" LOC = F2;
NET "fpga_out_ttl_o[2]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[3]" LOC = F5;
NET "fpga_out_ttl_o[3]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[4]" LOC = H4;
NET "fpga_out_ttl_o[4]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[5]" LOC = J4;
NET "fpga_out_ttl_o[5]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[6]" LOC = H2;
NET "fpga_out_ttl_o[6]" IOSTANDARD = LVCMOS33;

##-----------------------------------------------------------------------------
##-- Inverted TTL I/O
##-----------------------------------------------------------------------------
NET "inv_in_n_i[1]" LOC = V2;
NET "inv_in_n_i[1]" IOSTANDARD = LVCMOS33;
NET "inv_in_n_i[1]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "inv_in_n_i[2]" LOC = W3;
NET "inv_in_n_i[2]" IOSTANDARD = LVCMOS33;
NET "inv_in_n_i[2]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "inv_in_n_i[3]" LOC = Y2;
NET "inv_in_n_i[3]" IOSTANDARD = LVCMOS33;
NET "inv_in_n_i[3]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "inv_in_n_i[4]" LOC = AA2;
NET "inv_in_n_i[4]" IOSTANDARD = LVCMOS33;
NET "inv_in_n_i[4]" CLOCK_DEDICATED_ROUTE = FALSE;

NET "inv_out_o[1]" LOC = J3;
NET "inv_out_o[1]" IOSTANDARD = LVCMOS33;
NET "inv_out_o[2]" LOC = L3;
NET "inv_out_o[2]" IOSTANDARD = LVCMOS33;
NET "inv_out_o[3]" LOC = M3;
NET "inv_out_o[3]" IOSTANDARD = LVCMOS33;
NET "inv_out_o[4]" LOC = P2;
NET "inv_out_o[4]" IOSTANDARD = LVCMOS33;


##=============================================================================
##--          RTM signals
##=============================================================================
##-----------------------------------------------------------------------------
##-- Blocking I/O
##-----------------------------------------------------------------------------
NET "fpga_blo_in_i[1]" LOC = Y9;
NET "fpga_blo_in_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_blo_in_i[2]" LOC = AA10;
NET "fpga_blo_in_i[2]" IOSTANDARD = LVCMOS33;
NET "fpga_blo_in_i[3]" LOC = W12;
NET "fpga_blo_in_i[3]" IOSTANDARD = LVCMOS33;
NET "fpga_blo_in_i[4]" LOC = AA6;
NET "fpga_blo_in_i[4]" IOSTANDARD = LVCMOS33;
NET "fpga_blo_in_i[5]" LOC = Y7;
NET "fpga_blo_in_i[5]" IOSTANDARD = LVCMOS33;
NET "fpga_blo_in_i[6]" LOC = AA8;
NET "fpga_blo_in_i[6]" IOSTANDARD = LVCMOS33;

NET "fpga_trig_blo_o[1]" LOC = W9;
NET "fpga_trig_blo_o[1]" IOSTANDARD = LVCMOS33;
NET "fpga_trig_blo_o[2]" LOC = T10;
NET "fpga_trig_blo_o[2]" IOSTANDARD = LVCMOS33;
NET "fpga_trig_blo_o[3]" LOC = V7;
NET "fpga_trig_blo_o[3]" IOSTANDARD = LVCMOS33;
NET "fpga_trig_blo_o[4]" LOC = U9;
NET "fpga_trig_blo_o[4]" IOSTANDARD = LVCMOS33;
NET "fpga_trig_blo_o[5]" LOC = T8;
NET "fpga_trig_blo_o[5]" IOSTANDARD = LVCMOS33;
NET "fpga_trig_blo_o[6]" LOC = R9;
NET "fpga_trig_blo_o[6]" IOSTANDARD = LVCMOS33;

##=============================================================================
##--       VME CONNECTOR SIGNALS
##=============================================================================
##-----------------------------------------------------------------------------
##-- I2C lines
##-----------------------------------------------------------------------------
NET "scl_i" LOC = F19;
NET "scl_i" IOSTANDARD = LVCMOS33;
NET "scl_o" LOC = E20;
NET "scl_o" IOSTANDARD = LVCMOS33;
NET "scl_o" DRIVE = 4;
NET "scl_oe_o" LOC = H18;
NET "scl_oe_o" IOSTANDARD = LVCMOS33;
NET "scl_oe_o" DRIVE = 4;
#  NET "scl_oe_o"                 PULLDOWN;
NET "sda_i" LOC = G20;
NET "sda_i" IOSTANDARD = LVCMOS33;
NET "sda_o" LOC = F20;
NET "sda_o" IOSTANDARD = LVCMOS33;
NET "sda_o" SLEW = FAST;
NET "sda_o" DRIVE = 4;
#  NET "sda_o"                  PULLUP;
NET "sda_oe_o" LOC = J19;
NET "sda_oe_o" IOSTANDARD = LVCMOS33;
NET "sda_oe_o" SLEW = FAST;
NET "sda_oe_o" DRIVE = 4;
#  NET "sda_oe_o"                 PULLDOWN;

##-----------------------------------------------------------------------------
##-- Geographical Address
##-----------------------------------------------------------------------------
NET "fpga_ga_i[0]" LOC = H20;
NET "fpga_ga_i[0]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[1]" LOC = J20;
NET "fpga_ga_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[2]" LOC = K19;
NET "fpga_ga_i[2]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[3]" LOC = K20;
NET "fpga_ga_i[3]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[4]" LOC = L19;
NET "fpga_ga_i[4]" IOSTANDARD = LVCMOS33;
NET "fpga_gap_i" LOC = H19;
NET "fpga_gap_i" IOSTANDARD = LVCMOS33;

##-----------------------------------------------------------------------------
##-- ROM memory
##-----------------------------------------------------------------------------
NET "fpga_prom_cclk_o" LOC = Y20;
NET "fpga_prom_cclk_o" IOSTANDARD = LVCMOS33;
NET "fpga_prom_cso_b_n_o" LOC = AA3;
NET "fpga_prom_cso_b_n_o" IOSTANDARD = LVCMOS33;
NET "fpga_prom_miso_i" LOC = AA20;
NET "fpga_prom_miso_i" IOSTANDARD = LVCMOS33;
NET "fpga_prom_mosi_o" LOC = AB20;
NET "fpga_prom_mosi_o" IOSTANDARD = LVCMOS33;

##=============================================================================
##--          WHITE RABBIT
##=============================================================================
##-----------------------------------------------------------------------------
##-- Thermo for UID
##-----------------------------------------------------------------------------
NET "thermometer_b" LOC = B1;
NET "thermometer_b" IOSTANDARD = LVCMOS33;

##-----------------------------------------------------------------------------
##-- DAC control
##-----------------------------------------------------------------------------
NET "fpga_plldac1_din_o" LOC = AB14;
NET "fpga_plldac1_din_o" IOSTANDARD = LVCMOS33;
NET "fpga_plldac1_sclk_o" LOC = AA14;
NET "fpga_plldac1_sclk_o" IOSTANDARD = LVCMOS33;
NET "fpga_plldac1_sync_n_o" LOC = AB15;
NET "fpga_plldac1_sync_n_o" IOSTANDARD = LVCMOS33;

NET "fpga_plldac2_din_o" LOC = W14;
NET "fpga_plldac2_din_o" IOSTANDARD = LVCMOS33;
NET "fpga_plldac2_sclk_o" LOC = Y14;
NET "fpga_plldac2_sclk_o" IOSTANDARD = LVCMOS33;
NET "fpga_plldac2_sync_n_o" LOC = W13;
NET "fpga_plldac2_sync_n_o" IOSTANDARD = LVCMOS33;

##-----------------------------------------------------------------------------
##-- SFP connection
##-----------------------------------------------------------------------------
NET "fpga_sfp_los_i" LOC = G3;
NET "fpga_sfp_los_i" IOSTANDARD = LVCMOS33;
NET "fpga_sfp_mod_def0_i" LOC = K8;
NET "fpga_sfp_mod_def0_i" IOSTANDARD = LVCMOS33;
NET "fpga_sfp_rate_select_o" LOC = C4;
NET "fpga_sfp_rate_select_o" IOSTANDARD = LVCMOS33;
NET "fpga_sfp_mod_def1_b" LOC = G4;
NET "fpga_sfp_mod_def1_b" IOSTANDARD = LVCMOS33;

NET "fpga_sfp_mod_def2_b" LOC = F3;
NET "fpga_sfp_mod_def2_b" IOSTANDARD = LVCMOS33;
NET "fpga_sfp_tx_disable_o" LOC = E4;
NET "fpga_sfp_tx_disable_o" IOSTANDARD = LVCMOS33;
NET "fpga_sfp_tx_fault_i" LOC = D2;
NET "fpga_sfp_tx_fault_i" IOSTANDARD = LVCMOS33;

###-----------------------------------------------------------------------------
###-- FPGA MGT lines
###-----------------------------------------------------------------------------
#NET "fpga_mgt_clk0_p_i" LOC = A10;
#NET "fpga_mgt_clk0_n_i" LOC = B10;
#
#NET "mgt_sfp_rx0_p_i" LOC = D7;
#NET "mgt_sfp_rx0_n_i" LOC = C7;
#
#NET "mgt_sfp_tx0_p_o" LOC = B6;
#NET "mgt_sfp_tx0_n_o" LOC = A6;

###=============================================================================
###--         ADDITIONAL PINS
###=============================================================================
NET "fpga_oe_o" LOC = R3;
NET "fpga_oe_o" IOSTANDARD = LVCMOS33;
NET "fpga_oe_o" DRIVE = 4;
NET "fpga_oe_o" SLEW = QUIETIO;

NET "fpga_blo_oe_o" LOC = P5;
NET "fpga_blo_oe_o" IOSTANDARD = LVCMOS33;
NET "fpga_blo_oe_o" DRIVE = 4;
NET "fpga_blo_oe_o" SLEW = QUIETIO;

NET "fpga_trig_ttl_oe_o" LOC = N3;
NET "fpga_trig_ttl_oe_o" IOSTANDARD = LVCMOS33;
NET "fpga_trig_ttl_oe_o" DRIVE = 4;
NET "fpga_trig_ttl_oe_o" SLEW = QUIETIO;

NET "fpga_inv_oe_o" LOC = P6;
NET "fpga_inv_oe_o" IOSTANDARD = LVCMOS33;
NET "fpga_inv_oe_o" DRIVE = 4;
NET "fpga_inv_oe_o" SLEW = QUIETIO;

##-----------------------------------------------------------------------------
##-- Configuration Switches
##-----------------------------------------------------------------------------
NET "extra_switch_n_i[1]" LOC = F22;
NET "extra_switch_n_i[1]" IOSTANDARD = LVCMOS33;
NET "extra_switch_n_i[2]" LOC = G22;
NET "extra_switch_n_i[2]" IOSTANDARD = LVCMOS33;
NET "extra_switch_n_i[3]" LOC = H21;
NET "extra_switch_n_i[3]" IOSTANDARD = LVCMOS33;
NET "extra_switch_n_i[4]" LOC = H22;
NET "extra_switch_n_i[4]" IOSTANDARD = LVCMOS33;
NET "extra_switch_n_i[5]" LOC = J22;
NET "extra_switch_n_i[5]" IOSTANDARD = LVCMOS33;
NET "extra_switch_n_i[6]" LOC = K21;
NET "extra_switch_n_i[6]" IOSTANDARD = LVCMOS33;
NET "extra_switch_n_i[7]" LOC = K22;
NET "extra_switch_n_i[7]" IOSTANDARD = LVCMOS33;
NET "ttl_switch_n_i" LOC = L22;
NET "ttl_switch_n_i" IOSTANDARD = LVCMOS33;

##-----------------------------------------------------------------------------
##-- Motherboard and piggyback IDs
##-----------------------------------------------------------------------------
NET "fpga_rtmm_n_i[0]" LOC = V21;
NET "fpga_rtmm_n_i[0]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmm_n_i[1]" LOC = V22;
NET "fpga_rtmm_n_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmm_n_i[2]" LOC = U22;
NET "fpga_rtmm_n_i[2]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmp_n_i[0]" LOC = W22;
NET "fpga_rtmp_n_i[0]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmp_n_i[1]" LOC = Y22;
NET "fpga_rtmp_n_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmp_n_i[2]" LOC = Y21;
NET "fpga_rtmp_n_i[2]" IOSTANDARD = LVCMOS33;

###-----------------------------------------------------------------------------
###-- General purpose
###-----------------------------------------------------------------------------
# NET "fpga_header_out_n_o[1]"    LOC = F15;
# NET "fpga_header_out_n_o[1]"    IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[2]"    LOC = F16;
# NET "fpga_header_out_n_o[2]"    IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[3]"    LOC = F17;
# NET "fpga_header_out_n_o[3]"    IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[4]"    LOC = F14;
# NET "fpga_header_out_n_o[4]"    IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[5]"    LOC = H14;
# NET "fpga_header_out_n_o[5]"    IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[6]"    LOC = H13;
# NET "fpga_header_out_n_o[6]"    IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[1]"     LOC = A17;
# NET "fpga_header_in_n_i[1]"     IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[2]"     LOC = A18;
# NET "fpga_header_in_n_i[2]"     IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[3]"     LOC = B18;
# NET "fpga_header_in_n_i[3]"     IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[4]"     LOC = A19;
# NET "fpga_header_in_n_i[4]"     IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[5]"     LOC = A20;
# NET "fpga_header_in_n_i[5]"     IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[6]"     LOC = B20;
# NET "fpga_header_in_n_i[6]"     IOSTANDARD = "LVCMOS33";
