--==============================================================================
-- CERN (BE-CO-HT)
-- Converter board registers wbgen2 description file
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation:
--
-- version: 1.0
--
-- description:
--    This file contains the register description for the converter board
--    registers and is to be used as input to the wbgen2 tool for generating
--    an appropriate VHDL file.
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
--    03-05-2014   Theodor Stana     Added GPL header
--==============================================================================
-- TODO: -
--==============================================================================

peripheral {
  name = "Converter board registers";
  hdl_entity = "conv_regs";
  prefix = "reg";


  -- Board ID register
  reg {
    name = "BIDR";
    description = "Board ID Register";
    prefix = "bidr";
    reset_value = "0x54424c4f";
    field {
      name = "ID register bits";
      reset_value = "0x54424c4f";
      type = SLV;
      size = 32;
      access_dev = WRITE_ONLY;
      access_bus = READ_ONLY;
    };
  };


  -- Status register
  reg {
    name = "SR";
    description = "Status Register";
    prefix = "sr";
    field {
      name = "Gateware version";
      description = "Leftmost nibble hex value is major release decimal value \
                     Rightmost nibble hex value is minor release decimal value \
		     e.g. \
		     0x11 -- v1.1 \
		     0x2e -- v2.14";
      prefix = "gwvers";
      type = SLV;
      size = 8;
      access_dev = WRITE_ONLY;
      access_bus = READ_ONLY;
    };
    field {
      name = "Status of on-board switches";
      description = "0 -- switch is ON \
		     1 -- switch is OFF";
      prefix = "switches";
      type = SLV;
      size = 8;
      access_dev = WRITE_ONLY;
      access_bus = READ_ONLY;
    };
    field {
      name = "RTM detection lines~\\cite{rtm-det}";
      description = "0 -- line active \
                     1 -- line inactive";
      prefix = "rtm";
      type = SLV;
      size = 6;
      access_dev = WRITE_ONLY;
      access_bus = READ_ONLY;
    };
    field {
      name = "I2C communication watchdog timeout error";
      description = "1 -- timeout occured \
                     0 -- no timeout \
                     This bit can be cleared by writing a '1' to it";
      prefix     = "i2c_wdto";
      type       = BIT;
      size       = 1;
      access_dev = READ_WRITE;
      access_bus = READ_WRITE;
      load       = LOAD_EXT;
    };
    field {
      name = "White Rabbit present";
      description = "1 -- White Rabbit present \
                     0 -- White Rabbit not present";
      prefix = "wrpres";
      type = BIT;
      access_dev = WRITE_ONLY;
      access_bus = READ_ONLY;
    };
    field {
      name = "I2C communication error";
      description = "1 -- attempted to address non-existing address \
                     0 -- idle \
                     This bit can be cleared by writing a '1' to it";
      prefix = "i2c_err";
      type = BIT;
      access_dev = READ_WRITE;
      access_bus = READ_WRITE;
      load = LOAD_EXT;
    };
    field {
      name = "Pulse missed error";
      description = "1 -- pulse arrived during pulse rejection phase \
                     0 -- idle \
                     This bit can be cleared by writing a '1' to it";
      prefix = "pmisse";
      type = BIT;
      access_dev = READ_WRITE;
      access_bus = READ_WRITE;
      load = LOAD_EXT;
    };
  };


  -- Control Register
  reg {
    name = "CR";
    description = "Control Register";
    prefix = "cr";

    -- Logic reset bits
    field {
      name = "Reset unlock bit";
      description = "1 -- Reset bit unlocked \
                     0 -- Reset bit locked";
      prefix = "rst_unlock";
      type = BIT;
      access_dev = READ_WRITE;
      access_bus = READ_WRITE;
      load = LOAD_EXT;
    };
    field {
      name = "Reset bit";
      description = "1 -- initiate logic reset \
                     0 -- no reset";
      prefix = "rst";
      type = BIT;
      access_bus = READ_WRITE;
      access_dev = READ_WRITE;
      load = LOAD_EXT;
    };
    field {
      name = "Manual Pulse Trigger";
      description = "Write the following sequence to trigger a pulse: \
                     0xde -- Byte 1 of magic sequence \
                     0xad -- Byte 2 of magic sequence \
                     0xbe -- Byte 3 of magic sequence \
                     0xef -- Byte 4 of magic sequence \
		     Number in range 1..6 -- trigger a pulse";
      prefix = "mpt";
      size = 8;
      type = PASS_THROUGH;
    };
  };

  -- Pulse counter registers, R/W access from SysMon
  reg {
    name = "CH1PCR";
    description = "Channel 1 Pulse Counter Register";
    prefix = "ch1pcr";
    field {
      name = "Pulse counter value";
      type = SLV;
      size = 32;
      access_bus = READ_WRITE;
      access_dev = READ_WRITE;
      load = LOAD_EXT;
    };
  };

  reg {
    name = "CH2PCR";
    description = "Channel 2 Pulse Counter Register";
    prefix = "ch2pcr";
    field {
      name = "Pulse counter value";
      type = SLV;
      size = 32;
      access_bus = READ_WRITE;
      access_dev = READ_WRITE;
      load = LOAD_EXT;
    };
  };

  reg {
    name = "CH3PCR";
    description = "Channel 3 Pulse Counter Register";
    prefix = "ch3pcr";
    field {
      name = "Pulse counter value";
      type = SLV;
      size = 32;
      access_bus = READ_WRITE;
      access_dev = READ_WRITE;
      load = LOAD_EXT;
    };
  };

  reg {
    name = "CH4PCR";
    description = "Channel 4 Pulse Counter Register";
    prefix = "ch4pcr";
    field {
      name = "Pulse counter value";
      type = SLV;
      size = 32;
      access_bus = READ_WRITE;
      access_dev = READ_WRITE;
      load = LOAD_EXT;
    };
  };

  reg {
    name = "CH5PCR";
    description = "Channel 5 Pulse Counter Register";
    prefix = "ch5pcr";
    field {
      name = "Pulse counter value";
      type = SLV;
      size = 32;
      access_bus = READ_WRITE;
      access_dev = READ_WRITE;
      load = LOAD_EXT;
    };
  };

  reg {
    name = "CH6PCR";
    description = "Channel 6 Pulse Counter Register";
    prefix = "ch6pcr";
    field {
      name = "Pulse counter value";
      type = SLV;
      size = 32;
      access_bus = READ_WRITE;
      access_dev = READ_WRITE;
      load = LOAD_EXT;
    };
  };

  reg {
    name = "TVLR";
    description = "Time Value Low Register";
    prefix = "tvlr";
    field {
      name = "TAI seconds counter bits 31..0";
      description = "Writing this field resets the internal cycles counter.";
      type = SLV;
      size = 32;
      access_bus = READ_WRITE;
      access_dev = READ_WRITE;
      load = LOAD_EXT;
    };
  };

  reg {
    name = "TVHR";
    description = "Time Value High Register";
    prefix = "tvhr";
    field {
      name = "TAI seconds counter bits 39..32";
      description = "Writing this field resets the internal cycles counter.";
      type = SLV;
      size = 8;
      access_bus = READ_WRITE;
      access_dev = READ_WRITE;
      load = LOAD_EXT;
    };
  };

  reg {
    name = "TBMR";
    description = "Tag Buffer Meta Register";
    prefix = "tbmr";
    field {
      name = "Channel mask";
      description = "Mask for the channel(s) that triggered time-tag storage: \
                     bit 0 -- channel 1 \
		     bit 1 -- channel 2 \
		     ... \
		     bit 5 -- channel 6";
      prefix = "chan";
      type = SLV;
      size = 6;
      access_dev = WRITE_ONLY;
      access_bus = READ_ONLY;
    };
    field {
      name = "White Rabbit present";
      description = "1 - Current time tag generated with White Rabbit \
                     0 - Current time tag generated with internal counter";
      prefix = "wrtag";
      type = BIT;
      align = 31;
      access_dev = WRITE_ONLY;
      access_bus = READ_ONLY;
    };
  };

  reg {
    name = "TBCYR";
    description = "Tag Buffer Cycles Register";
    prefix = "tbcyr";
    field {
      name = "Cycles counter";
      description = "Value of the 8-ns cycles counter when time tag was taken.";
      type = SLV;
      size = 28;
      access_dev = WRITE_ONLY;
      access_bus = READ_ONLY;
    };
  };

  reg {
    name = "TBTLR";
    description = "Tag Buffer TAI Low Register";
    prefix = "tbtlr";
    field {
      name = "Lower part of TAI seconds counter";
      description = "Value of the TAI seconds counter bits 31..0 when time tag was taken.";
      type = SLV;
      size = 32;
      access_dev = WRITE_ONLY;
      access_bus = READ_ONLY;
    };
  };

  reg {
    name = "TBTHR";
    description = "Tag Buffer TAI High Register";
    prefix = "tbthr";
    field {
      name = "Upper part of TAI seconds counter";
      description = "Value of the TAI seconds counter bits 39..32 when time tag was taken.";
      type = SLV;
      size = 8;
      access_dev = WRITE_ONLY;
      access_bus = READ_ONLY;
    };
  };

  reg {
    name = "TBCSR";
    description = "Tag Buffer Control and Status Register";
    prefix = "tbcsr";
    field {
      name = "Buffer counter";
      prefix = "usedw";
      description = "Number of samples in the ring buffer";
      type = SLV;
      size = 7;
      access_dev = WRITE_ONLY;
      access_bus = READ_ONLY;
    };
    field {
      name = "Buffer full";
      description = "1 -- buffer full \
      0 -- buffer is not full";
      prefix = "full";
      type = BIT;
      align = 16;
      access_dev = WRITE_ONLY;
      access_bus = READ_ONLY;
    };
    field {
      name = "Buffer empty";
      description = "1 -- buffer empty\
      0 -- buffer is not empty";
      prefix = "empty";
      type = BIT;
      access_dev = WRITE_ONLY;
      access_bus = READ_ONLY;
    };
    field {
      name = "Clear tag buffer";
      description = "1 -- clear\
      0 -- no effect";
      prefix = "clr";
      type = BIT;
      access_dev = READ_WRITE;
      access_bus = READ_WRITE;
      load = LOAD_EXT;
    };
  };

};
