- 26 Feb, 2015 3 commits
-
-
Theodor-Adrian Stana authored
- connecting WRPC's SPI outputs to the conv-common-gw flash outputs - the flash outputs are multiplexed between the WRPC and the multiboot logic (MultiBoot logic has priority) - re-generating the code for local PPS generation when the hardware one-wire master is generated (gen_with_therm) - the PPS output is obtained from the WRPC when WR is present - connecting the WRPC's timing outputs to the time-tagging core
-
Theodor-Adrian Stana authored
-
Theodor-Adrian Stana authored
-
- 25 Feb, 2015 1 commit
-
-
Theodor-Adrian Stana authored
-
- 24 Feb, 2015 1 commit
-
-
Theodor-Adrian Stana authored
-
- 23 Feb, 2015 2 commits
-
-
Theodor-Adrian Stana authored
-
Theodor-Adrian Stana authored
-
- 18 Feb, 2015 1 commit
-
-
Theodor-Adrian Stana authored
-
- 15 Feb, 2015 1 commit
-
-
Theodor-Adrian Stana authored
-
- 26 Jan, 2015 2 commits
-
-
Theodor-Adrian Stana authored
-
Theodor-Adrian Stana authored
This means that g_with_thermometer is now used in the HDL and the one-wire master core is no longer used when g_with_thermometer is set to false. The HDL also makes sure the WB ack signal is set high all the time when g_with_thermometer is false. In addition, the limitation on the pulse width generic was removed from the conv_common_gw entity declaration.
-
- 11 Dec, 2014 3 commits
-
-
Theodor-Adrian Stana authored
-
Theodor-Adrian Stana authored
The description of the CSR.RST bit has been made clearer to show that it is only active when CSR.RST_UNLOCK = '1'.
-
Theodor-Adrian Stana authored
-
- 26 Sep, 2014 2 commits
-
-
Theodor-Adrian Stana authored
-
Theodor-Adrian Stana authored
-
- 25 Sep, 2014 1 commit
-
-
Theodor-Adrian Stana authored
OSWR also now contains 32 bits, to allow for 32 switches in addition to the existing 8 general-purpose ones.
-
- 24 Sep, 2014 1 commit
-
-
Theodor-Adrian Stana authored
The 125 MHz domain registers are loaded only once the 20 MHz clock domain registers are loaded. Like this, we avoid having different values in the registers in the two clock domains.
-
- 29 Aug, 2014 6 commits
-
-
Theodor-Adrian Stana authored
-
Theodor-Adrian Stana authored
-
Theodor-Adrian Stana authored
-
Theodor-Adrian Stana authored
-
Theodor-Adrian Stana authored
This makes the doc and module more generic. The modification will be made in the code as well.
-
Theodor-Adrian Stana authored
Also added link to OHWR Wiki page for project examples in the same section.
-
- 25 Aug, 2014 1 commit
-
-
Theodor-Adrian Stana authored
This is to make sure no readouts of erroneous values from this registers occur due to the register value not being stable at the time the WB read cycle is requested.
-
- 22 Aug, 2014 4 commits
-
-
Theodor-Adrian Stana authored
-
Theodor-Adrian Stana authored
-
Theodor-Adrian Stana authored
The pulse synchronizer for the latest timestamp load signal implemented as part of the previous commit was not working, due to a wrongly-connected signal. The appropriate signal was connected and the pulse synchronization mechanism seems to work.
-
Theodor-Adrian Stana authored
The pulse synchronizer makes sure the load pulse to the 125 MHz clock domain registers generates a pulse to load the registers in the 20 MHz clock domain, which are the registers that are read via I2C.
-
- 21 Aug, 2014 1 commit
-
-
Theodor-Adrian Stana authored
The sys err port also activates on PMISSE errors from any channels, which was an omission in the previous commits, since I was working mainly on the RS-485 repeater. Now, the interface is clearer and easier to use. Just connect led_syserr_o to the ERR bicolor LED on the board.
-
- 20 Aug, 2014 2 commits
-
-
Theodor-Adrian Stana authored
The memory map has been updated to include the thermometer SDB descriptor. Appendix B was added, containing guidelines on how to implement a pulse repeater with more than six channels.
-
Theodor-Adrian Stana authored
-
- 18 Aug, 2014 2 commits
-
-
Theodor-Adrian Stana authored
-
Theodor-Adrian Stana authored
- added g_with_pulse_cnt - added g_with_pulse_timetag - added SR.PMISSE bit for each of the six channels - made logic more customizable for g_nr_chans < 6 - doc: added reminder to treat board switches in Overview section
-
- 14 Aug, 2014 1 commit
-
-
Theodor-Adrian Stana authored
-
- 08 Aug, 2014 1 commit
-
-
Theodor-Adrian Stana authored
-
- 07 Aug, 2014 1 commit
-
-
Theodor-Adrian Stana authored
Also, update corresponding conv-regs.wb
-
- 06 Aug, 2014 1 commit
-
-
Theodor-Adrian Stana authored
In addition, the base address of conv-regs has been changed to three hex digits
-
- 05 Aug, 2014 2 commits
-
-
Theodor-Adrian Stana authored
- BIDR default reset value - active values of several SR fields (SWITCHES, RTM, etc.) - formatting in some registers - also adapted .wb file to account for this
-
Theodor-Adrian Stana authored
-