1. 26 Jan, 2015 2 commits
    • Theodor-Adrian Stana's avatar
    • Theodor-Adrian Stana's avatar
      Solved OHWR issue #1047 · cd7e4c49
      Theodor-Adrian Stana authored
      This means that g_with_thermometer is now used in the HDL and the one-wire
      master core is no longer used when g_with_thermometer is set to false. The HDL
      also makes sure the WB ack signal is set high all the time when
      g_with_thermometer is false.
      In addition, the limitation on the pulse width generic was removed from the
      conv_common_gw entity declaration.
  2. 11 Dec, 2014 3 commits
  3. 26 Sep, 2014 2 commits
  4. 25 Sep, 2014 1 commit
  5. 24 Sep, 2014 1 commit
    • Theodor-Adrian Stana's avatar
      Changed LTSR load policy · 885b948c
      Theodor-Adrian Stana authored
      The 125 MHz domain registers are loaded only once the 20 MHz clock domain
      registers are loaded. Like this, we avoid having different values in the
      registers in the two clock domains.
  6. 29 Aug, 2014 6 commits
  7. 25 Aug, 2014 1 commit
  8. 22 Aug, 2014 4 commits
  9. 21 Aug, 2014 1 commit
    • Theodor-Adrian Stana's avatar
      Port change: led_i2c_err_o is now led_syserr_o · e1bfd7b0
      Theodor-Adrian Stana authored
      The sys err port also activates on PMISSE errors from any channels,
      which was an omission in the previous commits, since I was working mainly
      on the RS-485 repeater.
      Now, the interface is clearer and easier to use. Just connect led_syserr_o
      to the ERR bicolor LED on the board.
  10. 20 Aug, 2014 2 commits
  11. 18 Aug, 2014 2 commits
  12. 14 Aug, 2014 1 commit
  13. 08 Aug, 2014 1 commit
  14. 07 Aug, 2014 1 commit
  15. 06 Aug, 2014 1 commit
  16. 05 Aug, 2014 4 commits
  17. 04 Aug, 2014 1 commit
  18. 01 Aug, 2014 1 commit
    • Theodor-Adrian Stana's avatar
      Added package file and made adjustments to output enable logic · 6e1a5f9e
      Theodor-Adrian Stana authored
      The main logic changes are that the output enable lines are now set after
      the internal reset has been spent. This is to make sure that the lines are
      only controlled by the FPGA and no erroneous glitches are generated.
      Other changes include the addition of the RTM detection lines to the
      interface, which are now reflected in the CONV Status Reg, and connecting
      the reset from register line, which was previously unconnected.
      Then, component instantiations and the SDB declaration for conv_regs have
      been moved to the package file (conv_common_gw_pkg).
  19. 31 Jul, 2014 2 commits
  20. 30 Jul, 2014 1 commit
  21. 29 Jul, 2014 1 commit
    • Theodor-Adrian Stana's avatar
      Made interface simpler and added pulse inhibit on no fixed width pulse side as well · a04f0dc8
      Theodor-Adrian Stana authored
      The simpler interface is by means of providing only one pulse and pulse LED port
      per channel (both inputa and output). If there's an RTM involved, the splitting
      should be done outside the module.
      Then, the pulse inhibit is moved outside the g_with_fixed_pwidth block and provided
      in the generally synthesizable block, so it gets synthesized regardless of the value
      of the g_with_fixed_pwidth generic.
  22. 25 Jul, 2014 1 commit