Changed manual the value of the reset timer appropriately for
simulation. This is a temporary solution. a simulation generic
is needed to make the conv_common_gw work for both, simulation
and synthesis (similar to WRPC, etc)

It is based on the testbench in conv-ttl-blo-gw/sim/Release
and includes
- top-level (testbench.vhd) with DUT and i2c facilites (next)
- i2c_bus_model.vhd to connect DUT with i2c_master_and_driver
- i2c_master_and_driver that allows access to DUT's register via i2c
- read_i2c procedures to easily use the driver (write_i2c semi-ready)

File contained instructions to modify wbgen2 generated vhdl. This is no longer required as explained in the file

Modified top files to use more generic front names rather than signal types that are more specific to a particular board, Eg: ttl and blo for conv-ttl-blo. Now using front and rear instead. this can now be reused with conv-ttl-rs485

Modified wbgen script to remove any references to ttl or blo signal types. Sole reference to front or rear signals

Some ports have been renamed. Notable some of the sfp ports, and a start on trying to replace all signal references, ttl or blo, with reference to input type, front or rear.

Small bug fixes to new version of conv_pulse_gen.vhd. Bug in pulse counters in top file conv_common_gw fixed. pulse counters were not resetting after the external loading of new values.

Major changes: conv_pulse_gen.vhd has been almost completely rewritten. Also top file now uses pulse periods instead of duty cycles, this is to be able to cope with none round duty cycles

Modified pulse counting process to use a Flancter based counter which is able to count very fast pulses

Cleaned up code with very small modifications to reflect new memory map with hardware revision number

Code further modified after review as was not behaving coorectly for very high frequencies with very small duty cycle

Previsous version had some bugs. Bugs fixed plus modified FSM by removing temp_rise processing from FSM and generating it from separate process.

Two important changes to wishbone file: 1-the TBMR read request output reg_tb_rd_req_p_o is presend in the conv_regs.vhd in the master branch, but no indication of how it has been added in the corresponding *.wb file. The conclusion was that the *.vhd file was either generated from a different *.wb file or has been modified manually. The right expression, ack_read=port_out, is now used in the *.wb file and fixes the problem. 2-Memory map has been modified to add PCB version information. Additionally a new type of error has been defined: flim_err and fwdg_err. To do so, a new error register has been created to put all error types together. The SR register now provides the hw version in addition to previous information, apart from errors.

Implementation post-review. Main changes are to pull the falling and rising edges of the asynch pulses directly from the conv_pulse_gen module as outputs and input those the burst controller. The top files have been modified accordingly. Also the pulse output now is correctly generated at the poutput port depending on PCB version and pulse width selection

Updated common gateware with distinct burst mode enable,from PCB version on the PCB, and pulse width select input coming from the dip switch.

Now using an FSM to hadel pulse repetition and rejection. Thermal model constant decrement steps are now a generic rather than a signal