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Converter Common Gateware
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a292ca9e
Commit
a292ca9e
authored
Feb 14, 2017
by
Denia Bouhired-Ferrag
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Started some work to integrate chipscope
parent
3848a6c9
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2 changed files
with
80 additions
and
8 deletions
+80
-8
conv_common_gw.vhd
top/conv_common_gw.vhd
+46
-8
conv_common_gw_pkg.vhd
top/conv_common_gw_pkg.vhd
+34
-0
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top/conv_common_gw.vhd
View file @
a292ca9e
...
...
@@ -249,7 +249,7 @@ architecture arch of conv_common_gw is
-- Number of Wishbone masters and slaves, for wb_crossbar
constant
c_nr_masters
:
natural
:
=
1
;
constant
c_nr_slaves
:
natural
:
=
3
;
constant
c_nr_slaves
:
natural
:
=
2
;
-- slave order definitions
constant
c_slv_conv_regs
:
natural
:
=
0
;
...
...
@@ -259,7 +259,7 @@ architecture arch of conv_common_gw is
-- base address definitions
constant
c_addr_conv_regs
:
t_wishbone_address
:
=
x"00000000"
;
constant
c_addr_multiboot
:
t_wishbone_address
:
=
x"00000100"
;
constant
c_addr_onewire_mst
:
t_wishbone_address
:
=
x"00000200"
;
--
constant c_addr_onewire_mst : t_wishbone_address := x"00000200";
constant
c_addr_sdb
:
t_wishbone_address
:
=
x"00000f00"
;
...
...
@@ -268,9 +268,9 @@ architecture arch of conv_common_gw is
constant
c_sdb_layout
:
t_sdb_record_array
(
c_nr_slaves
-1
downto
0
)
:
=
(
c_slv_conv_regs
=>
f_sdb_embed_device
(
c_conv_regs_sdb
,
c_addr_conv_regs
),
c_slv_multiboot
=>
f_sdb_embed_device
(
c_xwb_xil_multiboot_sdb
,
c_addr_multiboot
)
,
c_slv_onewire_mst
=>
f_sdb_embed_device
(
c_xwb_onewire_master_sdb
,
c_addr_onewire_mst
)
c_addr_multiboot
)
--
c_slv_onewire_mst => f_sdb_embed_device(c_xwb_onewire_master_sdb,
--
c_addr_onewire_mst)
);
-- Tag bufferdata width: 40 -- TAI
...
...
@@ -288,7 +288,9 @@ architecture arch of conv_common_gw is
type
t_inv_pulse_led_cnt
is
array
(
g_nr_inv_chans
-1
downto
0
)
of
unsigned
(
18
downto
0
);
type
t_temp_rise_cnt
is
array
(
c_max_nr_chans
-1
downto
0
)
of
unsigned
(
39
downto
0
);
type
t_pulse_cnt
is
array
(
c_max_nr_chans
-1
downto
0
)
of
unsigned
(
31
downto
0
);
type
t_ch_pcr
is
array
(
c_max_nr_chans
-1
downto
0
)
...
...
@@ -322,16 +324,18 @@ architecture arch of conv_common_gw is
signal
trig_pgen
:
std_logic_vector
(
g_nr_chans
-1
downto
0
);
signal
burst_en_n
:
std_logic
;
signal
pulse_outp_cont
:
std_logic_vector
(
g_nr_chans
-1
downto
0
);
signal
burst_outp_sh
:
std_logic_vector
(
g_nr_chans
-1
downto
0
);
signal
burst_outp_sh
:
std_logic_vector
(
g_nr_chans
-1
downto
0
);
signal
pulse_r_edge_lg_p
:
std_logic_vector
(
g_nr_chans
-1
downto
0
);
signal
pulse_f_edge_lg_p
:
std_logic_vector
(
g_nr_chans
-1
downto
0
);
signal
pulse_r_edge_sh_p
:
std_logic_vector
(
g_nr_chans
-1
downto
0
);
signal
pulse_f_edge_sh_p
:
std_logic_vector
(
g_nr_chans
-1
downto
0
);
signal
pulse_outp_sh
:
std_logic_vector
(
g_nr_chans
-1
downto
0
);
signal
burst_outp_lg
:
std_logic_vector
(
g_nr_chans
-1
downto
0
);
signal
burst_outp_lg
:
std_logic_vector
(
g_nr_chans
-1
downto
0
);
signal
pulse_outp_lg
:
std_logic_vector
(
g_nr_chans
-1
downto
0
);
signal
pulse_outp
:
std_logic_vector
(
g_nr_chans
-1
downto
0
);
signal
temp_rise_c_lg
:
t_temp_rise_cnt
;
signal
temp_rise_c_sh
:
t_temp_rise_cnt
;
signal
pulse_outp_d0
:
std_logic_vector
(
g_nr_chans
-1
downto
0
);
signal
pulse_outp_redge_p
:
std_logic_vector
(
g_nr_chans
-1
downto
0
);
signal
inv_pulse_outp
:
std_logic_vector
(
g_nr_inv_chans
-1
downto
0
);
...
...
@@ -460,13 +464,45 @@ architecture arch of conv_common_gw is
signal
id
:
std_logic_vector
(
63
downto
0
);
signal
temper
:
std_logic_vector
(
15
downto
0
);
--Chipscope signals
-- signal CONTROL : std_logic_vector(35 downto 0);
-- signal CLK : std_logic;
-- signal TRIG0 : std_logic_vector(7 downto 0);
-- signal TRIG1 : std_logic_vector(7 downto 0);
-- signal TRIG2 : std_logic_vector(7 downto 0);
-- signal TRIG3 : std_logic_vector(7 downto 0);
-- signal TRIG4 : std_logic_vector(7 downto 0);
-- signal TRIG5 : std_logic_vector(7 downto 0);
--==============================================================================
-- architecture begin
--==============================================================================
begin
---------------------------------------------------------------------------------------------------
-- CHIPSCOPE --
---------------------------------------------------------------------------------------------------
-- chipscope_ila_1 : chipscope_ila
-- port map (
-- CONTROL => CONTROL,
-- CLK => clk_20_i,
-- TRIG0 => TRIG0,
-- TRIG1 => TRIG1,
-- TRIG2 => TRIG2,
-- TRIG3 => TRIG3,
-- TRIG4 => TRIG4,
-- TRIG5 => TRIG5);
-- chipscope_icon_1 : chipscope_icon
-- port map ( CONTROL0 => CONTROL);
-- TRIG0(7 downto 0) <= std_logic_vector(temp_rise_c_sh (7 downto 0));
-- TRIG0(7 downto 0) <= std_logic_vector(temp_rise_c_sh (15 downto 8));
-- TRIG0(7 downto 0) <= std_logic_vector(temp_rise_c_sh (23 downto 16));
-- TRIG0(7 downto 0) <= std_logic_vector(temp_rise_c_sh (31 downto 24));
-- TRIG0(7 downto 0) <= std_logic_vector(temp_rise_c_sh (39 downto 32));
-- TRIG0(7 downto 0) <= std_logic_vector(temp_rise_c_sh (7 downto 0));
--============================================================================
-- Differential input buffer for 125 MHz clock
--============================================================================
...
...
@@ -766,6 +802,7 @@ end generate gen_pulse_cnt;
pulse_burst_i
=>
pulse_outp_lg
(
i
),
pulse_r_edge_p_i
=>
pulse_r_edge_lg_p
(
i
),
pulse_f_edge_p_i
=>
pulse_f_edge_lg_p
(
i
),
temp_rise_o
=>
temp_rise_c_lg
(
i
),
pulse_burst_o
=>
burst_outp_lg
(
i
),
burst_err_p_o
=>
burst_outp_err_lg_p
(
i
)
...
...
@@ -820,6 +857,7 @@ end generate gen_pulse_cnt;
pulse_burst_i
=>
pulse_outp_sh
(
i
),
pulse_r_edge_p_i
=>
pulse_r_edge_sh_p
(
i
),
pulse_f_edge_p_i
=>
pulse_f_edge_sh_p
(
i
),
temp_rise_o
=>
temp_rise_c_sh
(
i
),
pulse_burst_o
=>
burst_outp_sh
(
i
),
burst_err_p_o
=>
burst_outp_err_sh_p
(
i
)
);
...
...
top/conv_common_gw_pkg.vhd
View file @
a292ca9e
...
...
@@ -332,6 +332,9 @@ package conv_common_gw_pkg is
pulse_r_edge_p_i
:
in
std_logic
;
pulse_f_edge_p_i
:
in
std_logic
;
-- Temp_rise is output for external probing
temp_rise_o
:
out
unsigned
(
39
downto
0
)
;
-- Dynamic temperature-controlled ouput pulse train.
pulse_burst_o
:
out
std_logic
;
-- Burst error output, pulses high for one clock cycle when a pulse arrives
...
...
@@ -688,6 +691,37 @@ component wf_decr_counter is
counter_is_zero_o
:
out
std_logic
);
-- empty counter indication
end
component
wf_decr_counter
;
------------------------------------------------------------------------------
-- CHIPSCOPE COMPONENTS
------------------------------------------------------------------------------
component
chipscope_ila
IS
port
(
CONTROL
:
inout
std_logic_vector
(
35
downto
0
);
CLK
:
in
std_logic
;
TRIG0
:
in
std_logic_vector
(
7
downto
0
);
TRIG1
:
in
std_logic_vector
(
7
downto
0
);
TRIG2
:
in
std_logic_vector
(
7
downto
0
);
TRIG3
:
in
std_logic_vector
(
7
downto
0
);
TRIG4
:
in
std_logic_vector
(
7
downto
0
);
TRIG5
:
in
std_logic_vector
(
7
downto
0
));
END
component
chipscope_ila
;
component
chipscope_icon
IS
port
(
CONTROL0
:
inout
std_logic_vector
(
35
downto
0
);
TDO_OUT
:
out
std_logic
;
TDI_IN
:
in
std_logic
;
RESET_IN
:
in
std_logic
;
SHIFT_IN
:
in
std_logic
;
UPDATE_IN
:
in
std_logic
;
CAPTURE_IN
:
in
std_logic
;
SEL_IN
:
in
std_logic
;
DRCK_IN
:
in
std_logic
);
END
component
chipscope_icon
;
end
package
conv_common_gw_pkg
;
...
...
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