Made sure latest timestamp registers are not loaded on WB cycle

This is to make sure no readouts of erroneous values from this registers occur due to the register value not being stable at the time the WB read cycle is requested.

Made sure latest timestamp registers are not loaded on WB cycle
This is to make sure no readouts of erroneous values from this registers occur due to the register value not being stable at the time the WB read cycle is requested.
92778c1f · Theodor-Adrian Stana · 07ba0838 · 92778c1f
Commit 92778c1f authored Aug 25, 2014 by Theodor-Adrian Stana
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conv_common_gw.vhd top/conv_common_gw.vhd +5 -1

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--- a/top/conv_common_gw.vhd
+++ b/top/conv_common_gw.vhd
@@ -1031,7 +1031,11 @@ end generate;
        else
          lts_ld_toggle_d0(i) <= lts_ld_toggle(i);
          lts_ld_toggle_d1(i) <= lts_ld_toggle_d0(i);
-          lts_ld_20(i)        <= lts_ld_toggle_d0(i) xor lts_ld_toggle_d1(i);
+          -- avoid garbled data in regs by disabling load pulse on WB transfer
+          if (xbar_master_out(c_slv_conv_regs).stb = '0') and
+             (xbar_master_out(c_slv_conv_regs).cyc = '0') then
+            lts_ld_20(i) <= lts_ld_toggle_d0(i) xor lts_ld_toggle_d1(i);
+          end if;
        end if;
      end loop;
    end if;