Commit 73525861 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

doc: Updated conv-common-gw specification to v2.1

parent cd7e4c49
......@@ -9,7 +9,7 @@
\noindent \rule{\textwidth}{.1cm}
\hfill August 29, 2014
\hfill January 26, 2014
\vspace*{3cm}
......
......@@ -49,8 +49,20 @@
% Revision history
%------------------------------------------------------------------------------
\pagebreak
\addcontentsline{toc}{section}{Revision history}
\thispagestyle{empty}
\addcontentsline{toc}{section}{Licensing information}
\section*{Licensing information}
\noindent
This document is licensed under a Creative Commons Attribution-ShareAlike 4.0
International License. If you have not received a copy of the license along with this
work, see \\
\url{http://creativecommons.org/licenses/by-sa/4.0/}
\section*{Revision history}
\addcontentsline{toc}{section}{Revision history}
\centerline
{
......@@ -64,6 +76,8 @@
29-08-2014 & 2.0 & Added sections for input pulse counters, time-tagging,
manual pulse triggering, one-wire thermometer module, the switches
on the converter boards, and changed and corrected some wording \\
26-01-2014 & 2.1 & Added licensing information, Table~\ref{tbl:timetag-rd-seq} and information
on which generics enable synthesis of certain modules. \\
\hline
\end{tabular}
}
......@@ -74,6 +88,8 @@
\pagebreak
\pdfbookmark[1]{\contentsname}{toc}
\tableofcontents
\pagebreak
\listoffigures
\listoftables
......@@ -115,8 +131,7 @@ following commands:
\begin{small}
\begin{verbatim}
git clone git://ohwr.org/level-conversion/conv-common-gw.git
git submodule init
git submodule update
git submodule update --init --recursive
\end{verbatim}
\end{small}
......@@ -201,7 +216,7 @@ Table~\ref{tbl:switches} summarizes the switches on converter boards.
General-purpose & Eight switches that \textit{should} be implemented on all converter boards.
Read their state from the SR.SWITCHES field (see Appendix~\ref{app:conv-regs-sr}) \\
Other & Dedicated switches for specific converter boards.
y Read their state from the OSWR register
Read their state from the OSWR register
(see Appendix~\ref{app:conv-regs-oswr}) \\
\hline
\end{tabular}
......@@ -302,11 +317,31 @@ apart from driving the pulse output of the module. Input pulses also trigger
the incrementing of a pulse counter, as well as the storage of a timestamp to a dedicated
FIFO memory.
Note that the channel logic can be selectively synthesized by means of the
top-level component generics. Table~\ref{tbl:chan-logic-generics} shows which
generics enable channel logic shown in Figure~\ref{fig:chan-logic}.
\begin{figure}[h]
\centerline{\includegraphics[width=1.1\textwidth]{fig/chan-logic}}
\caption{\label{fig:chan-logic} Channel logic diagram}
\end{figure}
\begin{table}[h]
\rowcolors{2}{white}{gray!25}
\caption{\label{tbl:chan-logic-generics} Generics to enable components in the channel logic}
\centerline{
\begin{tabular}{l l}
\hline
\multicolumn{1}{c}{\textbf{Component}} & \multicolumn{1}{c}{\textbf{Generic}} \\
\hline
Pulse counters & \textit{g\_with\_pulse\_cnt $=>$ true} \\
Timetag logic & \textit{g\_with\_pulse\_timetag $=>$ true} \\
Manual trigger & \textit{g\_with\_man\_trig $=>$ true} \\
\hline
\end{tabular}
}
\end{table}
%------------------------------------------------------------------------------
\subsection{Output enable}
\label{subsec:oen}
......@@ -353,6 +388,14 @@ For information on the module's implementation, consult its documentation in the
\label{subsec:pulse-cnt}
%------------------------------------------------------------------------------
\begin{tabular}{p{.96\textwidth}}
\hline
\large \hspace*{22pt} Synthesized when \textit{g\_with\_pulse\_cnt $=>$ true}. \\
\hline
\end{tabular}
\vspace*{11pt}
Figure~\ref{fig:pulse-cnt} presents the implementation of the pulse counters.
When a pulse arrives on either the TTL or blocking side, it is resynchronized
in the 20~MHz clock domain and passed through a rising edge detector. When
......@@ -360,20 +403,28 @@ a rising edge occurs on the pulse, the counter is incremented by one and stored
to the channel pulse counter register (CHxPCR -- see Appendix~\ref{app:conv-regs})
register.
The pulse counter register can be written via the \textit{conv\_regs} component as a
result of an I$^2$C write access to the register's address.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/pulse-cnt}}
\caption{Pulse counter implementation}
\label{fig:pulse-cnt}
\end{figure}
The pulse counter register can be written via the \textit{conv\_regs} component as a
result of an I$^2$C write access to the register's address.
%------------------------------------------------------------------------------
\subsection{Time-tagging mechanism}
\label{subsec:pulse-timetag}
%------------------------------------------------------------------------------
\begin{tabular}{p{.96\textwidth}}
\hline
\large \hspace*{22pt} Synthesized when \textit{g\_with\_pulse\_timetag $=>$ true}. \\
\hline
\end{tabular}
\vspace*{11pt}
The architecture of the pulse time-tagging mechanism is shown in Figure~\ref{fig:timetag-arch}.
The time-tagging mechanism is clocked from the 125~MHz clock domain. Input pulses trigger the storage
to a ring buffer of either internally-generated timestamps, or precise timestamps from the White
......@@ -388,6 +439,7 @@ Finally, the current value of TAI time can be read from dedicated registers.
\end{figure}
%------------------------------------------------------------------------------
\pagebreak
\subsubsection{Time-tagging controller}
\label{subsec:pulse-timetag-ctrl}
%------------------------------------------------------------------------------
......@@ -411,14 +463,13 @@ ORed pulse rising edge detection signal, a timestamp is stored to the time-tag b
two to three cycles after its actual arrival on the input (Figure~\ref{fig:timetag-delay}).
The same delay applies to the latest timestamp registers.
\pagebreak
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/timetag-core}}
\caption{\label{fig:timetag-core} Time-tagging controller architecture}
\vspace*{22pt}
\end{figure}
\centerline{\includegraphics[width=.8\textwidth]{fig/timetag-delay}}
\begin{figure}
\centerline{\includegraphics[width=\textwidth]{fig/timetag-delay}}
\caption{\label{fig:timetag-delay} Timestamp storage delay}
\end{figure}
......@@ -432,7 +483,7 @@ A dual-clock asynchronous FIFO synchronizes data between the read and write cloc
Data from the FIFO is stored to the RAM clocked from the read clock domain.
\begin{figure}
\centerline{\includegraphics[width=.8\textwidth]{fig/timetag-ring-buf}}
\centerline{\includegraphics[width=\textwidth]{fig/timetag-ring-buf}}
\caption{Ring buffer implementation}
\label{fig:timetag-ring-buf}
\end{figure}
......@@ -448,14 +499,36 @@ buffer is empty, a write to a full buffer will start overwriting old timestamps.
For converter board designs, a caution should be put in place. Because the TBMR
register (see Appendix~\ref{app:conv-regs-tbmr}) causes the read pointer to advance,
it should be the last register read in a readout cycle. Otherwise, the values of the
other tag buffer registers will return the next sample in the tag buffer.
it should be the last register read in a readout cycle (Table~\ref{tbl:timetag-rd-seq}).
Otherwise, the values of the other tag buffer registers will return the next sample in the tag buffer.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/timetag-buf-mech}}
\begin{figure}
\centerline{\includegraphics[width=.97\textwidth]{fig/timetag-buf-mech}}
\caption{\label{fig:timetag-buf-mech} Ring buffer mechanics}
\end{figure}
\setcounter{rownr}{0}
\begin{table}[h]
\caption{Timetag read sequence}
\label{tbl:timetag-rd-seq}
\centerline {
\rowcolors{2}{white}{gray!25}
\begin{tabular}{c p{.8\textwidth}}
\hline
\textbf{Step} & \multicolumn{1}{c}{\textbf{Action}} \\
\hline
\rownumber & \textbf{Read the TBCSR} and make sure that the EMPTY bit is not '1' \\
\rownumber & \textbf{Read the TBCYR} to obtain the 8~ns cycles counter value \\
\rownumber & \textbf{Read the TBTLR} to obtain the lower part of the TAI seconds counter \\
\rownumber & \textbf{Read the TBTHR} to obtain the upper part of the TAI seconds counter \\
\rownumber & \textbf{Read the TBTMR} to obtain the meta data about the timetag sample and advance
the buffer read pointer \\
\hline
\end{tabular}
}
\end{table}
%------------------------------------------------------------------------------
\subsubsection{Synchronization issues}
\label{subsec:pulse-timetag-sync}
......@@ -481,6 +554,14 @@ any problem of synchronization when read by the user.
\label{subsec:man-trig}
%------------------------------------------------------------------------------
\begin{tabular}{p{.96\textwidth}}
\hline
\large \hspace*{22pt} Synthesized when \textit{g\_with\_man\_trig $=>$ true}. \\
\hline
\end{tabular}
\vspace*{11pt}
The manual pulse trigger module (\textit{conv\_man\_trig}) is implemented in the form
of a simple state machine, which is shown in Figure~\ref{fig:man-trig}. The module
is directly connected to the register load output of the \textit{conv\_regs} module,
......@@ -490,7 +571,7 @@ advances. Otherwise, the FSM returns to the IDLE state and the sequence must be
The FSM waits in each state indefinitely for a value to be input.
\begin{figure}[h]
\centerline{\includegraphics[width=.7\textwidth]{fig/man-trig-fsm}}
\centerline{\includegraphics[width=.55\textwidth]{fig/man-trig-fsm}}
\caption{\label{fig:man-trig} FSM of the manual pulse trigger module}
\end{figure}
......@@ -524,12 +605,10 @@ If this is enabled, then the pulse is synchronized externally to the \textit{con
block and it triggers the FSM directly. Alternatively, if the glitch filter is disabled, the trigger
input starts the pulse (to avoid glitches on the leading edge) and then the pulse is synchronized and the
FSM triggered to generate the fixed-width pulse. After the pulse width has been reached, the FSM resets
the input flip-flop and goes into the rejection state.
the input flip-flop and goes into the rejection state. If any pulses arrive either during the generation
state or the rejection state, the pulse is rejected and the error output is set high for one clock cycle.
If any pulses arrive either during the generation state, or the rejection state, the error output
is set high for one clock cycle.
\begin{figure}
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/pulse-gen-operation}}
\caption{\label{fig:pulse-gen-operation} Pulse generator operation with \textit{g\_pgen\_fixed\_width = true}}
\end{figure}
......@@ -668,6 +747,14 @@ module and how to use it, consult its documentation under the \textit{general-co
\label{subsec:onewire}
%==============================================================================
\begin{tabular}{p{.96\textwidth}}
\hline
\large \hspace*{22pt} Synthesized when \textit{g\_with\_thermometer $=>$ true}. \\
\hline
\end{tabular}
\vspace*{11pt}
Converter boards are expected to contain a DS18B20 thermometer chip~\cite{ds18b20},
which can be used for monitoring the temperature of, and obtaining a unique
identifier for the board.
......@@ -769,7 +856,7 @@ one-wire timings. The value for the current version of the gateware is
This appendix offers guidelines on how to use or change \textit{conv\_common\_gw}
should a pulse repeater with more than six channels be eventually implemented.
Note that none of the guidelines here have been tested, since no board exists
Note that the guidelines here have \textbf{not} been tested, since no board exists
with more than six channels at the time of writing of this document.
The first option is obviously instantiating more than one \textit{conv\_common\_gw}
......@@ -782,8 +869,8 @@ to the top-level module outputs, as shown in Figure~\ref{fig:more-than-six-chans
The synthesis tool should be smart enough to optimize away the unused modules.
\begin{figure}[h]
\centerline{\includegraphics[width=1.1\textwidth]{fig/more-than-six-chans}}
\caption{\label{fig:more-than-six-chans} Connect the outputs of only one \textit{conv\_common\_gw} module at the top-level}
\centerline{\includegraphics[width=\textwidth]{fig/more-than-six-chans}}
\caption{\label{fig:more-than-six-chans} Connections to flash and thermometer with more than one \textit{conv\_common\_gw} modules}
\end{figure}
\pagebreak
......
......@@ -2,6 +2,7 @@
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