Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
C
Converter Common Gateware
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
1
Issues
1
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
Converter Common Gateware
Commits
63a8201d
Commit
63a8201d
authored
Oct 10, 2017
by
Denia Bouhired-Ferrag
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
added fastevent_counter module. was in conv-ttl-blo-gw/modules
parent
c823fae5
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
123 additions
and
0 deletions
+123
-0
fastevent_counter.vhd
modules/fastevent_counter.vhd
+123
-0
No files found.
modules/fastevent_counter.vhd
0 → 100644
View file @
63a8201d
-- Q: I want to capture very fast pulses on a slower clock. the pulses are
-- shorter than a clock period but will not arrive more often than one
-- every few cycles. How do I detect them?
-- A: This circuit.
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
entity
fastevent_counter
is
port
(
sysclk_i
:
in
std_logic
;
rstcount_i
:
in
std_logic
;
en_i
:
in
std_logic
;
trig_i
:
in
std_logic
;
count_o
:
out
std_logic_vector
(
31
downto
0
);
count_int_o
:
out
unsigned
(
31
downto
0
));
end
entity
;
architecture
rtl
of
fastevent_counter
is
-- flancter signals
signal
setce
:
std_logic
;
signal
clrce
:
std_logic
;
signal
flag
:
std_logic
;
signal
flag_sync
:
std_logic
;
signal
setflop
:
std_logic
:
=
'0'
;
signal
clrflop
:
std_logic
:
=
'0'
;
--count value
-- signal count_int : unsigned(7 downto 0);
signal
rst_counter
,
incr_counter
:
std_logic
;
signal
count_int
:
unsigned
(
31
downto
0
);
type
state_t
is
(
wait_flag
,
flag_set
);
signal
state
,
nextstate
:
state_t
:
=
wait_flag
;
begin
-- This is the flancter bit:
-- set flop
set_proc
:
process
(
trig_i
)
begin
if
rising_edge
(
trig_i
)
then
if
setce
=
'1'
then
-- flops get opposite logic levels.
setflop
<=
not
clrflop
;
end
if
;
end
if
;
end
process
;
-- clr flop
clr_proc
:
process
(
sysclk_i
)
begin
if
rising_edge
(
sysclk_i
)
then
if
clrce
=
'1'
then
-- flops get the same logic levels.
clrflop
<=
setflop
;
end
if
;
end
if
;
end
process
;
-- sync the flag into the sysclk_i domain.
-- clear the sync regs in one go to react to the next trig earlier.
flag_sync_p
:
process
(
sysclk_i
)
begin
if
rising_edge
(
sysclk_i
)
then
if
clrce
=
'1'
then
flag_sync
<=
'0'
;
flag
<=
'0'
;
else
flag_sync
<=
setflop
xor
clrflop
;
flag
<=
flag_sync
;
end
if
;
end
if
;
end
process
;
-- the counter
counter_p
:
process
(
sysclk_i
)
begin
if
rising_edge
(
sysclk_i
)
then
if
rst_counter
=
'1'
then
count_int
<=
(
others
=>
'0'
);
elsif
incr_counter
=
'1'
then
count_int
<=
count_int
+
1
;
end
if
;
end
if
;
end
process
;
-- Two-state machine to keep track of what we're doing
-- Either we're waiting for a pulse, or we've had one
-- and we need to react to it by incrementing the counter and reseting the flag.
nextstate_p
:
process
(
state
,
en_i
,
flag
,
rstcount_i
)
is
begin
setce
<=
'0'
;
clrce
<=
'0'
;
incr_counter
<=
'0'
;
rst_counter
<=
'0'
;
nextstate
<=
state
;
case
state
is
when
wait_flag
=>
-- wait for flag to be set
if
en_i
=
'1'
then
setce
<=
'1'
;
if
flag
=
'1'
then
nextstate
<=
flag_set
;
end
if
;
end
if
;
if
rstcount_i
=
'1'
then
rst_counter
<=
'1'
;
end
if
;
when
flag_set
=>
-- flag set, so trig happened
-- increment count and clr flag
incr_counter
<=
'1'
;
clrce
<=
'1'
;
nextstate
<=
wait_flag
;
end
case
;
end
process
;
state_p
:
process
(
sysclk_i
)
begin
if
rising_edge
(
sysclk_i
)
then
state
<=
nextstate
;
end
if
;
end
process
;
count_o
<=
std_logic_vector
(
count_int
);
count_int_o
<=
count_int
;
end
architecture
rtl
;
\ No newline at end of file
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment