Merge remote-tracking branch 'origin/master'

3ae0cfc2 · Theodor-Adrian Stana · 8176b3ed · dc4bfb25 · 3ae0cfc2 · 3ae0cfc2
Commit 3ae0cfc2 authored Dec 11, 2014 by Theodor-Adrian Stana
6 changed files
--- a/doc/conv-common-gw.tex
+++ b/doc/conv-common-gw.tex
@@ -593,8 +593,8 @@ as part of \textit{conv\_regs} are intended to be active-high logic, so adaptati
 in logic external to the \textit{conv\_common\_gw} when an external connection is needed.

 The inputs that connect to bits in the status register are shown in Table~\ref{tbl:conv-regs-ext-inputs}.
-Should some of these inputs not be used, such as for example the failsafe lines in the case of CONV-TTL-BLO~\cite{conv-ttl-blo-ohwr},
-the corresponding lines should be connected to all-zeroes.
+Should some of these inputs not be used, such as for example the rear-panel failsafe lines in the case of
+CONV-TTL-BLO~\cite{conv-ttl-blo-ohwr}, the corresponding lines should be connected to all-zeroes.

 The \textit{g\_board\_id} and \textit{g\_gwvers} generics connect to registers in
 \textit{conv\_regs} as shown in Figure~\ref{fig:bidr-gwvers}.
@@ -613,7 +613,9 @@ The \textit{g\_board\_id} and \textit{g\_gwvers} generics connect to registers i
      line\_front\_i & LSR.FRONT & State of front-panel channel lines at FPGA input \\
      line\_inv\_i & LSR.FRONTINV & State of front-panel general-purpose inverter channels at FPGA input \\
      line\_rear\_i & LSR.REAR & State of rear-panel channel lines at FPGA input \\
-      line\_rear\_fs\_i & LSR.REARFS & State of fail-safe rear-panel inputs (whether a cable is plugged in or not) \\
+      line\_front\_fs\_i & LSR.FRONTFS & State of front-panel channel failsafe lines at FPGA input \\
+      line\_inv\_fs\_i & LSR.FRONTINVFS & State of front-panel general-purpose inverter failsafe lines at FPGA input \\
+      line\_rear\_fs\_i & LSR.REARFS & State of rear-panel input failsafe lines (whether a cable is plugged in or not) \\
      sw\_other\_i & OSWR & State of other on-board switches \\
      \hline
    \end{tabular}
@@ -631,10 +633,27 @@ bits or fields in \textit{conv\_regs} are set to a 'safe' value of '0'. Consult
 for details on how this is done and which are the fields concerned.

 Note that the logic allows less than 6 pulse repetition channels, but not more.
-If \textit{g\_nr\_chans < 6}, then the rest of the bits are automatically set to '0',
+If \textit{g\_nr\_chans $<$ 6}, then the rest of the bits are automatically set to '0',
 as in the case a \textit{g\_with\_*} generic is \textit{false}. If \textit{g\_nr\_chans $>$ 6}
 a synthesis error will be thrown.

+\subsubsection{Fail-safe lines in the line status register}
+
+The CONV-TTL-RS485~\cite{conv-ttl-rs485-ohwr} board has a an extra RS-485 transceiver per each
+channel input and output line, dedicated to detecting whether a line is in a fault state, or whether
+a cable is not plugged in.
+
+This in RS-485 parlance is called the fail-safe state and half the bits in the
+line status register (LSR -- see Appendix~\ref{app:conv-regs-lsr}) take their name after it. Designers of
+future converter boards would implement similar features for all the inputs might want to implement a 
+similar feature on future converter boards. For this, bits are provided in the LSR as shown in Table~\ref{tbl:conv-regs-ext-inputs}.
+If no such feature exists, or if the feature is only implemented for one of the two panels (front or rear),
+the non-used lines in Table~\ref{tbl:conv-regs-ext-inputs} can simply be connected to all-zeroes.
+
+Note that the register limits the user to six pulse repetition channels and four general-purpose inverter
+channels. Should more be needed, another \textit{conv\_common\_gw} module should be used, as shown in
+Appendix~\ref{app:more-than-six-chans}.
+
 %==============================================================================
 \subsection{MultiBoot}
 \label{subsec:multiboot}

--- a/doc/conv-regs.tex
+++ b/doc/conv-regs.tex
@@ -1522,11 +1522,11 @@ WRTAG
 \begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
 31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
 \hline
-\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\multicolumn{6}{|c|}{\cellcolor{gray!25}REARFS[5:0]} & \multicolumn{2}{|c|}{\cellcolor{gray!25}FRONTINVFS[3:2]}\\
 \hline
 23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
 \hline
-\multicolumn{1}{|c}{-} & - & \multicolumn{6}{|c|}{\cellcolor{gray!25}REARFS[5:0]}\\
+\multicolumn{2}{|c|}{\cellcolor{gray!25}FRONTINVFS[1:0]} & \multicolumn{6}{|c|}{\cellcolor{gray!25}FRONTFS[5:0]}\\
 \hline
 15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
 \hline
@@ -1563,10 +1563,24 @@ Line state at board input\\      Bit 0 -- channel 1\\      Bit 1 -- channel 2\\
 \end{small}
 \item \begin{small}
 {\bf 
+FRONTFS
+} [\emph{read-only}]: Front panel input failsafe state
+\\
+High if line is in failsafe mode (e.g., no cable plugged in)\\      Bit 0 -- channel 1\\      Bit 1 -- channel 2\\      etc.
+\end{small}
+\item \begin{small}
+{\bf 
+FRONTINVFS
+} [\emph{read-only}]: Front panel inverter input failsafe state
+\\
+High if line is in failsafe mode (e.g., no cable plugged in)\\      Bit 0 -- channel 1\\      Bit 1 -- channel 2\\      etc.
+\end{small}
+\item \begin{small}
+{\bf 
 REARFS
-} [\emph{read-only}]: Input failsafe state
+} [\emph{read-only}]: Rear panel input failsafe state
 \\
-High if line is in failsafe mode (no cable plugged in)\\      Bit 0 -- channel 1\\      Bit 1 -- channel 2\\      etc.
+High if line is in failsafe mode (e.g., no cable plugged in)\\      Bit 0 -- channel 1\\      Bit 1 -- channel 2\\      etc.
 \end{small}
 \item \begin{small}
 \textbf{Unimplemented bits}: write as '0', read undefined
@@ -1574,7 +1588,6 @@ High if line is in failsafe mode (no cable plugged in)\\      Bit 0 -- channel 1
 \end{itemize}
 \vspace{11pt}

-\pagebreak
 \subsubsection{OSWR -- Other Switches Register}
 \label{app:conv-regs-oswr}


--- a/modules/conv_regs.vhd
+++ b/modules/conv_regs.vhd
@@ -168,6 +168,10 @@ entity conv_regs is
    reg_lsr_frontinv_i                       : in     std_logic_vector(3 downto 0);
 -- Port for std_logic_vector field: 'Rear panel input state' in reg: 'LSR'
    reg_lsr_rear_i                           : in     std_logic_vector(5 downto 0);
+-- Port for std_logic_vector field: 'Front panel channel input state' in reg: 'LSR'
+    reg_lsr_frontfs_i                        : in     std_logic_vector(5 downto 0);
+-- Port for std_logic_vector field: 'Front panel INV-TTL input state' in reg: 'LSR'
+    reg_lsr_frontinvfs_i                     : in     std_logic_vector(3 downto 0);
 -- Port for std_logic_vector field: 'Input failsafe state' in reg: 'LSR'
    reg_lsr_rearfs_i                         : in     std_logic_vector(5 downto 0);
 -- Port for std_logic_vector field: 'Multicast address (from switch)' in reg: 'MSWR'
@@ -799,17 +803,9 @@ begin
            rddata_reg(5 downto 0) <= reg_lsr_front_i;
            rddata_reg(9 downto 6) <= reg_lsr_frontinv_i;
            rddata_reg(15 downto 10) <= reg_lsr_rear_i;
-            rddata_reg(21 downto 16) <= reg_lsr_rearfs_i;
-            rddata_reg(22) <= 'X';
-            rddata_reg(23) <= 'X';
-            rddata_reg(24) <= 'X';
-            rddata_reg(25) <= 'X';
-            rddata_reg(26) <= 'X';
-            rddata_reg(27) <= 'X';
-            rddata_reg(28) <= 'X';
-            rddata_reg(29) <= 'X';
-            rddata_reg(30) <= 'X';
-            rddata_reg(31) <= 'X';
+            rddata_reg(21 downto 16) <= reg_lsr_frontfs_i;
+            rddata_reg(25 downto 22) <= reg_lsr_frontinvfs_i;
+            rddata_reg(31 downto 26) <= reg_lsr_rearfs_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "100011" => 

--- a/modules/conv_regs.wb
+++ b/modules/conv_regs.wb
@@ -776,8 +776,32 @@ peripheral {
      access_bus = READ_ONLY;
    };
    field {
-      name = "Input failsafe state";
-      description = "High if line is in failsafe mode (no cable plugged in)\
+      name = "Front panel input failsafe state";
+      description = "High if line is in failsafe mode (e.g., no cable plugged in)\
+      Bit 0 -- channel 1\
+      Bit 1 -- channel 2\
+      etc.";
+      prefix = "frontfs";
+      type = SLV;
+      size = 6;
+      access_dev = WRITE_ONLY;
+      access_bus = READ_ONLY;
+    };
+    field {
+      name = "Front panel inverter input failsafe state";
+      description = "High if line is in failsafe mode (e.g., no cable plugged in)\
+      Bit 0 -- channel 1\
+      Bit 1 -- channel 2\
+      etc.";
+      prefix = "frontinvfs";
+      type = SLV;
+      size = 4;
+      access_dev = WRITE_ONLY;
+      access_bus = READ_ONLY;
+    };
+    field {
+      name = "Rear panel input failsafe state";
+      description = "High if line is in failsafe mode (e.g., no cable plugged in)\
      Bit 0 -- channel 1\
      Bit 1 -- channel 2\
      etc.";

--- a/top/conv_common_gw.vhd
+++ b/top/conv_common_gw.vhd
@@ -178,6 +178,10 @@ entity conv_common_gw is
    line_front_i            : in std_logic_vector(g_nr_chans-1 downto 0);
    line_inv_i              : in std_logic_vector(3 downto 0);
    line_rear_i             : in std_logic_vector(g_nr_chans-1 downto 0);
+
+    -- Fail-safe lines, detect invalid or no signal on channel input
+    line_front_fs_i         : in std_logic_vector(g_nr_chans-1 downto 0);
+    line_inv_fs_i           : in std_logic_vector(3 downto 0);
    line_rear_fs_i          : in std_logic_vector(g_nr_chans-1 downto 0);

    -- Thermometer line
@@ -314,6 +318,7 @@ architecture arch of conv_common_gw is
  signal i2c_err_bit_rst_ld  : std_logic;
  signal line_front          : std_logic_vector(c_max_nr_chans-1 downto 0);
  signal line_rear           : std_logic_vector(c_max_nr_chans-1 downto 0);
+  signal line_front_fs       : std_logic_vector(c_max_nr_chans-1 downto 0);
  signal line_rear_fs        : std_logic_vector(c_max_nr_chans-1 downto 0);

  -- LED signals
@@ -875,23 +880,26 @@ end generate gen_pulse_timetag;

 --------------------------------------------------------------------------------
 gen_line : if (g_nr_chans = c_max_nr_chans) generate
-  line_front   <= line_front_i;
-  line_rear    <= line_rear_i;
-  line_rear_fs <= line_rear_fs_i;
+  line_front    <= line_front_i;
+  line_rear     <= line_rear_i;
+  line_front_fs <= line_front_fs_i;
+  line_rear_fs  <= line_rear_fs_i;
 end generate gen_line;
 --------------------------------------------------------------------------------

 --------------------------------------------------------------------------------
 gen_line_unused_chans : if (g_nr_chans < c_max_nr_chans) generate
  -- connect used lines
-  line_front(g_nr_chans-1 downto 0)   <= line_front_i;
-  line_rear(g_nr_chans-1 downto 0)    <= line_rear_i;
-  line_rear_fs(g_nr_chans-1 downto 0) <= line_rear_fs_i;
+  line_front(g_nr_chans-1 downto 0)    <= line_front_i;
+  line_rear(g_nr_chans-1 downto 0)     <= line_rear_i;
+  line_front_fs(g_nr_chans-1 downto 0) <= line_front_fs_i;
+  line_rear_fs(g_nr_chans-1 downto 0)  <= line_rear_fs_i;

  -- unused lines to zeroes
-  line_front(c_max_nr_chans-1 downto g_nr_chans)   <= (others => '0');
-  line_rear(c_max_nr_chans-1 downto g_nr_chans)    <= (others => '0');
-  line_rear_fs(c_max_nr_chans-1 downto g_nr_chans) <= (others => '0');
+  line_front(c_max_nr_chans-1 downto g_nr_chans)    <= (others => '0');
+  line_rear(c_max_nr_chans-1 downto g_nr_chans)     <= (others => '0');
+  line_front_fs(c_max_nr_chans-1 downto g_nr_chans) <= (others => '0');
+  line_rear_fs(c_max_nr_chans-1 downto g_nr_chans)  <= (others => '0');
 end generate gen_line_unused_chans;
 --------------------------------------------------------------------------------

@@ -1168,6 +1176,8 @@ end generate gen_latest_timestamp_unused_chans;
      reg_lsr_front_i          => line_front,
      reg_lsr_frontinv_i       => line_inv_i,
      reg_lsr_rear_i           => line_rear,
+      reg_lsr_frontfs_i        => line_front_fs,
+      reg_lsr_frontinvfs_i     => line_inv_fs_i,
      reg_lsr_rearfs_i         => line_rear_fs,

      reg_oswr_switches_i      => sw_other_i

--- a/top/conv_common_gw_pkg.vhd
+++ b/top/conv_common_gw_pkg.vhd
@@ -180,6 +180,10 @@ package conv_common_gw_pkg is
      line_front_i            : in std_logic_vector(g_nr_chans-1 downto 0);
      line_inv_i              : in std_logic_vector(3 downto 0);
      line_rear_i             : in std_logic_vector(g_nr_chans-1 downto 0);
+
+      -- Fail-safe lines, detect invalid or no signal on channel input
+      line_front_fs_i         : in std_logic_vector(g_nr_chans-1 downto 0);
+      line_inv_fs_i           : in std_logic_vector(3 downto 0);
      line_rear_fs_i          : in std_logic_vector(g_nr_chans-1 downto 0);

      -- Thermometer line
@@ -419,6 +423,10 @@ package conv_common_gw_pkg is
      reg_lsr_frontinv_i                       : in     std_logic_vector(3 downto 0);
  -- Port for std_logic_vector field: 'Rear panel input state' in reg: 'LSR'
      reg_lsr_rear_i                           : in     std_logic_vector(5 downto 0);
+  -- Port for std_logic_vector field: 'Front panel channel input state' in reg: 'LSR'
+      reg_lsr_frontfs_i                        : in     std_logic_vector(5 downto 0);
+  -- Port for std_logic_vector field: 'Front panel INV-TTL input state' in reg: 'LSR'
+      reg_lsr_frontinvfs_i                     : in     std_logic_vector(3 downto 0);
  -- Port for std_logic_vector field: 'Input failsafe state' in reg: 'LSR'
      reg_lsr_rearfs_i                         : in     std_logic_vector(5 downto 0);
  -- Port for std_logic_vector field: 'Multicast address (from switch)' in reg: 'MSWR'