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C
Converter Common Gateware
Commit 108b24a0 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Add pulse counters

parent a1999c8c
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Showing with 50 additions and 18 deletions
top/conv_common_gw.vhd
View file @ 108b24a0
......@@ -224,6 +224,7 @@ architecture arch of conv_common_gw is
signal trig_synced : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_degl : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_chan : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_chan_redge_p : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_pgen : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_d0 : std_logic_vector(g_nr_chans-1 downto 0);
......@@ -386,6 +387,37 @@ begin
trig_chan(i) <= trig_a(i) when (gf_en_n_i = '1') else
trig_degl(i);
-- Now, sync this channel trigger signal before passing it to the counters
--
-- The pulse counter is triggered only by a pulse that actually makes it
-- to the pulse generator.
--
-- NOTE: glitch-filtered signal is also synced in 20MHz clock domain, but
-- another sync chain here avoids extra logic complication and shoudl have
-- no influence on the correctness of the pulse counter value
cmp_sync_ffs : gc_sync_ffs
port map
(
clk_i => clk_20_i,
rst_n_i => rst_20_n,
data_i => trig_chan(i),
ppulse_o => trig_chan_redge_p(i)
);
-- Then, generate the input pulse counters
p_pulse_cnt : process (clk_20_i)
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
pulse_cnt(i) <= (others => '0');
elsif (ch_pcr_ld(i) = '1') then
pulse_cnt(i) <= unsigned(ch_pcr(i));
elsif (trig_chan_redge_p(i) = '1') then
pulse_cnt(i) <= pulse_cnt(i) + 1;
end if;
end if;
end process p_pulse_cnt;
-- The trigger to the pulse generator is either manual OR from the channel input
trig_pgen(i) <= trig_chan(i);
......@@ -649,24 +681,24 @@ begin
reg_cr_mpt_o => open,
reg_cr_mpt_wr_o => open,
reg_ch1pcr_o => open, --ch_pcr(0),
reg_ch1pcr_i => (others => '0'), --std_logic_vector(pulse_cnt(0)),
reg_ch1pcr_load_o => open, --ch_pcr_ld(0),
reg_ch2pcr_o => open, --ch_pcr(1),
reg_ch2pcr_i => (others => '0'), --std_logic_vector(pulse_cnt(1)),
reg_ch2pcr_load_o => open, --ch_pcr_ld(1),
reg_ch3pcr_o => open, --ch_pcr(2),
reg_ch3pcr_i => (others => '0'), --std_logic_vector(pulse_cnt(2)),
reg_ch3pcr_load_o => open, --ch_pcr_ld(2),
reg_ch4pcr_o => open, --ch_pcr(3),
reg_ch4pcr_i => (others => '0'), --std_logic_vector(pulse_cnt(3)),
reg_ch4pcr_load_o => open, --ch_pcr_ld(3),
reg_ch5pcr_o => open, --ch_pcr(4),
reg_ch5pcr_i => (others => '0'), --std_logic_vector(pulse_cnt(4)),
reg_ch5pcr_load_o => open, --ch_pcr_ld(4),
reg_ch6pcr_o => open, --ch_pcr(5),
reg_ch6pcr_i => (others => '0'), --std_logic_vector(pulse_cnt(5)),
reg_ch6pcr_load_o => open, --ch_pcr_ld(5),
reg_ch1pcr_o => ch_pcr(0),
reg_ch1pcr_i => std_logic_vector(pulse_cnt(0)),
reg_ch1pcr_load_o => ch_pcr_ld(0),
reg_ch2pcr_o => ch_pcr(1),
reg_ch2pcr_i => std_logic_vector(pulse_cnt(1)),
reg_ch2pcr_load_o => ch_pcr_ld(1),
reg_ch3pcr_o => ch_pcr(2),
reg_ch3pcr_i => std_logic_vector(pulse_cnt(2)),
reg_ch3pcr_load_o => ch_pcr_ld(2),
reg_ch4pcr_o => ch_pcr(3),
reg_ch4pcr_i => std_logic_vector(pulse_cnt(3)),
reg_ch4pcr_load_o => ch_pcr_ld(3),
reg_ch5pcr_o => ch_pcr(4),
reg_ch5pcr_i => std_logic_vector(pulse_cnt(4)),
reg_ch5pcr_load_o => ch_pcr_ld(4),
reg_ch6pcr_o => ch_pcr(5),
reg_ch6pcr_i => std_logic_vector(pulse_cnt(5)),
reg_ch6pcr_load_o => ch_pcr_ld(5),
reg_tvlr_o => open,
reg_tvlr_i => (others => '0'),
......
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