Voltage level mismatch between PS MIO and AD9516 & AD9510 pins
WR_PLL_STATUS and RF_PLL_STATUS signals are directly tied from AD9516 and AD9510 to PS MIO pins 35 and 36 respectively.
AD9516 and AD9510 have a minimum high level of 2.7V whereas PS MIO pins 35 and 36 are in the bank 501 supplied by the 1.8V.
WR_PLL_STATUS and RF_PLL_STATUS signals must be interfaced by the level translator IC89 converting from 3.3V to 1.8V (used for SPI_MISO signal).