This is note from discussions I had during the FSiC2019 conference.
When you design an ASIC, you need to get a PDK from the foundry. The PDK consists mainly of a library of standard cells, rules for the design (DRC), various parameters... The licence of the PDK is usually very restrictive: you cannot publish anything derived from it. In particular, you cannot publish the layout of your design because it references the cells of the PDK. Even if you do full custom design (you design the transistors by hand), you are not allowed to publish your design because you used the rules or parameters from the PDK to do your design.
So it might be very difficult to use the CERN OHLv2 Less for an ASIC design with a restrictive PDK. Only the permissive licence would be possible.