CernFIP issueshttps://ohwr.org/project/cern-fip/issues2019-02-12T08:37:44Zhttps://ohwr.org/project/cern-fip/issues/1Users Wish: implementation of JC_TRST2019-02-12T08:37:44ZEvangelia GousiouUsers Wish: implementation of JC_TRSTAddition of JC\_TRST: reset pin for remote JTAG updating.
User PA3 FPGA needs TRST to be driven. This can be implemented as
external logic (see attachment),
but may require components that are not likely to be used in the rest of
the design,
which would also need to be qualified in radiation.
Suggested JC\_TRST Pin: 39
### Files
* [nanoFIP_JTAG_JC.pdf](/uploads/e6c9e704c4b5e98aa20a98d88277389b/nanoFIP_JTAG_JC.pdf)https://ohwr.org/project/cern-fip/issues/2Users Wish: addition of SUBS output bus2019-02-12T08:37:45ZEvangelia GousiouUsers Wish: addition of SUBS output busBen Todd explains: addition of SUBS\_O bus which is a route-through of
SUBS\[7:0\]
Allows the connected user to determine the station address, without
interfering with the SUBS read by the nanoFIP.
Suggested SUBS\_O pins:
SUBS\_O \[7\] pin: 148
SUBS\_O \[6\] pin: 147
SUBS\_O \[5\] pin: 146
SUBS\_O \[4\] pin: 145
SUBS\_O \[3\] pin: 144
SUBS\_O \[2\] pin: 143
SUBS\_O \[1\] pin: 139
SUBS\_O \[0\] pin: 138https://ohwr.org/project/cern-fip/issues/3Users Wish: extend RSTON pulse2019-02-12T08:37:45ZEvangelia GousiouUsers Wish: extend RSTON pulseAddition of RSTOLONGN: this is the same function as RSTON but it is a
pulse of 2ms.
Ben Todd explains: Allows the reset output to be connected to analogue
circuitry on our main board.
200ns pulse is quite short for our application, so we have risk of SEU
leading to spurious power cycles, and have quite a short RC-filter on
the signal.
Could also be implemented as external hardware, but could mean
additional logic which may not be used elsewhere in the design,
may need to be qualified in radiation.
Suggested RSTOLONGN pin: 95