Project Description
The Brazilian Synchrotron Light Laboratory (LNLS) is currently designing a third-generation 3 GeV low emmitance synchrotron light source in Campinas, Brazil, called Sirius, with first beam due to the second quarter of 2016. The main parameters of the machine are:
| Parameter | Value | Unit |
| Beam energy | 3.0 | GeV |
| Injection energy (top up) | 3.0 | GeV |
| Beam current | 500 | mA |
| RF frequency | 500 | MHz |
| Harmonic number | 800 | - |
| Natural bunch length | 13.2 | ps |
| Beam size on insertion devices @ 0.5% coupling (horizontal X vertical) | 139.6-195.9 X 2.6-5.6 | um |
| Circumference (storage ring) | 479.664 | m |
In the context of the Sirius project, the Beam Diagnostics Group (DIG) of LNLS has been called to develop a beam position monitoring system (BPM) which must provide electron beam position real-time monitoring, buffered data readouts, fast orbit feedback capabilities and advanced beam diagnostics tools for the new accelerator’s injector and storage ring. This project is primarily intended to deliver a BPM system for the Sirius machine. Nevertheless, it is made open for the particle accelerators community and grand public for design reuse and collaborative development.
The BPM electronics was decomposed into 3 main subsystems: RF front-end ((RFFE), ADC board (ADC) and digital back-end (DBE).
The RF front-end is designed for button BPM pick-ups and must allow 50 dB dynamic range with maximum gain of 60 dB (0 to 5 dBm output). Bandpass filtering must provide 45 MHz bandwidth around the 500 MHz beam's main frequency, with 80 dB attenuation in the stop band.
The ADC board is a FMC mezzanine fully compliant to ANSI/VITA 57.1, providing 4-channel 16-bit 130 MS/s (LTC2208IUP) with 200 MHz bandwidth around 500 MHz. Clocking can be phase-locked to external reference or direct clock inputs . Input/output triggers are also present. It is expected to achieve above 10 bits ENOB and above 80 dBFS SFDR for 500 MHz.
The DBE is a bused system which integrates in a single enclosure BPM processing boards (beam position sensor data processing, data acquisition, advanced diagnostics), FOFB processing boards (feedback control) and a single board computer (control system interface). The FPGA boards are connected to the single board computer via PCIe link. The backplane provides power, JTAG chain access, PCIe switch and point-to-point connection (multigigabit serial links, GPIO, triggers, clocks) between the carriers’ FPGAs.
Status
| Date | Event |
| 20-04-2012 | Start of project in OHR. Hardware designs will be done by external companies and LNLS. |
| 05-2012 | Ask for quotations for RF front-end, ADC board and digital back-end designs. |
| 23-07-2012 | DBE schematics started. Creotech is in charge of the boards design. |