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Beam Positoning Monitor - Software
Commit c757c939 authored by Lucas Russo's avatar Lucas Russo
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include/*: add Trigger Mux register definitions

parent f2fbab25
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include/boards/afcv3/mem_layout.h
View file @ c757c939
...@@ -101,6 +101,17 @@ ...@@ -101,6 +101,17 @@
#define WB_TRIGGER_IFACE_RAW_CTRL_REGS (WB_TRIGGER_IFACE_RAW_ADDR + \ #define WB_TRIGGER_IFACE_RAW_CTRL_REGS (WB_TRIGGER_IFACE_RAW_ADDR + \
WB_TRIGGER_IFACE_RAW_REG_OFFS) WB_TRIGGER_IFACE_RAW_REG_OFFS)
#define WB_TRIGGER_MUX1_RAW_ADDR 0x00400000
#define WB_TRIGGER_MUX1_RAW_CTRL_REGS (WB_TRIGGER_MUX1_RAW_ADDR + \
WB_TRIGGER_MUX_RAW_REG_OFFS)
#define WB_TRIGGER_MUX2_RAW_ADDR 0x00410000
#define WB_TRIGGER_MUX2_RAW_CTRL_REGS (WB_TRIGGER_MUX2_RAW_ADDR + \
WB_TRIGGER_MUX_RAW_REG_OFFS)
/* Large Memory RAW Addresses. It lives at address 0 */ /* Large Memory RAW Addresses. It lives at address 0 */
#define LARGE_MEM_RAW_ADDR 0x00000000 #define LARGE_MEM_RAW_ADDR 0x00000000
...@@ -183,6 +194,15 @@ ...@@ -183,6 +194,15 @@
#define WB_TRIGGER_IFACE_BASE_ADDR (BAR4_ADDR | WB_TRIGGER_IFACE_RAW_ADDR) #define WB_TRIGGER_IFACE_BASE_ADDR (BAR4_ADDR | WB_TRIGGER_IFACE_RAW_ADDR)
#define WB_TRIGGER_IFACE_CTRL_REGS (BAR4_ADDR | WB_TRIGGER_IFACE_RAW_CTRL_REGS) #define WB_TRIGGER_IFACE_CTRL_REGS (BAR4_ADDR | WB_TRIGGER_IFACE_RAW_CTRL_REGS)
#define WB_TRIGGER_MUX1_ADDR (BAR4_ADDR | WB_TRIGGER_MUX1_RAW_ADDR)
#define WB_TRIGGER_MUX1_CTRL_REGS (BAR4_ADDR | WB_TRIGGER_MUX1_RAW_CTRL_REGS)
#define WB_TRIGGER_MUX2_ADDR (BAR4_ADDR | WB_TRIGGER_MUX2_RAW_ADDR)
#define WB_TRIGGER_MUX2_CTRL_REGS (BAR4_ADDR | WB_TRIGGER_MUX2_RAW_CTRL_REGS)
/************************* AFCv3 Gateware Options *************************/ /************************* AFCv3 Gateware Options *************************/
/********************* FMC130M_4CH SMIO Gateware Options ******************/ /********************* FMC130M_4CH SMIO Gateware Options ******************/
......
include/boards/afcv3_1/mem_layout.h
View file @ c757c939
...@@ -101,6 +101,18 @@ ...@@ -101,6 +101,18 @@
#define WB_TRIGGER_IFACE_RAW_CTRL_REGS (WB_TRIGGER_IFACE_RAW_ADDR + \ #define WB_TRIGGER_IFACE_RAW_CTRL_REGS (WB_TRIGGER_IFACE_RAW_ADDR + \
WB_TRIGGER_IFACE_RAW_REG_OFFS) WB_TRIGGER_IFACE_RAW_REG_OFFS)
#define WB_TRIGGER_MUX1_RAW_ADDR 0x00400000
#define WB_TRIGGER_MUX1_RAW_CTRL_REGS (WB_TRIGGER_MUX1_RAW_ADDR + \
WB_TRIGGER_MUX_RAW_REG_OFFS)
#define WB_TRIGGER_MUX2_RAW_ADDR 0x00410000
#define WB_TRIGGER_MUX2_RAW_CTRL_REGS (WB_TRIGGER_MUX2_RAW_ADDR + \
WB_TRIGGER_MUX_RAW_REG_OFFS)
/* Large Memory RAW Addresses. It lives at address 0 */ /* Large Memory RAW Addresses. It lives at address 0 */
#define LARGE_MEM_RAW_ADDR 0x00000000 #define LARGE_MEM_RAW_ADDR 0x00000000
...@@ -183,6 +195,15 @@ ...@@ -183,6 +195,15 @@
#define WB_TRIGGER_IFACE_BASE_ADDR (BAR4_ADDR | WB_TRIGGER_IFACE_RAW_ADDR) #define WB_TRIGGER_IFACE_BASE_ADDR (BAR4_ADDR | WB_TRIGGER_IFACE_RAW_ADDR)
#define WB_TRIGGER_IFACE_CTRL_REGS (BAR4_ADDR | WB_TRIGGER_IFACE_RAW_CTRL_REGS) #define WB_TRIGGER_IFACE_CTRL_REGS (BAR4_ADDR | WB_TRIGGER_IFACE_RAW_CTRL_REGS)
#define WB_TRIGGER_MUX1_ADDR (BAR4_ADDR | WB_TRIGGER_MUX1_RAW_ADDR)
#define WB_TRIGGER_MUX1_CTRL_REGS (BAR4_ADDR | WB_TRIGGER_MUX1_RAW_CTRL_REGS)
#define WB_TRIGGER_MUX2_ADDR (BAR4_ADDR | WB_TRIGGER_MUX2_RAW_ADDR)
#define WB_TRIGGER_MUX2_CTRL_REGS (BAR4_ADDR | WB_TRIGGER_MUX2_RAW_CTRL_REGS)
/************************* AFCv3 Gateware Options *************************/ /************************* AFCv3 Gateware Options *************************/
/********************* FMC130M_4CH SMIO Gateware Options ******************/ /********************* FMC130M_4CH SMIO Gateware Options ******************/
......
include/hw/wb_trigger_mux_regs.h 0 → 100644
View file @ c757c939
This diff is collapsed.
include/mem_layout_common.h
View file @ c757c939
...@@ -40,6 +40,9 @@ extern "C" { ...@@ -40,6 +40,9 @@ extern "C" {
/* Trigger Interface Components */ /* Trigger Interface Components */
#define WB_TRIGGER_IFACE_RAW_REG_OFFS 0x0000 #define WB_TRIGGER_IFACE_RAW_REG_OFFS 0x0000
/* Trigger Mux Components */
#define WB_TRIGGER_MUX_RAW_REG_OFFS 0x0000
/* Large Memory RAW Addresses. It lives at address 0 */ /* Large Memory RAW Addresses. It lives at address 0 */
#define LARGE_MEM_RAW_ADDR 0x00000000 #define LARGE_MEM_RAW_ADDR 0x00000000
......
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