Commit 43330bf3 authored by Lucas Russo's avatar Lucas Russo

sm_io/*/trigger_mux/*: default SW_CLK trigger channel to DSP CLK

parent bc3db3c6
......@@ -64,6 +64,16 @@ smio_err_e trigger_mux_config_defaults (char *broker_endp, char *service,
client_err |= bpm_set_trigger_transm_out_sel (config_client, service, chan, TRIGGER_MUX_DFLT_TRANSM_IN_SEL);
}
/* Switching Trigger. Change it to correct parameters */
client_err = bpm_set_trigger_rcv_src (config_client, service, TRIGGER_MUX_SW_CLK_CHAN,
TRIGGER_MUX_SW_CLK_DFLT_RCV_SRC);
client_err |= bpm_set_trigger_rcv_in_sel (config_client, service, TRIGGER_MUX_SW_CLK_CHAN,
TRIGGER_MUX_SW_CLK_DFLT_RCV_IN_SEL);
client_err |= bpm_set_trigger_transm_src (config_client, service, TRIGGER_MUX_SW_CLK_CHAN,
TRIGGER_MUX_SW_CLK_DFLT_TRANSM_SRC);
client_err |= bpm_set_trigger_transm_out_sel (config_client, service, TRIGGER_MUX_SW_CLK_CHAN,
TRIGGER_MUX_SW_CLK_DFLT_TRANSM_IN_SEL);
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could set trigger mux defaults",
err_param_set, SMIO_ERR_CONFIG_DFLT);
......
......@@ -15,6 +15,13 @@
#define TRIGGER_MUX_DFLT_TRANSM_SRC 0 /* Trigger Backplane */
#define TRIGGER_MUX_DFLT_TRANSM_IN_SEL 0 /* Trigger Index 0 */
/* FIXME. This shoulw be somewhere else*/
#define TRIGGER_MUX_SW_CLK_CHAN 17 /* Trigger Channel */
#define TRIGGER_MUX_SW_CLK_DFLT_RCV_SRC 1 /* FPGA Internal */
#define TRIGGER_MUX_SW_CLK_DFLT_RCV_IN_SEL 1 /* Trigger Index 1 */
#define TRIGGER_MUX_SW_CLK_DFLT_TRANSM_SRC 0 /* FPGA Internal */
#define TRIGGER_MUX_SW_CLK_DFLT_TRANSM_IN_SEL 0 /* Trigger Index 0 */
smio_err_e trigger_mux_config_defaults (char *broker_endp, char *service,
const char *log_file_name);
......
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