diff --git a/examples/trigger.c b/examples/trigger.c
new file mode 100644
index 0000000000000000000000000000000000000000..ab7159c2606f619863b748d819cdbc313b04fcb4
--- /dev/null
+++ b/examples/trigger.c
@@ -0,0 +1,336 @@
+/*
+ * Simple example demonstrating the communication between
+ * a client and the FPGA device
+ *
+ * */
+
+#include <getopt.h>
+#include <czmq.h>
+#include <inttypes.h>
+#include <stdio.h>
+#include <string.h>
+#include <bpm_client.h>
+
+#define DFLT_BIND_FOLDER "/tmp/bpm"
+
+#define DFLT_BPM_NUMBER 0
+#define MAX_BPM_NUMBER 1
+
+#define DFLT_BOARD_NUMBER 0
+
+#define DFLT_CHAN_NUM 0
+
+static struct option long_options[] =
+{
+ {"help", no_argument, NULL, 'h'},
+ {"brokerendp", required_argument, NULL, 'b'},
+ {"verbose", no_argument, NULL, 'v'},
+ {"bpmnumber", required_argument, NULL, 's'},
+ {"boardslot", required_argument, NULL, 'o'},
+ {"channumber", required_argument, NULL, 'c'},
+ {"rcvsrc", required_argument, NULL, 'r'},
+ {"rcvsel", required_argument, NULL, 'p'},
+ {"transmsrc", required_argument, NULL, 't'},
+ {"transsel", required_argument, NULL, 'u'},
+ {"dir", required_argument, NULL, 'd'},
+ {"dirpol", required_argument, NULL, 'x'},
+ {NULL, 0, NULL, 0}
+};
+
+static const char* shortopt = "hb:vo:s:c:r:p:t:u:d:x:";
+
+void print_help (char *program_name)
+{
+ fprintf (stdout, "EBPM Trigger Utility\n"
+ "Usage: %s [options]\n"
+ "\n"
+ " -h --help Display this usage information\n"
+ " -b --brokerendp <Broker endpoint> Broker endpoint\n"
+ " -v --verbose Verbose output\n"
+ " -o --boardslot <Board slot number = [1-12]> \n"
+ " -s --bpmnumber <BPM number = [0|1]> BPM number\n"
+ " Board slot number\n"
+ " -c --channumber <Channel | Channel Range>\n"
+ " Trigger Channel number\n"
+ " <Channel> must be one of the following:\n"
+ " 0 -> ADC; 1 -> ADC_SWAP; 2 -> Mixer IQ120; 3 -> Mixer IQ340;\n"
+ " 4 -> TBT Decim IQ120; 5 -> TBT Decim IQ340; 6 -> TBT Amp;\n"
+ " 7 -> TBT Phase; 8 -> TBT Pos; 9 -> FOFB Decim IQ120;\n"
+ " 10 -> FOFB Decim IQ340; 11 -> FOFB Amp; 12 -> FOFB Pha;\n"
+ " 13 -> FOFB Pos; 14 -> Monit Amp; 15 -> Monit Pha; 16 -> Monit Pos]\n"
+ " 17 -> Swithcing Clock]\n"
+ " -r --rcvsrc <Receive source for the selected channel = [0 = trigger backplane, 1 = FPGA internal]> \n"
+ " -p --rcvsel <Receive selection source for the selected channel = [TBD]> \n"
+ " -t --transmsrc <Transmit source for the selected channel = [0 = trigger backplane, 1 = FPGA internal]> \n"
+ " -u --transmsel <Transmit selection source for the selected channel = [TBD]> \n"
+ " -d --dir <Trigger direction = [0 = FPGA Output, 1 = FPGA Input]> \n"
+ " -x --dirpol <Trigger direction polarity = [0 = Polarity unchanged, 1 = Polarity reversed]> \n",
+ program_name);
+}
+
+int main (int argc, char *argv [])
+{
+ int verbose = 0;
+ char *broker_endp = NULL;
+ char *num_samples_str = NULL;
+ char *board_number_str = NULL;
+ char *bpm_number_str = NULL;
+ char *chan_str = NULL;
+ int chan_sel = 0;
+ char *rcvsrc_str = NULL;
+ int rcvsrc_sel = 0;
+ char *rcvsel_str = NULL;
+ int rcvsel_sel = 0;
+ char *transmsrc_str = NULL;
+ int transmsrc_sel = 0;
+ char *transmsel_str = NULL;
+ int transmsel_sel = 0;
+ char *dir_str = NULL;
+ int dir_sel = 0;
+ char *dirpol_str = NULL;
+ int dirpol_sel = 0;
+ int opt;
+
+ while ((opt = getopt_long (argc, argv, shortopt, long_options, NULL)) != -1) {
+ /* Get the user selected options */
+ switch (opt) {
+ /* Display Help */
+ case 'h':
+ print_help (argv [0]);
+ exit (1);
+ break;
+
+ case 'b':
+ broker_endp = strdup (optarg);
+ break;
+
+ case 'v':
+ verbose = 1;
+ break;
+
+ case 'o':
+ board_number_str = strdup (optarg);
+ break;
+
+ case 's':
+ bpm_number_str = strdup (optarg);
+ break;
+
+ case 'c':
+ chan_str = strdup (optarg);
+ chan_sel = 1;
+ break;
+
+ case 'r':
+ rcvsrc_str = strdup (optarg);
+ rcvsrc_sel = 1;
+ break;
+
+ case 'p':
+ rcvsel_str = strdup (optarg);
+ rcvsel_sel = 1;
+ break;
+
+ case 't':
+ transmsrc_str = strdup (optarg);
+ transmsrc_sel = 1;
+ break;
+
+ case 'u':
+ transmsel_str = strdup (optarg);
+ transmsel_sel = 1;
+ break;
+
+ case 'd':
+ dir_str = strdup (optarg);
+ dir_sel = 1;
+ break;
+
+ case 'x':
+ dirpol_str = strdup (optarg);
+ dirpol_sel = 1;
+ break;
+
+ case '?':
+ fprintf (stderr, "[client:trigger] Option not recognized or missing argument\n");
+ print_help (argv [0]);
+ exit (1);
+ break;
+
+ default:
+ fprintf (stderr, "[client:trigger] Could not parse options\n");
+ print_help (argv [0]);
+ exit (1);
+ }
+ }
+
+ /* If we want to change a channel property, we must select a channel first */
+ if ((rcvsrc_sel == 1 || rcvsel_sel == 1 || transmsrc_sel == 1 || transmsel_sel == 1 ||
+ dir_sel == 1 || dirpol_sel == 1) && chan_sel == 0) {
+ fprintf (stderr, "[client:trigger]: Channel number not selected (use -c or --channumber option)\n");
+ exit (1);
+ }
+
+ /* Set default broker address */
+ if (broker_endp == NULL) {
+ fprintf (stderr, "[client:trigger]: Setting default broker endpoint: %s\n",
+ "ipc://"DFLT_BIND_FOLDER);
+ broker_endp = strdup ("ipc://"DFLT_BIND_FOLDER);
+ }
+
+ /* Set default channel */
+ uint32_t chan_min;
+ uint32_t chan_max;
+ if (chan_str == NULL) {
+ fprintf (stderr, "[client:trigger]: Setting default value to 'chan'\n");
+ chan_min = DFLT_CHAN_NUM;
+ chan_max = chan_min+1;
+ }
+ else {
+ if (sscanf (chan_str, "[%u:%u]", &chan_min, &chan_max) != 2) {
+ if (sscanf (chan_str, "%u", &chan_min) != 1) {
+ fprintf (stderr, "[client:trigger]: Unexpected channel format\n");
+ exit (1);
+ }
+ chan_max = chan_min+1;
+ }
+ else {
+ chan_max++;
+ }
+
+ if (chan_max < chan_min) {
+ fprintf (stderr, "[client:trigger]: Channel range must be ascending\n");
+ exit (1);
+ }
+ }
+
+ /* Set default board number */
+ uint32_t board_number;
+ if (board_number_str == NULL) {
+ fprintf (stderr, "[client:trigger]: Setting default value to BOARD number: %u\n",
+ DFLT_BOARD_NUMBER);
+ board_number = DFLT_BOARD_NUMBER;
+ }
+ else {
+ board_number = strtoul (board_number_str, NULL, 10);
+ }
+
+ /* Set default bpm number */
+ uint32_t bpm_number;
+ if (bpm_number_str == NULL) {
+ fprintf (stderr, "[client:trigger]: Setting default value to BPM number: %u\n",
+ DFLT_BPM_NUMBER);
+ bpm_number = DFLT_BPM_NUMBER;
+ }
+ else {
+ bpm_number = strtoul (bpm_number_str, NULL, 10);
+
+ if (bpm_number > MAX_BPM_NUMBER) {
+ fprintf (stderr, "[client:trigger]: BPM number too big! Defaulting to: %u\n",
+ MAX_BPM_NUMBER);
+ bpm_number = MAX_BPM_NUMBER;
+ }
+ }
+
+ char service_iface[50];
+ snprintf (service_iface, sizeof (service_iface), "BPM%u:DEVIO:TRIGGER_IFACE0", board_number);
+ char service_mux[50];
+ snprintf (service_mux, sizeof (service_mux), "BPM%u:DEVIO:TRIGGER_MUX%u", board_number, bpm_number);
+
+ bpm_client_t *bpm_client = bpm_client_new (broker_endp, verbose, NULL);
+ if (bpm_client == NULL) {
+ fprintf (stderr, "[client:trigger]: bpm_client could be created\n");
+ goto err_bpm_client_new;
+ }
+
+ uint32_t chan;
+ for (chan = chan_min; chan < chan_max; ++chan) {
+ uint32_t rcvsrc = 0;
+ if (rcvsrc_sel == 1) {
+ rcvsrc = strtoul (rcvsrc_str, NULL, 10);
+ bpm_client_err_e err = bpm_set_trigger_rcv_src (bpm_client, service_mux, chan, rcvsrc);
+ if (err != BPM_CLIENT_SUCCESS){
+ fprintf (stderr, "[client:trigger]: bpm_set_trigger_rcv_src failed\n");
+ goto err_bpm_set;
+ }
+ }
+
+ uint32_t rcvsel = 0;
+ if (rcvsel_sel == 1) {
+ rcvsel = strtoul (rcvsel_str, NULL, 10);
+ bpm_client_err_e err = bpm_set_trigger_rcv_in_sel (bpm_client, service_mux, chan, rcvsel);
+ if (err != BPM_CLIENT_SUCCESS){
+ fprintf (stderr, "[client:trigger]: bpm_set_trigger_rcv_sel failed\n");
+ goto err_bpm_set;
+ }
+ }
+
+ uint32_t transmsrc = 0;
+ if (transmsrc_sel == 1) {
+ transmsrc = strtoul (transmsrc_str, NULL, 10);
+ bpm_client_err_e err = bpm_set_trigger_transm_src (bpm_client, service_mux, chan, transmsrc);
+ if (err != BPM_CLIENT_SUCCESS){
+ fprintf (stderr, "[client:trigger]: bpm_set_trigger_transm_sel failed\n");
+ goto err_bpm_set;
+ }
+ }
+
+ uint32_t transmsel = 0;
+ if (transmsel_sel == 1) {
+ transmsel = strtoul (transmsel_str, NULL, 10);
+ bpm_client_err_e err = bpm_set_trigger_transm_out_sel (bpm_client, service_mux, chan, transmsel);
+ if (err != BPM_CLIENT_SUCCESS){
+ fprintf (stderr, "[client:trigger]: bpm_set_trigger_transm_sel failed\n");
+ goto err_bpm_set;
+ }
+ }
+
+ uint32_t dir = 0;
+ if (dir_sel == 1) {
+ dir = strtoul (dir_str, NULL, 10);
+ bpm_client_err_e err = bpm_set_trigger_dir (bpm_client, service_iface, chan, dir);
+ if (err != BPM_CLIENT_SUCCESS){
+ fprintf (stderr, "[client:trigger]: bpm_set_trigger_dir failed\n");
+ goto err_bpm_set;
+ }
+ }
+
+ uint32_t dirpol = 0;
+ if (dirpol_sel == 1) {
+ dirpol = strtoul (dirpol_str, NULL, 10);
+ bpm_client_err_e err = bpm_set_trigger_dir_pol (bpm_client, service_iface, chan, dirpol);
+ if (err != BPM_CLIENT_SUCCESS){
+ fprintf (stderr, "[client:trigger]: bpm_set_trigger_dir_pol failed\n");
+ goto err_bpm_set;
+ }
+ }
+ }
+
+err_bpm_set:
+err_bpm_client_new:
+ free (dirpol_str);
+ dirpol_str = NULL;
+ free (dir_str);
+ dir_str = NULL;
+ free (transmsel_str);
+ transmsel_str = NULL;
+ free (transmsrc_str);
+ transmsrc_str = NULL;
+ free (rcvsel_str);
+ rcvsel_str = NULL;
+ free (rcvsrc_str);
+ rcvsrc_str = NULL;
+ free (chan_str);
+ chan_str = NULL;
+ free (board_number_str);
+ board_number_str = NULL;
+ free (bpm_number_str);
+ bpm_number_str = NULL;
+ free (num_samples_str);
+ num_samples_str = NULL;
+ free (broker_endp);
+ broker_endp = NULL;
+ bpm_client_destroy (&bpm_client);
+
+ return 0;
+}
diff --git a/include/boards/afcv3/mem_layout.h b/include/boards/afcv3/mem_layout.h
index d0f0b42a186431e0466f92f4379fd469c26984f4..c976bc4e6e0ee979bc919fedb0463c300c6d5da1 100644
--- a/include/boards/afcv3/mem_layout.h
+++ b/include/boards/afcv3/mem_layout.h
@@ -97,6 +97,21 @@
#define WB_AFC_DIAG_CTRL_RAW_REGS (WB_AFC_DIAG_RAW_ADDR + \
WB_AFC_DIAG_CTRL_RAW_REGS_OFFS)
+#define WB_TRIGGER_IFACE_RAW_ADDR 0x00390000
+
+#define WB_TRIGGER_IFACE_RAW_CTRL_REGS (WB_TRIGGER_IFACE_RAW_ADDR + \
+ WB_TRIGGER_IFACE_RAW_REG_OFFS)
+
+#define WB_TRIGGER_MUX1_RAW_ADDR 0x00400000
+
+#define WB_TRIGGER_MUX1_RAW_CTRL_REGS (WB_TRIGGER_MUX1_RAW_ADDR + \
+ WB_TRIGGER_MUX_RAW_REG_OFFS)
+
+#define WB_TRIGGER_MUX2_RAW_ADDR 0x00410000
+
+#define WB_TRIGGER_MUX2_RAW_CTRL_REGS (WB_TRIGGER_MUX2_RAW_ADDR + \
+ WB_TRIGGER_MUX_RAW_REG_OFFS)
+
/* Large Memory RAW Addresses. It lives at address 0 */
#define LARGE_MEM_RAW_ADDR 0x00000000
@@ -176,6 +191,18 @@
#define WB_AFC_DIAG_CTRL_REGS (BAR4_ADDR | WB_AFC_DIAG_CTRL_RAW_REGS)
+#define WB_TRIGGER_IFACE_BASE_ADDR (BAR4_ADDR | WB_TRIGGER_IFACE_RAW_ADDR)
+
+#define WB_TRIGGER_IFACE_CTRL_REGS (BAR4_ADDR | WB_TRIGGER_IFACE_RAW_CTRL_REGS)
+
+#define WB_TRIGGER_MUX1_BASE_ADDR (BAR4_ADDR | WB_TRIGGER_MUX1_RAW_ADDR)
+
+#define WB_TRIGGER_MUX1_CTRL_REGS (BAR4_ADDR | WB_TRIGGER_MUX1_RAW_CTRL_REGS)
+
+#define WB_TRIGGER_MUX2_BASE_ADDR (BAR4_ADDR | WB_TRIGGER_MUX2_RAW_ADDR)
+
+#define WB_TRIGGER_MUX2_CTRL_REGS (BAR4_ADDR | WB_TRIGGER_MUX2_RAW_CTRL_REGS)
+
/************************* AFCv3 Gateware Options *************************/
/********************* FMC130M_4CH SMIO Gateware Options ******************/
diff --git a/include/boards/afcv3_1/mem_layout.h b/include/boards/afcv3_1/mem_layout.h
index d0f0b42a186431e0466f92f4379fd469c26984f4..1e65c35a219afd334fcd00d985c22f033b46a9b9 100644
--- a/include/boards/afcv3_1/mem_layout.h
+++ b/include/boards/afcv3_1/mem_layout.h
@@ -97,6 +97,22 @@
#define WB_AFC_DIAG_CTRL_RAW_REGS (WB_AFC_DIAG_RAW_ADDR + \
WB_AFC_DIAG_CTRL_RAW_REGS_OFFS)
+#define WB_TRIGGER_IFACE_RAW_ADDR 0x00390000
+
+#define WB_TRIGGER_IFACE_RAW_CTRL_REGS (WB_TRIGGER_IFACE_RAW_ADDR + \
+ WB_TRIGGER_IFACE_RAW_REG_OFFS)
+
+#define WB_TRIGGER_MUX1_RAW_ADDR 0x00400000
+
+#define WB_TRIGGER_MUX1_RAW_CTRL_REGS (WB_TRIGGER_MUX1_RAW_ADDR + \
+ WB_TRIGGER_MUX_RAW_REG_OFFS)
+
+#define WB_TRIGGER_MUX2_RAW_ADDR 0x00410000
+
+#define WB_TRIGGER_MUX2_RAW_CTRL_REGS (WB_TRIGGER_MUX2_RAW_ADDR + \
+ WB_TRIGGER_MUX_RAW_REG_OFFS)
+
+
/* Large Memory RAW Addresses. It lives at address 0 */
#define LARGE_MEM_RAW_ADDR 0x00000000
@@ -176,6 +192,18 @@
#define WB_AFC_DIAG_CTRL_REGS (BAR4_ADDR | WB_AFC_DIAG_CTRL_RAW_REGS)
+#define WB_TRIGGER_IFACE_BASE_ADDR (BAR4_ADDR | WB_TRIGGER_IFACE_RAW_ADDR)
+
+#define WB_TRIGGER_IFACE_CTRL_REGS (BAR4_ADDR | WB_TRIGGER_IFACE_RAW_CTRL_REGS)
+
+#define WB_TRIGGER_MUX1_BASE_ADDR (BAR4_ADDR | WB_TRIGGER_MUX1_RAW_ADDR)
+
+#define WB_TRIGGER_MUX1_CTRL_REGS (BAR4_ADDR | WB_TRIGGER_MUX1_RAW_CTRL_REGS)
+
+#define WB_TRIGGER_MUX2_BASE_ADDR (BAR4_ADDR | WB_TRIGGER_MUX2_RAW_ADDR)
+
+#define WB_TRIGGER_MUX2_CTRL_REGS (BAR4_ADDR | WB_TRIGGER_MUX2_RAW_CTRL_REGS)
+
/************************* AFCv3 Gateware Options *************************/
/********************* FMC130M_4CH SMIO Gateware Options ******************/
diff --git a/include/hw/wb_trigger_iface_regs.h b/include/hw/wb_trigger_iface_regs.h
new file mode 100644
index 0000000000000000000000000000000000000000..c269e751683091e808111eadaae32b63f3db418c
--- /dev/null
+++ b/include/hw/wb_trigger_iface_regs.h
@@ -0,0 +1,1185 @@
+/*
+ Register definitions for slave core: Control and status register for the MLVDS trigger
+
+ * File : wb_trigger_iface_regs.h
+ * Author : auto-generated by wbgen2 from wb_trigger_iface.wb
+ * Created : Fri May 20 13:37:27 2016
+ * Standard : ANSI C
+
+ THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_trigger_iface.wb
+ DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+
+*/
+
+#ifndef __WBGEN2_REGDEFS_WB_TRIGGER_IFACE_WB
+#define __WBGEN2_REGDEFS_WB_TRIGGER_IFACE_WB
+
+#include <inttypes.h>
+
+#if defined( __GNUC__)
+#define PACKED __attribute__ ((packed))
+#else
+#error "Unsupported compiler?"
+#endif
+
+#ifndef __WBGEN2_MACROS_DEFINED__
+#define __WBGEN2_MACROS_DEFINED__
+#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
+#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
+#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
+#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
+#endif
+
+
+/* definitions for register: Channel 0 Control */
+
+/* definitions for field: Trigger Direction in reg: Channel 0 Control */
+#define WB_TRIG_IFACE_CH0_CTL_DIR WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Trigger Direction Polarity in reg: Channel 0 Control */
+#define WB_TRIG_IFACE_CH0_CTL_DIR_POL WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for field: Receiver Pulse Counter Reset in reg: Channel 0 Control */
+#define WB_TRIG_IFACE_CH0_CTL_RCV_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+
+/* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 0 Control */
+#define WB_TRIG_IFACE_CH0_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
+
+/* definitions for register: Channel 0 Configuration Parameters */
+
+/* definitions for field: Receiver Pulse Length in reg: Channel 0 Configuration Parameters */
+#define WB_TRIG_IFACE_CH0_CFG_RCV_LEN_MASK WBGEN2_GEN_MASK(0, 8)
+#define WB_TRIG_IFACE_CH0_CFG_RCV_LEN_SHIFT 0
+#define WB_TRIG_IFACE_CH0_CFG_RCV_LEN_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
+#define WB_TRIG_IFACE_CH0_CFG_RCV_LEN_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
+
+/* definitions for field: Transmitter Pulse Length in reg: Channel 0 Configuration Parameters */
+#define WB_TRIG_IFACE_CH0_CFG_TRANSM_LEN_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_IFACE_CH0_CFG_TRANSM_LEN_SHIFT 8
+#define WB_TRIG_IFACE_CH0_CFG_TRANSM_LEN_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_IFACE_CH0_CFG_TRANSM_LEN_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for register: Channel 0 Transmitter/Receiver Pulses Counter */
+
+/* definitions for field: Receiver Counter in reg: Channel 0 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH0_COUNT_RCV_MASK WBGEN2_GEN_MASK(0, 16)
+#define WB_TRIG_IFACE_CH0_COUNT_RCV_SHIFT 0
+#define WB_TRIG_IFACE_CH0_COUNT_RCV_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
+#define WB_TRIG_IFACE_CH0_COUNT_RCV_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
+
+/* definitions for field: Transmitter Counter in reg: Channel 0 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH0_COUNT_TRANSM_MASK WBGEN2_GEN_MASK(16, 16)
+#define WB_TRIG_IFACE_CH0_COUNT_TRANSM_SHIFT 16
+#define WB_TRIG_IFACE_CH0_COUNT_TRANSM_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
+#define WB_TRIG_IFACE_CH0_COUNT_TRANSM_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
+
+/* definitions for register: Channel 1 Control */
+
+/* definitions for field: Trigger Direction in reg: Channel 1 Control */
+#define WB_TRIG_IFACE_CH1_CTL_DIR WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Trigger Direction Polarity in reg: Channel 1 Control */
+#define WB_TRIG_IFACE_CH1_CTL_DIR_POL WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for field: Receiver Pulse Counter Reset in reg: Channel 1 Control */
+#define WB_TRIG_IFACE_CH1_CTL_RCV_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+
+/* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 1 Control */
+#define WB_TRIG_IFACE_CH1_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
+
+/* definitions for register: Channel 1 Configuration Parameters */
+
+/* definitions for field: Receiver Pulse Length in reg: Channel 1 Configuration Parameters */
+#define WB_TRIG_IFACE_CH1_CFG_RCV_LEN_MASK WBGEN2_GEN_MASK(0, 8)
+#define WB_TRIG_IFACE_CH1_CFG_RCV_LEN_SHIFT 0
+#define WB_TRIG_IFACE_CH1_CFG_RCV_LEN_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
+#define WB_TRIG_IFACE_CH1_CFG_RCV_LEN_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
+
+/* definitions for field: Transmitter Pulse Length in reg: Channel 1 Configuration Parameters */
+#define WB_TRIG_IFACE_CH1_CFG_TRANSM_LEN_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_IFACE_CH1_CFG_TRANSM_LEN_SHIFT 8
+#define WB_TRIG_IFACE_CH1_CFG_TRANSM_LEN_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_IFACE_CH1_CFG_TRANSM_LEN_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for register: Channel 1 Transmitter/Receiver Pulses Counter */
+
+/* definitions for field: Receiver Counter in reg: Channel 1 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH1_COUNT_RCV_MASK WBGEN2_GEN_MASK(0, 16)
+#define WB_TRIG_IFACE_CH1_COUNT_RCV_SHIFT 0
+#define WB_TRIG_IFACE_CH1_COUNT_RCV_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
+#define WB_TRIG_IFACE_CH1_COUNT_RCV_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
+
+/* definitions for field: Transmitter Counter in reg: Channel 1 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH1_COUNT_TRANSM_MASK WBGEN2_GEN_MASK(16, 16)
+#define WB_TRIG_IFACE_CH1_COUNT_TRANSM_SHIFT 16
+#define WB_TRIG_IFACE_CH1_COUNT_TRANSM_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
+#define WB_TRIG_IFACE_CH1_COUNT_TRANSM_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
+
+/* definitions for register: Channel 2 Control */
+
+/* definitions for field: Trigger Direction in reg: Channel 2 Control */
+#define WB_TRIG_IFACE_CH2_CTL_DIR WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Trigger Direction Polarity in reg: Channel 2 Control */
+#define WB_TRIG_IFACE_CH2_CTL_DIR_POL WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for field: Receiver Pulse Counter Reset in reg: Channel 2 Control */
+#define WB_TRIG_IFACE_CH2_CTL_RCV_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+
+/* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 2 Control */
+#define WB_TRIG_IFACE_CH2_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
+
+/* definitions for register: Channel 2 Configuration Parameters */
+
+/* definitions for field: Receiver Pulse Length in reg: Channel 2 Configuration Parameters */
+#define WB_TRIG_IFACE_CH2_CFG_RCV_LEN_MASK WBGEN2_GEN_MASK(0, 8)
+#define WB_TRIG_IFACE_CH2_CFG_RCV_LEN_SHIFT 0
+#define WB_TRIG_IFACE_CH2_CFG_RCV_LEN_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
+#define WB_TRIG_IFACE_CH2_CFG_RCV_LEN_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
+
+/* definitions for field: Transmitter Pulse Length in reg: Channel 2 Configuration Parameters */
+#define WB_TRIG_IFACE_CH2_CFG_TRANSM_LEN_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_IFACE_CH2_CFG_TRANSM_LEN_SHIFT 8
+#define WB_TRIG_IFACE_CH2_CFG_TRANSM_LEN_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_IFACE_CH2_CFG_TRANSM_LEN_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for register: Channel 2 Transmitter/Receiver Pulses Counter */
+
+/* definitions for field: Receiver Counter in reg: Channel 2 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH2_COUNT_RCV_MASK WBGEN2_GEN_MASK(0, 16)
+#define WB_TRIG_IFACE_CH2_COUNT_RCV_SHIFT 0
+#define WB_TRIG_IFACE_CH2_COUNT_RCV_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
+#define WB_TRIG_IFACE_CH2_COUNT_RCV_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
+
+/* definitions for field: Transmitter Counter in reg: Channel 2 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH2_COUNT_TRANSM_MASK WBGEN2_GEN_MASK(16, 16)
+#define WB_TRIG_IFACE_CH2_COUNT_TRANSM_SHIFT 16
+#define WB_TRIG_IFACE_CH2_COUNT_TRANSM_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
+#define WB_TRIG_IFACE_CH2_COUNT_TRANSM_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
+
+/* definitions for register: Channel 3 Control */
+
+/* definitions for field: Trigger Direction in reg: Channel 3 Control */
+#define WB_TRIG_IFACE_CH3_CTL_DIR WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Trigger Direction Polarity in reg: Channel 3 Control */
+#define WB_TRIG_IFACE_CH3_CTL_DIR_POL WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for field: Receiver Pulse Counter Reset in reg: Channel 3 Control */
+#define WB_TRIG_IFACE_CH3_CTL_RCV_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+
+/* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 3 Control */
+#define WB_TRIG_IFACE_CH3_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
+
+/* definitions for register: Channel 3 Configuration Parameters */
+
+/* definitions for field: Receiver Pulse Length in reg: Channel 3 Configuration Parameters */
+#define WB_TRIG_IFACE_CH3_CFG_RCV_LEN_MASK WBGEN2_GEN_MASK(0, 8)
+#define WB_TRIG_IFACE_CH3_CFG_RCV_LEN_SHIFT 0
+#define WB_TRIG_IFACE_CH3_CFG_RCV_LEN_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
+#define WB_TRIG_IFACE_CH3_CFG_RCV_LEN_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
+
+/* definitions for field: Transmitter Pulse Length in reg: Channel 3 Configuration Parameters */
+#define WB_TRIG_IFACE_CH3_CFG_TRANSM_LEN_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_IFACE_CH3_CFG_TRANSM_LEN_SHIFT 8
+#define WB_TRIG_IFACE_CH3_CFG_TRANSM_LEN_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_IFACE_CH3_CFG_TRANSM_LEN_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for register: Channel 3 Transmitter/Receiver Pulses Counter */
+
+/* definitions for field: Receiver Counter in reg: Channel 3 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH3_COUNT_RCV_MASK WBGEN2_GEN_MASK(0, 16)
+#define WB_TRIG_IFACE_CH3_COUNT_RCV_SHIFT 0
+#define WB_TRIG_IFACE_CH3_COUNT_RCV_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
+#define WB_TRIG_IFACE_CH3_COUNT_RCV_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
+
+/* definitions for field: Transmitter Counter in reg: Channel 3 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH3_COUNT_TRANSM_MASK WBGEN2_GEN_MASK(16, 16)
+#define WB_TRIG_IFACE_CH3_COUNT_TRANSM_SHIFT 16
+#define WB_TRIG_IFACE_CH3_COUNT_TRANSM_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
+#define WB_TRIG_IFACE_CH3_COUNT_TRANSM_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
+
+/* definitions for register: Channel 4 Control */
+
+/* definitions for field: Trigger Direction in reg: Channel 4 Control */
+#define WB_TRIG_IFACE_CH4_CTL_DIR WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Trigger Direction Polarity in reg: Channel 4 Control */
+#define WB_TRIG_IFACE_CH4_CTL_DIR_POL WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for field: Receiver Pulse Counter Reset in reg: Channel 4 Control */
+#define WB_TRIG_IFACE_CH4_CTL_RCV_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+
+/* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 4 Control */
+#define WB_TRIG_IFACE_CH4_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
+
+/* definitions for register: Channel 4 Configuration Parameters */
+
+/* definitions for field: Receiver Pulse Length in reg: Channel 4 Configuration Parameters */
+#define WB_TRIG_IFACE_CH4_CFG_RCV_LEN_MASK WBGEN2_GEN_MASK(0, 8)
+#define WB_TRIG_IFACE_CH4_CFG_RCV_LEN_SHIFT 0
+#define WB_TRIG_IFACE_CH4_CFG_RCV_LEN_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
+#define WB_TRIG_IFACE_CH4_CFG_RCV_LEN_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
+
+/* definitions for field: Transmitter Pulse Length in reg: Channel 4 Configuration Parameters */
+#define WB_TRIG_IFACE_CH4_CFG_TRANSM_LEN_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_IFACE_CH4_CFG_TRANSM_LEN_SHIFT 8
+#define WB_TRIG_IFACE_CH4_CFG_TRANSM_LEN_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_IFACE_CH4_CFG_TRANSM_LEN_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for register: Channel 4 Transmitter/Receiver Pulses Counter */
+
+/* definitions for field: Receiver Counter in reg: Channel 4 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH4_COUNT_RCV_MASK WBGEN2_GEN_MASK(0, 16)
+#define WB_TRIG_IFACE_CH4_COUNT_RCV_SHIFT 0
+#define WB_TRIG_IFACE_CH4_COUNT_RCV_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
+#define WB_TRIG_IFACE_CH4_COUNT_RCV_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
+
+/* definitions for field: Transmitter Counter in reg: Channel 4 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH4_COUNT_TRANSM_MASK WBGEN2_GEN_MASK(16, 16)
+#define WB_TRIG_IFACE_CH4_COUNT_TRANSM_SHIFT 16
+#define WB_TRIG_IFACE_CH4_COUNT_TRANSM_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
+#define WB_TRIG_IFACE_CH4_COUNT_TRANSM_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
+
+/* definitions for register: Channel 5 Control */
+
+/* definitions for field: Trigger Direction in reg: Channel 5 Control */
+#define WB_TRIG_IFACE_CH5_CTL_DIR WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Trigger Direction Polarity in reg: Channel 5 Control */
+#define WB_TRIG_IFACE_CH5_CTL_DIR_POL WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for field: Receiver Pulse Counter Reset in reg: Channel 5 Control */
+#define WB_TRIG_IFACE_CH5_CTL_RCV_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+
+/* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 5 Control */
+#define WB_TRIG_IFACE_CH5_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
+
+/* definitions for register: Channel 5 Configuration Parameters */
+
+/* definitions for field: Receiver Pulse Length in reg: Channel 5 Configuration Parameters */
+#define WB_TRIG_IFACE_CH5_CFG_RCV_LEN_MASK WBGEN2_GEN_MASK(0, 8)
+#define WB_TRIG_IFACE_CH5_CFG_RCV_LEN_SHIFT 0
+#define WB_TRIG_IFACE_CH5_CFG_RCV_LEN_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
+#define WB_TRIG_IFACE_CH5_CFG_RCV_LEN_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
+
+/* definitions for field: Transmitter Pulse Length in reg: Channel 5 Configuration Parameters */
+#define WB_TRIG_IFACE_CH5_CFG_TRANSM_LEN_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_IFACE_CH5_CFG_TRANSM_LEN_SHIFT 8
+#define WB_TRIG_IFACE_CH5_CFG_TRANSM_LEN_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_IFACE_CH5_CFG_TRANSM_LEN_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for register: Channel 5 Transmitter/Receiver Pulses Counter */
+
+/* definitions for field: Receiver Counter in reg: Channel 5 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH5_COUNT_RCV_MASK WBGEN2_GEN_MASK(0, 16)
+#define WB_TRIG_IFACE_CH5_COUNT_RCV_SHIFT 0
+#define WB_TRIG_IFACE_CH5_COUNT_RCV_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
+#define WB_TRIG_IFACE_CH5_COUNT_RCV_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
+
+/* definitions for field: Transmitter Counter in reg: Channel 5 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH5_COUNT_TRANSM_MASK WBGEN2_GEN_MASK(16, 16)
+#define WB_TRIG_IFACE_CH5_COUNT_TRANSM_SHIFT 16
+#define WB_TRIG_IFACE_CH5_COUNT_TRANSM_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
+#define WB_TRIG_IFACE_CH5_COUNT_TRANSM_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
+
+/* definitions for register: Channel 6 Control */
+
+/* definitions for field: Trigger Direction in reg: Channel 6 Control */
+#define WB_TRIG_IFACE_CH6_CTL_DIR WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Trigger Direction Polarity in reg: Channel 6 Control */
+#define WB_TRIG_IFACE_CH6_CTL_DIR_POL WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for field: Receiver Pulse Counter Reset in reg: Channel 6 Control */
+#define WB_TRIG_IFACE_CH6_CTL_RCV_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+
+/* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 6 Control */
+#define WB_TRIG_IFACE_CH6_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
+
+/* definitions for register: Channel 6 Configuration Parameters */
+
+/* definitions for field: Receiver Pulse Length in reg: Channel 6 Configuration Parameters */
+#define WB_TRIG_IFACE_CH6_CFG_RCV_LEN_MASK WBGEN2_GEN_MASK(0, 8)
+#define WB_TRIG_IFACE_CH6_CFG_RCV_LEN_SHIFT 0
+#define WB_TRIG_IFACE_CH6_CFG_RCV_LEN_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
+#define WB_TRIG_IFACE_CH6_CFG_RCV_LEN_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
+
+/* definitions for field: Transmitter Pulse Length in reg: Channel 6 Configuration Parameters */
+#define WB_TRIG_IFACE_CH6_CFG_TRANSM_LEN_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_IFACE_CH6_CFG_TRANSM_LEN_SHIFT 8
+#define WB_TRIG_IFACE_CH6_CFG_TRANSM_LEN_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_IFACE_CH6_CFG_TRANSM_LEN_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for register: Channel 6 Transmitter/Receiver Pulses Counter */
+
+/* definitions for field: Receiver Counter in reg: Channel 6 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH6_COUNT_RCV_MASK WBGEN2_GEN_MASK(0, 16)
+#define WB_TRIG_IFACE_CH6_COUNT_RCV_SHIFT 0
+#define WB_TRIG_IFACE_CH6_COUNT_RCV_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
+#define WB_TRIG_IFACE_CH6_COUNT_RCV_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
+
+/* definitions for field: Transmitter Counter in reg: Channel 6 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH6_COUNT_TRANSM_MASK WBGEN2_GEN_MASK(16, 16)
+#define WB_TRIG_IFACE_CH6_COUNT_TRANSM_SHIFT 16
+#define WB_TRIG_IFACE_CH6_COUNT_TRANSM_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
+#define WB_TRIG_IFACE_CH6_COUNT_TRANSM_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
+
+/* definitions for register: Channel 7 Control */
+
+/* definitions for field: Trigger Direction in reg: Channel 7 Control */
+#define WB_TRIG_IFACE_CH7_CTL_DIR WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Trigger Direction Polarity in reg: Channel 7 Control */
+#define WB_TRIG_IFACE_CH7_CTL_DIR_POL WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for field: Receiver Pulse Counter Reset in reg: Channel 7 Control */
+#define WB_TRIG_IFACE_CH7_CTL_RCV_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+
+/* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 7 Control */
+#define WB_TRIG_IFACE_CH7_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
+
+/* definitions for register: Channel 7 Configuration Parameters */
+
+/* definitions for field: Receiver Pulse Length in reg: Channel 7 Configuration Parameters */
+#define WB_TRIG_IFACE_CH7_CFG_RCV_LEN_MASK WBGEN2_GEN_MASK(0, 8)
+#define WB_TRIG_IFACE_CH7_CFG_RCV_LEN_SHIFT 0
+#define WB_TRIG_IFACE_CH7_CFG_RCV_LEN_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
+#define WB_TRIG_IFACE_CH7_CFG_RCV_LEN_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
+
+/* definitions for field: Transmitter Pulse Length in reg: Channel 7 Configuration Parameters */
+#define WB_TRIG_IFACE_CH7_CFG_TRANSM_LEN_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_IFACE_CH7_CFG_TRANSM_LEN_SHIFT 8
+#define WB_TRIG_IFACE_CH7_CFG_TRANSM_LEN_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_IFACE_CH7_CFG_TRANSM_LEN_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for register: Channel 7 Transmitter/Receiver Pulses Counter */
+
+/* definitions for field: Receiver Counter in reg: Channel 7 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH7_COUNT_RCV_MASK WBGEN2_GEN_MASK(0, 16)
+#define WB_TRIG_IFACE_CH7_COUNT_RCV_SHIFT 0
+#define WB_TRIG_IFACE_CH7_COUNT_RCV_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
+#define WB_TRIG_IFACE_CH7_COUNT_RCV_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
+
+/* definitions for field: Transmitter Counter in reg: Channel 7 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH7_COUNT_TRANSM_MASK WBGEN2_GEN_MASK(16, 16)
+#define WB_TRIG_IFACE_CH7_COUNT_TRANSM_SHIFT 16
+#define WB_TRIG_IFACE_CH7_COUNT_TRANSM_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
+#define WB_TRIG_IFACE_CH7_COUNT_TRANSM_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
+
+/* definitions for register: Channel 8 Control */
+
+/* definitions for field: Trigger Direction in reg: Channel 8 Control */
+#define WB_TRIG_IFACE_CH8_CTL_DIR WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Trigger Direction Polarity in reg: Channel 8 Control */
+#define WB_TRIG_IFACE_CH8_CTL_DIR_POL WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for field: Receiver Pulse Counter Reset in reg: Channel 8 Control */
+#define WB_TRIG_IFACE_CH8_CTL_RCV_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+
+/* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 8 Control */
+#define WB_TRIG_IFACE_CH8_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
+
+/* definitions for register: Channel 8 Configuration Parameters */
+
+/* definitions for field: Receiver Pulse Length in reg: Channel 8 Configuration Parameters */
+#define WB_TRIG_IFACE_CH8_CFG_RCV_LEN_MASK WBGEN2_GEN_MASK(0, 8)
+#define WB_TRIG_IFACE_CH8_CFG_RCV_LEN_SHIFT 0
+#define WB_TRIG_IFACE_CH8_CFG_RCV_LEN_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
+#define WB_TRIG_IFACE_CH8_CFG_RCV_LEN_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
+
+/* definitions for field: Transmitter Pulse Length in reg: Channel 8 Configuration Parameters */
+#define WB_TRIG_IFACE_CH8_CFG_TRANSM_LEN_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_IFACE_CH8_CFG_TRANSM_LEN_SHIFT 8
+#define WB_TRIG_IFACE_CH8_CFG_TRANSM_LEN_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_IFACE_CH8_CFG_TRANSM_LEN_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for register: Channel 8 Transmitter/Receiver Pulses Counter */
+
+/* definitions for field: Receiver Counter in reg: Channel 8 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH8_COUNT_RCV_MASK WBGEN2_GEN_MASK(0, 16)
+#define WB_TRIG_IFACE_CH8_COUNT_RCV_SHIFT 0
+#define WB_TRIG_IFACE_CH8_COUNT_RCV_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
+#define WB_TRIG_IFACE_CH8_COUNT_RCV_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
+
+/* definitions for field: Transmitter Counter in reg: Channel 8 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH8_COUNT_TRANSM_MASK WBGEN2_GEN_MASK(16, 16)
+#define WB_TRIG_IFACE_CH8_COUNT_TRANSM_SHIFT 16
+#define WB_TRIG_IFACE_CH8_COUNT_TRANSM_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
+#define WB_TRIG_IFACE_CH8_COUNT_TRANSM_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
+
+/* definitions for register: Channel 9 Control */
+
+/* definitions for field: Trigger Direction in reg: Channel 9 Control */
+#define WB_TRIG_IFACE_CH9_CTL_DIR WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Trigger Direction Polarity in reg: Channel 9 Control */
+#define WB_TRIG_IFACE_CH9_CTL_DIR_POL WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for field: Receiver Pulse Counter Reset in reg: Channel 9 Control */
+#define WB_TRIG_IFACE_CH9_CTL_RCV_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+
+/* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 9 Control */
+#define WB_TRIG_IFACE_CH9_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
+
+/* definitions for register: Channel 9 Configuration Parameters */
+
+/* definitions for field: Receiver Pulse Length in reg: Channel 9 Configuration Parameters */
+#define WB_TRIG_IFACE_CH9_CFG_RCV_LEN_MASK WBGEN2_GEN_MASK(0, 8)
+#define WB_TRIG_IFACE_CH9_CFG_RCV_LEN_SHIFT 0
+#define WB_TRIG_IFACE_CH9_CFG_RCV_LEN_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
+#define WB_TRIG_IFACE_CH9_CFG_RCV_LEN_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
+
+/* definitions for field: Transmitter Pulse Length in reg: Channel 9 Configuration Parameters */
+#define WB_TRIG_IFACE_CH9_CFG_TRANSM_LEN_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_IFACE_CH9_CFG_TRANSM_LEN_SHIFT 8
+#define WB_TRIG_IFACE_CH9_CFG_TRANSM_LEN_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_IFACE_CH9_CFG_TRANSM_LEN_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for register: Channel 9 Transmitter/Receiver Pulses Counter */
+
+/* definitions for field: Receiver Counter in reg: Channel 9 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH9_COUNT_RCV_MASK WBGEN2_GEN_MASK(0, 16)
+#define WB_TRIG_IFACE_CH9_COUNT_RCV_SHIFT 0
+#define WB_TRIG_IFACE_CH9_COUNT_RCV_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
+#define WB_TRIG_IFACE_CH9_COUNT_RCV_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
+
+/* definitions for field: Transmitter Counter in reg: Channel 9 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH9_COUNT_TRANSM_MASK WBGEN2_GEN_MASK(16, 16)
+#define WB_TRIG_IFACE_CH9_COUNT_TRANSM_SHIFT 16
+#define WB_TRIG_IFACE_CH9_COUNT_TRANSM_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
+#define WB_TRIG_IFACE_CH9_COUNT_TRANSM_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
+
+/* definitions for register: Channel 10 Control */
+
+/* definitions for field: Trigger Direction in reg: Channel 10 Control */
+#define WB_TRIG_IFACE_CH10_CTL_DIR WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Trigger Direction Polarity in reg: Channel 10 Control */
+#define WB_TRIG_IFACE_CH10_CTL_DIR_POL WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for field: Receiver Pulse Counter Reset in reg: Channel 10 Control */
+#define WB_TRIG_IFACE_CH10_CTL_RCV_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+
+/* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 10 Control */
+#define WB_TRIG_IFACE_CH10_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
+
+/* definitions for register: Channel 10 Configuration Parameters */
+
+/* definitions for field: Receiver Pulse Length in reg: Channel 10 Configuration Parameters */
+#define WB_TRIG_IFACE_CH10_CFG_RCV_LEN_MASK WBGEN2_GEN_MASK(0, 8)
+#define WB_TRIG_IFACE_CH10_CFG_RCV_LEN_SHIFT 0
+#define WB_TRIG_IFACE_CH10_CFG_RCV_LEN_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
+#define WB_TRIG_IFACE_CH10_CFG_RCV_LEN_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
+
+/* definitions for field: Transmitter Pulse Length in reg: Channel 10 Configuration Parameters */
+#define WB_TRIG_IFACE_CH10_CFG_TRANSM_LEN_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_IFACE_CH10_CFG_TRANSM_LEN_SHIFT 8
+#define WB_TRIG_IFACE_CH10_CFG_TRANSM_LEN_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_IFACE_CH10_CFG_TRANSM_LEN_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for register: Channel 10 Transmitter/Receiver Pulses Counter */
+
+/* definitions for field: Receiver Counter in reg: Channel 10 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH10_COUNT_RCV_MASK WBGEN2_GEN_MASK(0, 16)
+#define WB_TRIG_IFACE_CH10_COUNT_RCV_SHIFT 0
+#define WB_TRIG_IFACE_CH10_COUNT_RCV_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
+#define WB_TRIG_IFACE_CH10_COUNT_RCV_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
+
+/* definitions for field: Transmitter Counter in reg: Channel 10 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH10_COUNT_TRANSM_MASK WBGEN2_GEN_MASK(16, 16)
+#define WB_TRIG_IFACE_CH10_COUNT_TRANSM_SHIFT 16
+#define WB_TRIG_IFACE_CH10_COUNT_TRANSM_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
+#define WB_TRIG_IFACE_CH10_COUNT_TRANSM_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
+
+/* definitions for register: Channel 11 Control */
+
+/* definitions for field: Trigger Direction in reg: Channel 11 Control */
+#define WB_TRIG_IFACE_CH11_CTL_DIR WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Trigger Direction Polarity in reg: Channel 11 Control */
+#define WB_TRIG_IFACE_CH11_CTL_DIR_POL WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for field: Receiver Pulse Counter Reset in reg: Channel 11 Control */
+#define WB_TRIG_IFACE_CH11_CTL_RCV_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+
+/* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 11 Control */
+#define WB_TRIG_IFACE_CH11_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
+
+/* definitions for register: Channel 11 Configuration Parameters */
+
+/* definitions for field: Receiver Pulse Length in reg: Channel 11 Configuration Parameters */
+#define WB_TRIG_IFACE_CH11_CFG_RCV_LEN_MASK WBGEN2_GEN_MASK(0, 8)
+#define WB_TRIG_IFACE_CH11_CFG_RCV_LEN_SHIFT 0
+#define WB_TRIG_IFACE_CH11_CFG_RCV_LEN_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
+#define WB_TRIG_IFACE_CH11_CFG_RCV_LEN_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
+
+/* definitions for field: Transmitter Pulse Length in reg: Channel 11 Configuration Parameters */
+#define WB_TRIG_IFACE_CH11_CFG_TRANSM_LEN_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_IFACE_CH11_CFG_TRANSM_LEN_SHIFT 8
+#define WB_TRIG_IFACE_CH11_CFG_TRANSM_LEN_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_IFACE_CH11_CFG_TRANSM_LEN_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for register: Channel 11 Transmitter/Receiver Pulses Counter */
+
+/* definitions for field: Receiver Counter in reg: Channel 11 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH11_COUNT_RCV_MASK WBGEN2_GEN_MASK(0, 16)
+#define WB_TRIG_IFACE_CH11_COUNT_RCV_SHIFT 0
+#define WB_TRIG_IFACE_CH11_COUNT_RCV_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
+#define WB_TRIG_IFACE_CH11_COUNT_RCV_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
+
+/* definitions for field: Transmitter Counter in reg: Channel 11 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH11_COUNT_TRANSM_MASK WBGEN2_GEN_MASK(16, 16)
+#define WB_TRIG_IFACE_CH11_COUNT_TRANSM_SHIFT 16
+#define WB_TRIG_IFACE_CH11_COUNT_TRANSM_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
+#define WB_TRIG_IFACE_CH11_COUNT_TRANSM_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
+
+/* definitions for register: Channel 12 Control */
+
+/* definitions for field: Trigger Direction in reg: Channel 12 Control */
+#define WB_TRIG_IFACE_CH12_CTL_DIR WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Trigger Direction Polarity in reg: Channel 12 Control */
+#define WB_TRIG_IFACE_CH12_CTL_DIR_POL WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for field: Receiver Pulse Counter Reset in reg: Channel 12 Control */
+#define WB_TRIG_IFACE_CH12_CTL_RCV_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+
+/* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 12 Control */
+#define WB_TRIG_IFACE_CH12_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
+
+/* definitions for register: Channel 12 Configuration Parameters */
+
+/* definitions for field: Receiver Pulse Length in reg: Channel 12 Configuration Parameters */
+#define WB_TRIG_IFACE_CH12_CFG_RCV_LEN_MASK WBGEN2_GEN_MASK(0, 8)
+#define WB_TRIG_IFACE_CH12_CFG_RCV_LEN_SHIFT 0
+#define WB_TRIG_IFACE_CH12_CFG_RCV_LEN_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
+#define WB_TRIG_IFACE_CH12_CFG_RCV_LEN_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
+
+/* definitions for field: Transmitter Pulse Length in reg: Channel 12 Configuration Parameters */
+#define WB_TRIG_IFACE_CH12_CFG_TRANSM_LEN_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_IFACE_CH12_CFG_TRANSM_LEN_SHIFT 8
+#define WB_TRIG_IFACE_CH12_CFG_TRANSM_LEN_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_IFACE_CH12_CFG_TRANSM_LEN_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for register: Channel 12 Transmitter/Receiver Pulses Counter */
+
+/* definitions for field: Receiver Counter in reg: Channel 12 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH12_COUNT_RCV_MASK WBGEN2_GEN_MASK(0, 16)
+#define WB_TRIG_IFACE_CH12_COUNT_RCV_SHIFT 0
+#define WB_TRIG_IFACE_CH12_COUNT_RCV_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
+#define WB_TRIG_IFACE_CH12_COUNT_RCV_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
+
+/* definitions for field: Transmitter Counter in reg: Channel 12 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH12_COUNT_TRANSM_MASK WBGEN2_GEN_MASK(16, 16)
+#define WB_TRIG_IFACE_CH12_COUNT_TRANSM_SHIFT 16
+#define WB_TRIG_IFACE_CH12_COUNT_TRANSM_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
+#define WB_TRIG_IFACE_CH12_COUNT_TRANSM_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
+
+/* definitions for register: Channel 13 Control */
+
+/* definitions for field: Trigger Direction in reg: Channel 13 Control */
+#define WB_TRIG_IFACE_CH13_CTL_DIR WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Trigger Direction Polarity in reg: Channel 13 Control */
+#define WB_TRIG_IFACE_CH13_CTL_DIR_POL WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for field: Receiver Pulse Counter Reset in reg: Channel 13 Control */
+#define WB_TRIG_IFACE_CH13_CTL_RCV_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+
+/* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 13 Control */
+#define WB_TRIG_IFACE_CH13_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
+
+/* definitions for register: Channel 13 Configuration Parameters */
+
+/* definitions for field: Receiver Pulse Length in reg: Channel 13 Configuration Parameters */
+#define WB_TRIG_IFACE_CH13_CFG_RCV_LEN_MASK WBGEN2_GEN_MASK(0, 8)
+#define WB_TRIG_IFACE_CH13_CFG_RCV_LEN_SHIFT 0
+#define WB_TRIG_IFACE_CH13_CFG_RCV_LEN_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
+#define WB_TRIG_IFACE_CH13_CFG_RCV_LEN_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
+
+/* definitions for field: Transmitter Pulse Length in reg: Channel 13 Configuration Parameters */
+#define WB_TRIG_IFACE_CH13_CFG_TRANSM_LEN_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_IFACE_CH13_CFG_TRANSM_LEN_SHIFT 8
+#define WB_TRIG_IFACE_CH13_CFG_TRANSM_LEN_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_IFACE_CH13_CFG_TRANSM_LEN_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for register: Channel 13 Transmitter/Receiver Pulses Counter */
+
+/* definitions for field: Receiver Counter in reg: Channel 13 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH13_COUNT_RCV_MASK WBGEN2_GEN_MASK(0, 16)
+#define WB_TRIG_IFACE_CH13_COUNT_RCV_SHIFT 0
+#define WB_TRIG_IFACE_CH13_COUNT_RCV_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
+#define WB_TRIG_IFACE_CH13_COUNT_RCV_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
+
+/* definitions for field: Transmitter Counter in reg: Channel 13 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH13_COUNT_TRANSM_MASK WBGEN2_GEN_MASK(16, 16)
+#define WB_TRIG_IFACE_CH13_COUNT_TRANSM_SHIFT 16
+#define WB_TRIG_IFACE_CH13_COUNT_TRANSM_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
+#define WB_TRIG_IFACE_CH13_COUNT_TRANSM_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
+
+/* definitions for register: Channel 14 Control */
+
+/* definitions for field: Trigger Direction in reg: Channel 14 Control */
+#define WB_TRIG_IFACE_CH14_CTL_DIR WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Trigger Direction Polarity in reg: Channel 14 Control */
+#define WB_TRIG_IFACE_CH14_CTL_DIR_POL WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for field: Receiver Pulse Counter Reset in reg: Channel 14 Control */
+#define WB_TRIG_IFACE_CH14_CTL_RCV_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+
+/* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 14 Control */
+#define WB_TRIG_IFACE_CH14_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
+
+/* definitions for register: Channel 14 Configuration Parameters */
+
+/* definitions for field: Receiver Pulse Length in reg: Channel 14 Configuration Parameters */
+#define WB_TRIG_IFACE_CH14_CFG_RCV_LEN_MASK WBGEN2_GEN_MASK(0, 8)
+#define WB_TRIG_IFACE_CH14_CFG_RCV_LEN_SHIFT 0
+#define WB_TRIG_IFACE_CH14_CFG_RCV_LEN_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
+#define WB_TRIG_IFACE_CH14_CFG_RCV_LEN_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
+
+/* definitions for field: Transmitter Pulse Length in reg: Channel 14 Configuration Parameters */
+#define WB_TRIG_IFACE_CH14_CFG_TRANSM_LEN_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_IFACE_CH14_CFG_TRANSM_LEN_SHIFT 8
+#define WB_TRIG_IFACE_CH14_CFG_TRANSM_LEN_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_IFACE_CH14_CFG_TRANSM_LEN_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for register: Channel 14 Transmitter/Receiver Pulses Counter */
+
+/* definitions for field: Receiver Counter in reg: Channel 14 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH14_COUNT_RCV_MASK WBGEN2_GEN_MASK(0, 16)
+#define WB_TRIG_IFACE_CH14_COUNT_RCV_SHIFT 0
+#define WB_TRIG_IFACE_CH14_COUNT_RCV_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
+#define WB_TRIG_IFACE_CH14_COUNT_RCV_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
+
+/* definitions for field: Transmitter Counter in reg: Channel 14 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH14_COUNT_TRANSM_MASK WBGEN2_GEN_MASK(16, 16)
+#define WB_TRIG_IFACE_CH14_COUNT_TRANSM_SHIFT 16
+#define WB_TRIG_IFACE_CH14_COUNT_TRANSM_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
+#define WB_TRIG_IFACE_CH14_COUNT_TRANSM_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
+
+/* definitions for register: Channel 15 Control */
+
+/* definitions for field: Trigger Direction in reg: Channel 15 Control */
+#define WB_TRIG_IFACE_CH15_CTL_DIR WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Trigger Direction Polarity in reg: Channel 15 Control */
+#define WB_TRIG_IFACE_CH15_CTL_DIR_POL WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for field: Receiver Pulse Counter Reset in reg: Channel 15 Control */
+#define WB_TRIG_IFACE_CH15_CTL_RCV_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+
+/* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 15 Control */
+#define WB_TRIG_IFACE_CH15_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
+
+/* definitions for register: Channel 15 Configuration Parameters */
+
+/* definitions for field: Receiver Pulse Length in reg: Channel 15 Configuration Parameters */
+#define WB_TRIG_IFACE_CH15_CFG_RCV_LEN_MASK WBGEN2_GEN_MASK(0, 8)
+#define WB_TRIG_IFACE_CH15_CFG_RCV_LEN_SHIFT 0
+#define WB_TRIG_IFACE_CH15_CFG_RCV_LEN_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
+#define WB_TRIG_IFACE_CH15_CFG_RCV_LEN_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
+
+/* definitions for field: Transmitter Pulse Length in reg: Channel 15 Configuration Parameters */
+#define WB_TRIG_IFACE_CH15_CFG_TRANSM_LEN_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_IFACE_CH15_CFG_TRANSM_LEN_SHIFT 8
+#define WB_TRIG_IFACE_CH15_CFG_TRANSM_LEN_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_IFACE_CH15_CFG_TRANSM_LEN_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for register: Channel 15 Transmitter/Receiver Pulses Counter */
+
+/* definitions for field: Receiver Counter in reg: Channel 15 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH15_COUNT_RCV_MASK WBGEN2_GEN_MASK(0, 16)
+#define WB_TRIG_IFACE_CH15_COUNT_RCV_SHIFT 0
+#define WB_TRIG_IFACE_CH15_COUNT_RCV_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
+#define WB_TRIG_IFACE_CH15_COUNT_RCV_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
+
+/* definitions for field: Transmitter Counter in reg: Channel 15 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH15_COUNT_TRANSM_MASK WBGEN2_GEN_MASK(16, 16)
+#define WB_TRIG_IFACE_CH15_COUNT_TRANSM_SHIFT 16
+#define WB_TRIG_IFACE_CH15_COUNT_TRANSM_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
+#define WB_TRIG_IFACE_CH15_COUNT_TRANSM_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
+
+/* definitions for register: Channel 16 Control */
+
+/* definitions for field: Trigger Direction in reg: Channel 16 Control */
+#define WB_TRIG_IFACE_CH16_CTL_DIR WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Trigger Direction Polarity in reg: Channel 16 Control */
+#define WB_TRIG_IFACE_CH16_CTL_DIR_POL WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for field: Receiver Pulse Counter Reset in reg: Channel 16 Control */
+#define WB_TRIG_IFACE_CH16_CTL_RCV_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+
+/* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 16 Control */
+#define WB_TRIG_IFACE_CH16_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
+
+/* definitions for register: Channel 16 Configuration Parameters */
+
+/* definitions for field: Receiver Pulse Length in reg: Channel 16 Configuration Parameters */
+#define WB_TRIG_IFACE_CH16_CFG_RCV_LEN_MASK WBGEN2_GEN_MASK(0, 8)
+#define WB_TRIG_IFACE_CH16_CFG_RCV_LEN_SHIFT 0
+#define WB_TRIG_IFACE_CH16_CFG_RCV_LEN_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
+#define WB_TRIG_IFACE_CH16_CFG_RCV_LEN_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
+
+/* definitions for field: Transmitter Pulse Length in reg: Channel 16 Configuration Parameters */
+#define WB_TRIG_IFACE_CH16_CFG_TRANSM_LEN_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_IFACE_CH16_CFG_TRANSM_LEN_SHIFT 8
+#define WB_TRIG_IFACE_CH16_CFG_TRANSM_LEN_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_IFACE_CH16_CFG_TRANSM_LEN_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for register: Channel 16 Transmitter/Receiver Pulses Counter */
+
+/* definitions for field: Receiver Counter in reg: Channel 16 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH16_COUNT_RCV_MASK WBGEN2_GEN_MASK(0, 16)
+#define WB_TRIG_IFACE_CH16_COUNT_RCV_SHIFT 0
+#define WB_TRIG_IFACE_CH16_COUNT_RCV_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
+#define WB_TRIG_IFACE_CH16_COUNT_RCV_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
+
+/* definitions for field: Transmitter Counter in reg: Channel 16 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH16_COUNT_TRANSM_MASK WBGEN2_GEN_MASK(16, 16)
+#define WB_TRIG_IFACE_CH16_COUNT_TRANSM_SHIFT 16
+#define WB_TRIG_IFACE_CH16_COUNT_TRANSM_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
+#define WB_TRIG_IFACE_CH16_COUNT_TRANSM_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
+
+/* definitions for register: Channel 17 Control */
+
+/* definitions for field: Trigger Direction in reg: Channel 17 Control */
+#define WB_TRIG_IFACE_CH17_CTL_DIR WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Trigger Direction Polarity in reg: Channel 17 Control */
+#define WB_TRIG_IFACE_CH17_CTL_DIR_POL WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for field: Receiver Pulse Counter Reset in reg: Channel 17 Control */
+#define WB_TRIG_IFACE_CH17_CTL_RCV_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+
+/* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 17 Control */
+#define WB_TRIG_IFACE_CH17_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
+
+/* definitions for register: Channel 17 Configuration Parameters */
+
+/* definitions for field: Receiver Pulse Length in reg: Channel 17 Configuration Parameters */
+#define WB_TRIG_IFACE_CH17_CFG_RCV_LEN_MASK WBGEN2_GEN_MASK(0, 8)
+#define WB_TRIG_IFACE_CH17_CFG_RCV_LEN_SHIFT 0
+#define WB_TRIG_IFACE_CH17_CFG_RCV_LEN_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
+#define WB_TRIG_IFACE_CH17_CFG_RCV_LEN_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
+
+/* definitions for field: Transmitter Pulse Length in reg: Channel 17 Configuration Parameters */
+#define WB_TRIG_IFACE_CH17_CFG_TRANSM_LEN_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_IFACE_CH17_CFG_TRANSM_LEN_SHIFT 8
+#define WB_TRIG_IFACE_CH17_CFG_TRANSM_LEN_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_IFACE_CH17_CFG_TRANSM_LEN_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for register: Channel 17 Transmitter/Receiver Pulses Counter */
+
+/* definitions for field: Receiver Counter in reg: Channel 17 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH17_COUNT_RCV_MASK WBGEN2_GEN_MASK(0, 16)
+#define WB_TRIG_IFACE_CH17_COUNT_RCV_SHIFT 0
+#define WB_TRIG_IFACE_CH17_COUNT_RCV_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
+#define WB_TRIG_IFACE_CH17_COUNT_RCV_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
+
+/* definitions for field: Transmitter Counter in reg: Channel 17 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH17_COUNT_TRANSM_MASK WBGEN2_GEN_MASK(16, 16)
+#define WB_TRIG_IFACE_CH17_COUNT_TRANSM_SHIFT 16
+#define WB_TRIG_IFACE_CH17_COUNT_TRANSM_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
+#define WB_TRIG_IFACE_CH17_COUNT_TRANSM_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
+
+/* definitions for register: Channel 18 Control */
+
+/* definitions for field: Trigger Direction in reg: Channel 18 Control */
+#define WB_TRIG_IFACE_CH18_CTL_DIR WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Trigger Direction Polarity in reg: Channel 18 Control */
+#define WB_TRIG_IFACE_CH18_CTL_DIR_POL WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for field: Receiver Pulse Counter Reset in reg: Channel 18 Control */
+#define WB_TRIG_IFACE_CH18_CTL_RCV_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+
+/* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 18 Control */
+#define WB_TRIG_IFACE_CH18_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
+
+/* definitions for register: Channel 18 Configuration Parameters */
+
+/* definitions for field: Receiver Pulse Length in reg: Channel 18 Configuration Parameters */
+#define WB_TRIG_IFACE_CH18_CFG_RCV_LEN_MASK WBGEN2_GEN_MASK(0, 8)
+#define WB_TRIG_IFACE_CH18_CFG_RCV_LEN_SHIFT 0
+#define WB_TRIG_IFACE_CH18_CFG_RCV_LEN_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
+#define WB_TRIG_IFACE_CH18_CFG_RCV_LEN_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
+
+/* definitions for field: Transmitter Pulse Length in reg: Channel 18 Configuration Parameters */
+#define WB_TRIG_IFACE_CH18_CFG_TRANSM_LEN_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_IFACE_CH18_CFG_TRANSM_LEN_SHIFT 8
+#define WB_TRIG_IFACE_CH18_CFG_TRANSM_LEN_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_IFACE_CH18_CFG_TRANSM_LEN_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for register: Channel 18 Transmitter/Receiver Pulses Counter */
+
+/* definitions for field: Receiver Counter in reg: Channel 18 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH18_COUNT_RCV_MASK WBGEN2_GEN_MASK(0, 16)
+#define WB_TRIG_IFACE_CH18_COUNT_RCV_SHIFT 0
+#define WB_TRIG_IFACE_CH18_COUNT_RCV_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
+#define WB_TRIG_IFACE_CH18_COUNT_RCV_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
+
+/* definitions for field: Transmitter Counter in reg: Channel 18 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH18_COUNT_TRANSM_MASK WBGEN2_GEN_MASK(16, 16)
+#define WB_TRIG_IFACE_CH18_COUNT_TRANSM_SHIFT 16
+#define WB_TRIG_IFACE_CH18_COUNT_TRANSM_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
+#define WB_TRIG_IFACE_CH18_COUNT_TRANSM_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
+
+/* definitions for register: Channel 19 Control */
+
+/* definitions for field: Trigger Direction in reg: Channel 19 Control */
+#define WB_TRIG_IFACE_CH19_CTL_DIR WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Trigger Direction Polarity in reg: Channel 19 Control */
+#define WB_TRIG_IFACE_CH19_CTL_DIR_POL WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for field: Receiver Pulse Counter Reset in reg: Channel 19 Control */
+#define WB_TRIG_IFACE_CH19_CTL_RCV_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+
+/* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 19 Control */
+#define WB_TRIG_IFACE_CH19_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
+
+/* definitions for register: Channel 19 Configuration Parameters */
+
+/* definitions for field: Receiver Pulse Length in reg: Channel 19 Configuration Parameters */
+#define WB_TRIG_IFACE_CH19_CFG_RCV_LEN_MASK WBGEN2_GEN_MASK(0, 8)
+#define WB_TRIG_IFACE_CH19_CFG_RCV_LEN_SHIFT 0
+#define WB_TRIG_IFACE_CH19_CFG_RCV_LEN_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
+#define WB_TRIG_IFACE_CH19_CFG_RCV_LEN_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
+
+/* definitions for field: Transmitter Pulse Length in reg: Channel 19 Configuration Parameters */
+#define WB_TRIG_IFACE_CH19_CFG_TRANSM_LEN_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_IFACE_CH19_CFG_TRANSM_LEN_SHIFT 8
+#define WB_TRIG_IFACE_CH19_CFG_TRANSM_LEN_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_IFACE_CH19_CFG_TRANSM_LEN_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for register: Channel 19 Transmitter/Receiver Pulses Counter */
+
+/* definitions for field: Receiver Counter in reg: Channel 19 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH19_COUNT_RCV_MASK WBGEN2_GEN_MASK(0, 16)
+#define WB_TRIG_IFACE_CH19_COUNT_RCV_SHIFT 0
+#define WB_TRIG_IFACE_CH19_COUNT_RCV_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
+#define WB_TRIG_IFACE_CH19_COUNT_RCV_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
+
+/* definitions for field: Transmitter Counter in reg: Channel 19 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH19_COUNT_TRANSM_MASK WBGEN2_GEN_MASK(16, 16)
+#define WB_TRIG_IFACE_CH19_COUNT_TRANSM_SHIFT 16
+#define WB_TRIG_IFACE_CH19_COUNT_TRANSM_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
+#define WB_TRIG_IFACE_CH19_COUNT_TRANSM_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
+
+/* definitions for register: Channel 20 Control */
+
+/* definitions for field: Trigger Direction in reg: Channel 20 Control */
+#define WB_TRIG_IFACE_CH20_CTL_DIR WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Trigger Direction Polarity in reg: Channel 20 Control */
+#define WB_TRIG_IFACE_CH20_CTL_DIR_POL WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for field: Receiver Pulse Counter Reset in reg: Channel 20 Control */
+#define WB_TRIG_IFACE_CH20_CTL_RCV_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+
+/* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 20 Control */
+#define WB_TRIG_IFACE_CH20_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
+
+/* definitions for register: Channel 20 Configuration Parameters */
+
+/* definitions for field: Receiver Pulse Length in reg: Channel 20 Configuration Parameters */
+#define WB_TRIG_IFACE_CH20_CFG_RCV_LEN_MASK WBGEN2_GEN_MASK(0, 8)
+#define WB_TRIG_IFACE_CH20_CFG_RCV_LEN_SHIFT 0
+#define WB_TRIG_IFACE_CH20_CFG_RCV_LEN_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
+#define WB_TRIG_IFACE_CH20_CFG_RCV_LEN_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
+
+/* definitions for field: Transmitter Pulse Length in reg: Channel 20 Configuration Parameters */
+#define WB_TRIG_IFACE_CH20_CFG_TRANSM_LEN_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_IFACE_CH20_CFG_TRANSM_LEN_SHIFT 8
+#define WB_TRIG_IFACE_CH20_CFG_TRANSM_LEN_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_IFACE_CH20_CFG_TRANSM_LEN_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for register: Channel 20 Transmitter/Receiver Pulses Counter */
+
+/* definitions for field: Receiver Counter in reg: Channel 20 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH20_COUNT_RCV_MASK WBGEN2_GEN_MASK(0, 16)
+#define WB_TRIG_IFACE_CH20_COUNT_RCV_SHIFT 0
+#define WB_TRIG_IFACE_CH20_COUNT_RCV_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
+#define WB_TRIG_IFACE_CH20_COUNT_RCV_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
+
+/* definitions for field: Transmitter Counter in reg: Channel 20 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH20_COUNT_TRANSM_MASK WBGEN2_GEN_MASK(16, 16)
+#define WB_TRIG_IFACE_CH20_COUNT_TRANSM_SHIFT 16
+#define WB_TRIG_IFACE_CH20_COUNT_TRANSM_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
+#define WB_TRIG_IFACE_CH20_COUNT_TRANSM_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
+
+/* definitions for register: Channel 21 Control */
+
+/* definitions for field: Trigger Direction in reg: Channel 21 Control */
+#define WB_TRIG_IFACE_CH21_CTL_DIR WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Trigger Direction Polarity in reg: Channel 21 Control */
+#define WB_TRIG_IFACE_CH21_CTL_DIR_POL WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for field: Receiver Pulse Counter Reset in reg: Channel 21 Control */
+#define WB_TRIG_IFACE_CH21_CTL_RCV_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+
+/* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 21 Control */
+#define WB_TRIG_IFACE_CH21_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
+
+/* definitions for register: Channel 21 Configuration Parameters */
+
+/* definitions for field: Receiver Pulse Length in reg: Channel 21 Configuration Parameters */
+#define WB_TRIG_IFACE_CH21_CFG_RCV_LEN_MASK WBGEN2_GEN_MASK(0, 8)
+#define WB_TRIG_IFACE_CH21_CFG_RCV_LEN_SHIFT 0
+#define WB_TRIG_IFACE_CH21_CFG_RCV_LEN_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
+#define WB_TRIG_IFACE_CH21_CFG_RCV_LEN_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
+
+/* definitions for field: Transmitter Pulse Length in reg: Channel 21 Configuration Parameters */
+#define WB_TRIG_IFACE_CH21_CFG_TRANSM_LEN_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_IFACE_CH21_CFG_TRANSM_LEN_SHIFT 8
+#define WB_TRIG_IFACE_CH21_CFG_TRANSM_LEN_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_IFACE_CH21_CFG_TRANSM_LEN_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for register: Channel 21 Transmitter/Receiver Pulses Counter */
+
+/* definitions for field: Receiver Counter in reg: Channel 21 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH21_COUNT_RCV_MASK WBGEN2_GEN_MASK(0, 16)
+#define WB_TRIG_IFACE_CH21_COUNT_RCV_SHIFT 0
+#define WB_TRIG_IFACE_CH21_COUNT_RCV_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
+#define WB_TRIG_IFACE_CH21_COUNT_RCV_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
+
+/* definitions for field: Transmitter Counter in reg: Channel 21 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH21_COUNT_TRANSM_MASK WBGEN2_GEN_MASK(16, 16)
+#define WB_TRIG_IFACE_CH21_COUNT_TRANSM_SHIFT 16
+#define WB_TRIG_IFACE_CH21_COUNT_TRANSM_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
+#define WB_TRIG_IFACE_CH21_COUNT_TRANSM_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
+
+/* definitions for register: Channel 22 Control */
+
+/* definitions for field: Trigger Direction in reg: Channel 22 Control */
+#define WB_TRIG_IFACE_CH22_CTL_DIR WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Trigger Direction Polarity in reg: Channel 22 Control */
+#define WB_TRIG_IFACE_CH22_CTL_DIR_POL WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for field: Receiver Pulse Counter Reset in reg: Channel 22 Control */
+#define WB_TRIG_IFACE_CH22_CTL_RCV_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+
+/* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 22 Control */
+#define WB_TRIG_IFACE_CH22_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
+
+/* definitions for register: Channel 22 Configuration Parameters */
+
+/* definitions for field: Receiver Pulse Length in reg: Channel 22 Configuration Parameters */
+#define WB_TRIG_IFACE_CH22_CFG_RCV_LEN_MASK WBGEN2_GEN_MASK(0, 8)
+#define WB_TRIG_IFACE_CH22_CFG_RCV_LEN_SHIFT 0
+#define WB_TRIG_IFACE_CH22_CFG_RCV_LEN_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
+#define WB_TRIG_IFACE_CH22_CFG_RCV_LEN_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
+
+/* definitions for field: Transmitter Pulse Length in reg: Channel 22 Configuration Parameters */
+#define WB_TRIG_IFACE_CH22_CFG_TRANSM_LEN_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_IFACE_CH22_CFG_TRANSM_LEN_SHIFT 8
+#define WB_TRIG_IFACE_CH22_CFG_TRANSM_LEN_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_IFACE_CH22_CFG_TRANSM_LEN_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for register: Channel 22 Transmitter/Receiver Pulses Counter */
+
+/* definitions for field: Receiver Counter in reg: Channel 22 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH22_COUNT_RCV_MASK WBGEN2_GEN_MASK(0, 16)
+#define WB_TRIG_IFACE_CH22_COUNT_RCV_SHIFT 0
+#define WB_TRIG_IFACE_CH22_COUNT_RCV_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
+#define WB_TRIG_IFACE_CH22_COUNT_RCV_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
+
+/* definitions for field: Transmitter Counter in reg: Channel 22 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH22_COUNT_TRANSM_MASK WBGEN2_GEN_MASK(16, 16)
+#define WB_TRIG_IFACE_CH22_COUNT_TRANSM_SHIFT 16
+#define WB_TRIG_IFACE_CH22_COUNT_TRANSM_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
+#define WB_TRIG_IFACE_CH22_COUNT_TRANSM_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
+
+/* definitions for register: Channel 23 Control */
+
+/* definitions for field: Trigger Direction in reg: Channel 23 Control */
+#define WB_TRIG_IFACE_CH23_CTL_DIR WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Trigger Direction Polarity in reg: Channel 23 Control */
+#define WB_TRIG_IFACE_CH23_CTL_DIR_POL WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for field: Receiver Pulse Counter Reset in reg: Channel 23 Control */
+#define WB_TRIG_IFACE_CH23_CTL_RCV_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+
+/* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 23 Control */
+#define WB_TRIG_IFACE_CH23_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
+
+/* definitions for register: Channel 23 Configuration Parameters */
+
+/* definitions for field: Receiver Pulse Length in reg: Channel 23 Configuration Parameters */
+#define WB_TRIG_IFACE_CH23_CFG_RCV_LEN_MASK WBGEN2_GEN_MASK(0, 8)
+#define WB_TRIG_IFACE_CH23_CFG_RCV_LEN_SHIFT 0
+#define WB_TRIG_IFACE_CH23_CFG_RCV_LEN_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
+#define WB_TRIG_IFACE_CH23_CFG_RCV_LEN_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
+
+/* definitions for field: Transmitter Pulse Length in reg: Channel 23 Configuration Parameters */
+#define WB_TRIG_IFACE_CH23_CFG_TRANSM_LEN_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_IFACE_CH23_CFG_TRANSM_LEN_SHIFT 8
+#define WB_TRIG_IFACE_CH23_CFG_TRANSM_LEN_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_IFACE_CH23_CFG_TRANSM_LEN_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for register: Channel 23 Transmitter/Receiver Pulses Counter */
+
+/* definitions for field: Receiver Counter in reg: Channel 23 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH23_COUNT_RCV_MASK WBGEN2_GEN_MASK(0, 16)
+#define WB_TRIG_IFACE_CH23_COUNT_RCV_SHIFT 0
+#define WB_TRIG_IFACE_CH23_COUNT_RCV_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
+#define WB_TRIG_IFACE_CH23_COUNT_RCV_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
+
+/* definitions for field: Transmitter Counter in reg: Channel 23 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_CH23_COUNT_TRANSM_MASK WBGEN2_GEN_MASK(16, 16)
+#define WB_TRIG_IFACE_CH23_COUNT_TRANSM_SHIFT 16
+#define WB_TRIG_IFACE_CH23_COUNT_TRANSM_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
+#define WB_TRIG_IFACE_CH23_COUNT_TRANSM_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
+/* [0x0]: REG Channel 0 Control */
+#define WB_TRIG_IFACE_REG_CH0_CTL 0x00000000
+/* [0x4]: REG Channel 0 Configuration Parameters */
+#define WB_TRIG_IFACE_REG_CH0_CFG 0x00000004
+/* [0x8]: REG Channel 0 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_REG_CH0_COUNT 0x00000008
+/* [0xc]: REG Channel 1 Control */
+#define WB_TRIG_IFACE_REG_CH1_CTL 0x0000000c
+/* [0x10]: REG Channel 1 Configuration Parameters */
+#define WB_TRIG_IFACE_REG_CH1_CFG 0x00000010
+/* [0x14]: REG Channel 1 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_REG_CH1_COUNT 0x00000014
+/* [0x18]: REG Channel 2 Control */
+#define WB_TRIG_IFACE_REG_CH2_CTL 0x00000018
+/* [0x1c]: REG Channel 2 Configuration Parameters */
+#define WB_TRIG_IFACE_REG_CH2_CFG 0x0000001c
+/* [0x20]: REG Channel 2 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_REG_CH2_COUNT 0x00000020
+/* [0x24]: REG Channel 3 Control */
+#define WB_TRIG_IFACE_REG_CH3_CTL 0x00000024
+/* [0x28]: REG Channel 3 Configuration Parameters */
+#define WB_TRIG_IFACE_REG_CH3_CFG 0x00000028
+/* [0x2c]: REG Channel 3 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_REG_CH3_COUNT 0x0000002c
+/* [0x30]: REG Channel 4 Control */
+#define WB_TRIG_IFACE_REG_CH4_CTL 0x00000030
+/* [0x34]: REG Channel 4 Configuration Parameters */
+#define WB_TRIG_IFACE_REG_CH4_CFG 0x00000034
+/* [0x38]: REG Channel 4 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_REG_CH4_COUNT 0x00000038
+/* [0x3c]: REG Channel 5 Control */
+#define WB_TRIG_IFACE_REG_CH5_CTL 0x0000003c
+/* [0x40]: REG Channel 5 Configuration Parameters */
+#define WB_TRIG_IFACE_REG_CH5_CFG 0x00000040
+/* [0x44]: REG Channel 5 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_REG_CH5_COUNT 0x00000044
+/* [0x48]: REG Channel 6 Control */
+#define WB_TRIG_IFACE_REG_CH6_CTL 0x00000048
+/* [0x4c]: REG Channel 6 Configuration Parameters */
+#define WB_TRIG_IFACE_REG_CH6_CFG 0x0000004c
+/* [0x50]: REG Channel 6 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_REG_CH6_COUNT 0x00000050
+/* [0x54]: REG Channel 7 Control */
+#define WB_TRIG_IFACE_REG_CH7_CTL 0x00000054
+/* [0x58]: REG Channel 7 Configuration Parameters */
+#define WB_TRIG_IFACE_REG_CH7_CFG 0x00000058
+/* [0x5c]: REG Channel 7 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_REG_CH7_COUNT 0x0000005c
+/* [0x60]: REG Channel 8 Control */
+#define WB_TRIG_IFACE_REG_CH8_CTL 0x00000060
+/* [0x64]: REG Channel 8 Configuration Parameters */
+#define WB_TRIG_IFACE_REG_CH8_CFG 0x00000064
+/* [0x68]: REG Channel 8 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_REG_CH8_COUNT 0x00000068
+/* [0x6c]: REG Channel 9 Control */
+#define WB_TRIG_IFACE_REG_CH9_CTL 0x0000006c
+/* [0x70]: REG Channel 9 Configuration Parameters */
+#define WB_TRIG_IFACE_REG_CH9_CFG 0x00000070
+/* [0x74]: REG Channel 9 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_REG_CH9_COUNT 0x00000074
+/* [0x78]: REG Channel 10 Control */
+#define WB_TRIG_IFACE_REG_CH10_CTL 0x00000078
+/* [0x7c]: REG Channel 10 Configuration Parameters */
+#define WB_TRIG_IFACE_REG_CH10_CFG 0x0000007c
+/* [0x80]: REG Channel 10 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_REG_CH10_COUNT 0x00000080
+/* [0x84]: REG Channel 11 Control */
+#define WB_TRIG_IFACE_REG_CH11_CTL 0x00000084
+/* [0x88]: REG Channel 11 Configuration Parameters */
+#define WB_TRIG_IFACE_REG_CH11_CFG 0x00000088
+/* [0x8c]: REG Channel 11 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_REG_CH11_COUNT 0x0000008c
+/* [0x90]: REG Channel 12 Control */
+#define WB_TRIG_IFACE_REG_CH12_CTL 0x00000090
+/* [0x94]: REG Channel 12 Configuration Parameters */
+#define WB_TRIG_IFACE_REG_CH12_CFG 0x00000094
+/* [0x98]: REG Channel 12 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_REG_CH12_COUNT 0x00000098
+/* [0x9c]: REG Channel 13 Control */
+#define WB_TRIG_IFACE_REG_CH13_CTL 0x0000009c
+/* [0xa0]: REG Channel 13 Configuration Parameters */
+#define WB_TRIG_IFACE_REG_CH13_CFG 0x000000a0
+/* [0xa4]: REG Channel 13 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_REG_CH13_COUNT 0x000000a4
+/* [0xa8]: REG Channel 14 Control */
+#define WB_TRIG_IFACE_REG_CH14_CTL 0x000000a8
+/* [0xac]: REG Channel 14 Configuration Parameters */
+#define WB_TRIG_IFACE_REG_CH14_CFG 0x000000ac
+/* [0xb0]: REG Channel 14 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_REG_CH14_COUNT 0x000000b0
+/* [0xb4]: REG Channel 15 Control */
+#define WB_TRIG_IFACE_REG_CH15_CTL 0x000000b4
+/* [0xb8]: REG Channel 15 Configuration Parameters */
+#define WB_TRIG_IFACE_REG_CH15_CFG 0x000000b8
+/* [0xbc]: REG Channel 15 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_REG_CH15_COUNT 0x000000bc
+/* [0xc0]: REG Channel 16 Control */
+#define WB_TRIG_IFACE_REG_CH16_CTL 0x000000c0
+/* [0xc4]: REG Channel 16 Configuration Parameters */
+#define WB_TRIG_IFACE_REG_CH16_CFG 0x000000c4
+/* [0xc8]: REG Channel 16 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_REG_CH16_COUNT 0x000000c8
+/* [0xcc]: REG Channel 17 Control */
+#define WB_TRIG_IFACE_REG_CH17_CTL 0x000000cc
+/* [0xd0]: REG Channel 17 Configuration Parameters */
+#define WB_TRIG_IFACE_REG_CH17_CFG 0x000000d0
+/* [0xd4]: REG Channel 17 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_REG_CH17_COUNT 0x000000d4
+/* [0xd8]: REG Channel 18 Control */
+#define WB_TRIG_IFACE_REG_CH18_CTL 0x000000d8
+/* [0xdc]: REG Channel 18 Configuration Parameters */
+#define WB_TRIG_IFACE_REG_CH18_CFG 0x000000dc
+/* [0xe0]: REG Channel 18 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_REG_CH18_COUNT 0x000000e0
+/* [0xe4]: REG Channel 19 Control */
+#define WB_TRIG_IFACE_REG_CH19_CTL 0x000000e4
+/* [0xe8]: REG Channel 19 Configuration Parameters */
+#define WB_TRIG_IFACE_REG_CH19_CFG 0x000000e8
+/* [0xec]: REG Channel 19 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_REG_CH19_COUNT 0x000000ec
+/* [0xf0]: REG Channel 20 Control */
+#define WB_TRIG_IFACE_REG_CH20_CTL 0x000000f0
+/* [0xf4]: REG Channel 20 Configuration Parameters */
+#define WB_TRIG_IFACE_REG_CH20_CFG 0x000000f4
+/* [0xf8]: REG Channel 20 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_REG_CH20_COUNT 0x000000f8
+/* [0xfc]: REG Channel 21 Control */
+#define WB_TRIG_IFACE_REG_CH21_CTL 0x000000fc
+/* [0x100]: REG Channel 21 Configuration Parameters */
+#define WB_TRIG_IFACE_REG_CH21_CFG 0x00000100
+/* [0x104]: REG Channel 21 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_REG_CH21_COUNT 0x00000104
+/* [0x108]: REG Channel 22 Control */
+#define WB_TRIG_IFACE_REG_CH22_CTL 0x00000108
+/* [0x10c]: REG Channel 22 Configuration Parameters */
+#define WB_TRIG_IFACE_REG_CH22_CFG 0x0000010c
+/* [0x110]: REG Channel 22 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_REG_CH22_COUNT 0x00000110
+/* [0x114]: REG Channel 23 Control */
+#define WB_TRIG_IFACE_REG_CH23_CTL 0x00000114
+/* [0x118]: REG Channel 23 Configuration Parameters */
+#define WB_TRIG_IFACE_REG_CH23_CFG 0x00000118
+/* [0x11c]: REG Channel 23 Transmitter/Receiver Pulses Counter */
+#define WB_TRIG_IFACE_REG_CH23_COUNT 0x0000011c
+#endif
diff --git a/include/hw/wb_trigger_mux_regs.h b/include/hw/wb_trigger_mux_regs.h
new file mode 100644
index 0000000000000000000000000000000000000000..53bd30d36438d5caeece9aeebc0a2244cc4f6224
--- /dev/null
+++ b/include/hw/wb_trigger_mux_regs.h
@@ -0,0 +1,657 @@
+/*
+ Register definitions for slave core: Control and status register for the MLVDS trigger
+
+ * File : wb_trigger_mux_regs.h
+ * Author : auto-generated by wbgen2 from wb_trigger_mux.wb
+ * Created : Wed May 11 18:21:31 2016
+ * Standard : ANSI C
+
+ THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_trigger_mux.wb
+ DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+
+*/
+
+#ifndef __WBGEN2_REGDEFS_WB_TRIGGER_MUX_WB
+#define __WBGEN2_REGDEFS_WB_TRIGGER_MUX_WB
+
+#include <inttypes.h>
+
+#if defined( __GNUC__)
+#define PACKED __attribute__ ((packed))
+#else
+#error "Unsupported compiler?"
+#endif
+
+#ifndef __WBGEN2_MACROS_DEFINED__
+#define __WBGEN2_MACROS_DEFINED__
+#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
+#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
+#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
+#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
+#endif
+
+
+/* definitions for register: Channel 0 Control */
+
+/* definitions for field: Receiver Source in reg: Channel 0 Control */
+#define WB_TRIG_MUX_CH0_CTL_RCV_SRC WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Select Receiver Input in reg: Channel 0 Control */
+#define WB_TRIG_MUX_CH0_CTL_RCV_IN_SEL_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_MUX_CH0_CTL_RCV_IN_SEL_SHIFT 8
+#define WB_TRIG_MUX_CH0_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_MUX_CH0_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for field: Transmitter Source in reg: Channel 0 Control */
+#define WB_TRIG_MUX_CH0_CTL_TRANSM_SRC WBGEN2_GEN_MASK(16, 1)
+
+/* definitions for field: Select Transmitter Output in reg: Channel 0 Control */
+#define WB_TRIG_MUX_CH0_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
+#define WB_TRIG_MUX_CH0_CTL_TRANSM_OUT_SEL_SHIFT 24
+#define WB_TRIG_MUX_CH0_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
+#define WB_TRIG_MUX_CH0_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)
+
+/* definitions for register: Channel 0 Dummy Register */
+
+/* definitions for register: Channel 1 Control */
+
+/* definitions for field: Receiver Source in reg: Channel 1 Control */
+#define WB_TRIG_MUX_CH1_CTL_RCV_SRC WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Select Receiver Input in reg: Channel 1 Control */
+#define WB_TRIG_MUX_CH1_CTL_RCV_IN_SEL_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_MUX_CH1_CTL_RCV_IN_SEL_SHIFT 8
+#define WB_TRIG_MUX_CH1_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_MUX_CH1_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for field: Transmitter Source in reg: Channel 1 Control */
+#define WB_TRIG_MUX_CH1_CTL_TRANSM_SRC WBGEN2_GEN_MASK(16, 1)
+
+/* definitions for field: Select Transmitter Output in reg: Channel 1 Control */
+#define WB_TRIG_MUX_CH1_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
+#define WB_TRIG_MUX_CH1_CTL_TRANSM_OUT_SEL_SHIFT 24
+#define WB_TRIG_MUX_CH1_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
+#define WB_TRIG_MUX_CH1_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)
+
+/* definitions for register: Channel 1 Dummy Register */
+
+/* definitions for register: Channel 2 Control */
+
+/* definitions for field: Receiver Source in reg: Channel 2 Control */
+#define WB_TRIG_MUX_CH2_CTL_RCV_SRC WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Select Receiver Input in reg: Channel 2 Control */
+#define WB_TRIG_MUX_CH2_CTL_RCV_IN_SEL_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_MUX_CH2_CTL_RCV_IN_SEL_SHIFT 8
+#define WB_TRIG_MUX_CH2_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_MUX_CH2_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for field: Transmitter Source in reg: Channel 2 Control */
+#define WB_TRIG_MUX_CH2_CTL_TRANSM_SRC WBGEN2_GEN_MASK(16, 1)
+
+/* definitions for field: Select Transmitter Output in reg: Channel 2 Control */
+#define WB_TRIG_MUX_CH2_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
+#define WB_TRIG_MUX_CH2_CTL_TRANSM_OUT_SEL_SHIFT 24
+#define WB_TRIG_MUX_CH2_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
+#define WB_TRIG_MUX_CH2_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)
+
+/* definitions for register: Channel 2 Dummy Register */
+
+/* definitions for register: Channel 3 Control */
+
+/* definitions for field: Receiver Source in reg: Channel 3 Control */
+#define WB_TRIG_MUX_CH3_CTL_RCV_SRC WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Select Receiver Input in reg: Channel 3 Control */
+#define WB_TRIG_MUX_CH3_CTL_RCV_IN_SEL_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_MUX_CH3_CTL_RCV_IN_SEL_SHIFT 8
+#define WB_TRIG_MUX_CH3_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_MUX_CH3_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for field: Transmitter Source in reg: Channel 3 Control */
+#define WB_TRIG_MUX_CH3_CTL_TRANSM_SRC WBGEN2_GEN_MASK(16, 1)
+
+/* definitions for field: Select Transmitter Output in reg: Channel 3 Control */
+#define WB_TRIG_MUX_CH3_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
+#define WB_TRIG_MUX_CH3_CTL_TRANSM_OUT_SEL_SHIFT 24
+#define WB_TRIG_MUX_CH3_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
+#define WB_TRIG_MUX_CH3_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)
+
+/* definitions for register: Channel 3 Dummy Register */
+
+/* definitions for register: Channel 4 Control */
+
+/* definitions for field: Receiver Source in reg: Channel 4 Control */
+#define WB_TRIG_MUX_CH4_CTL_RCV_SRC WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Select Receiver Input in reg: Channel 4 Control */
+#define WB_TRIG_MUX_CH4_CTL_RCV_IN_SEL_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_MUX_CH4_CTL_RCV_IN_SEL_SHIFT 8
+#define WB_TRIG_MUX_CH4_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_MUX_CH4_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for field: Transmitter Source in reg: Channel 4 Control */
+#define WB_TRIG_MUX_CH4_CTL_TRANSM_SRC WBGEN2_GEN_MASK(16, 1)
+
+/* definitions for field: Select Transmitter Output in reg: Channel 4 Control */
+#define WB_TRIG_MUX_CH4_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
+#define WB_TRIG_MUX_CH4_CTL_TRANSM_OUT_SEL_SHIFT 24
+#define WB_TRIG_MUX_CH4_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
+#define WB_TRIG_MUX_CH4_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)
+
+/* definitions for register: Channel 4 Dummy Register */
+
+/* definitions for register: Channel 5 Control */
+
+/* definitions for field: Receiver Source in reg: Channel 5 Control */
+#define WB_TRIG_MUX_CH5_CTL_RCV_SRC WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Select Receiver Input in reg: Channel 5 Control */
+#define WB_TRIG_MUX_CH5_CTL_RCV_IN_SEL_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_MUX_CH5_CTL_RCV_IN_SEL_SHIFT 8
+#define WB_TRIG_MUX_CH5_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_MUX_CH5_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for field: Transmitter Source in reg: Channel 5 Control */
+#define WB_TRIG_MUX_CH5_CTL_TRANSM_SRC WBGEN2_GEN_MASK(16, 1)
+
+/* definitions for field: Select Transmitter Output in reg: Channel 5 Control */
+#define WB_TRIG_MUX_CH5_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
+#define WB_TRIG_MUX_CH5_CTL_TRANSM_OUT_SEL_SHIFT 24
+#define WB_TRIG_MUX_CH5_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
+#define WB_TRIG_MUX_CH5_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)
+
+/* definitions for register: Channel 5 Dummy Register */
+
+/* definitions for register: Channel 6 Control */
+
+/* definitions for field: Receiver Source in reg: Channel 6 Control */
+#define WB_TRIG_MUX_CH6_CTL_RCV_SRC WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Select Receiver Input in reg: Channel 6 Control */
+#define WB_TRIG_MUX_CH6_CTL_RCV_IN_SEL_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_MUX_CH6_CTL_RCV_IN_SEL_SHIFT 8
+#define WB_TRIG_MUX_CH6_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_MUX_CH6_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for field: Transmitter Source in reg: Channel 6 Control */
+#define WB_TRIG_MUX_CH6_CTL_TRANSM_SRC WBGEN2_GEN_MASK(16, 1)
+
+/* definitions for field: Select Transmitter Output in reg: Channel 6 Control */
+#define WB_TRIG_MUX_CH6_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
+#define WB_TRIG_MUX_CH6_CTL_TRANSM_OUT_SEL_SHIFT 24
+#define WB_TRIG_MUX_CH6_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
+#define WB_TRIG_MUX_CH6_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)
+
+/* definitions for register: Channel 6 Dummy Register */
+
+/* definitions for register: Channel 7 Control */
+
+/* definitions for field: Receiver Source in reg: Channel 7 Control */
+#define WB_TRIG_MUX_CH7_CTL_RCV_SRC WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Select Receiver Input in reg: Channel 7 Control */
+#define WB_TRIG_MUX_CH7_CTL_RCV_IN_SEL_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_MUX_CH7_CTL_RCV_IN_SEL_SHIFT 8
+#define WB_TRIG_MUX_CH7_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_MUX_CH7_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for field: Transmitter Source in reg: Channel 7 Control */
+#define WB_TRIG_MUX_CH7_CTL_TRANSM_SRC WBGEN2_GEN_MASK(16, 1)
+
+/* definitions for field: Select Transmitter Output in reg: Channel 7 Control */
+#define WB_TRIG_MUX_CH7_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
+#define WB_TRIG_MUX_CH7_CTL_TRANSM_OUT_SEL_SHIFT 24
+#define WB_TRIG_MUX_CH7_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
+#define WB_TRIG_MUX_CH7_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)
+
+/* definitions for register: Channel 7 Dummy Register */
+
+/* definitions for register: Channel 8 Control */
+
+/* definitions for field: Receiver Source in reg: Channel 8 Control */
+#define WB_TRIG_MUX_CH8_CTL_RCV_SRC WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Select Receiver Input in reg: Channel 8 Control */
+#define WB_TRIG_MUX_CH8_CTL_RCV_IN_SEL_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_MUX_CH8_CTL_RCV_IN_SEL_SHIFT 8
+#define WB_TRIG_MUX_CH8_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_MUX_CH8_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for field: Transmitter Source in reg: Channel 8 Control */
+#define WB_TRIG_MUX_CH8_CTL_TRANSM_SRC WBGEN2_GEN_MASK(16, 1)
+
+/* definitions for field: Select Transmitter Output in reg: Channel 8 Control */
+#define WB_TRIG_MUX_CH8_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
+#define WB_TRIG_MUX_CH8_CTL_TRANSM_OUT_SEL_SHIFT 24
+#define WB_TRIG_MUX_CH8_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
+#define WB_TRIG_MUX_CH8_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)
+
+/* definitions for register: Channel 8 Dummy Register */
+
+/* definitions for register: Channel 9 Control */
+
+/* definitions for field: Receiver Source in reg: Channel 9 Control */
+#define WB_TRIG_MUX_CH9_CTL_RCV_SRC WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Select Receiver Input in reg: Channel 9 Control */
+#define WB_TRIG_MUX_CH9_CTL_RCV_IN_SEL_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_MUX_CH9_CTL_RCV_IN_SEL_SHIFT 8
+#define WB_TRIG_MUX_CH9_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_MUX_CH9_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for field: Transmitter Source in reg: Channel 9 Control */
+#define WB_TRIG_MUX_CH9_CTL_TRANSM_SRC WBGEN2_GEN_MASK(16, 1)
+
+/* definitions for field: Select Transmitter Output in reg: Channel 9 Control */
+#define WB_TRIG_MUX_CH9_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
+#define WB_TRIG_MUX_CH9_CTL_TRANSM_OUT_SEL_SHIFT 24
+#define WB_TRIG_MUX_CH9_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
+#define WB_TRIG_MUX_CH9_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)
+
+/* definitions for register: Channel 9 Dummy Register */
+
+/* definitions for register: Channel 10 Control */
+
+/* definitions for field: Receiver Source in reg: Channel 10 Control */
+#define WB_TRIG_MUX_CH10_CTL_RCV_SRC WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Select Receiver Input in reg: Channel 10 Control */
+#define WB_TRIG_MUX_CH10_CTL_RCV_IN_SEL_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_MUX_CH10_CTL_RCV_IN_SEL_SHIFT 8
+#define WB_TRIG_MUX_CH10_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_MUX_CH10_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for field: Transmitter Source in reg: Channel 10 Control */
+#define WB_TRIG_MUX_CH10_CTL_TRANSM_SRC WBGEN2_GEN_MASK(16, 1)
+
+/* definitions for field: Select Transmitter Output in reg: Channel 10 Control */
+#define WB_TRIG_MUX_CH10_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
+#define WB_TRIG_MUX_CH10_CTL_TRANSM_OUT_SEL_SHIFT 24
+#define WB_TRIG_MUX_CH10_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
+#define WB_TRIG_MUX_CH10_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)
+
+/* definitions for register: Channel 10 Dummy Register */
+
+/* definitions for register: Channel 11 Control */
+
+/* definitions for field: Receiver Source in reg: Channel 11 Control */
+#define WB_TRIG_MUX_CH11_CTL_RCV_SRC WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Select Receiver Input in reg: Channel 11 Control */
+#define WB_TRIG_MUX_CH11_CTL_RCV_IN_SEL_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_MUX_CH11_CTL_RCV_IN_SEL_SHIFT 8
+#define WB_TRIG_MUX_CH11_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_MUX_CH11_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for field: Transmitter Source in reg: Channel 11 Control */
+#define WB_TRIG_MUX_CH11_CTL_TRANSM_SRC WBGEN2_GEN_MASK(16, 1)
+
+/* definitions for field: Select Transmitter Output in reg: Channel 11 Control */
+#define WB_TRIG_MUX_CH11_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
+#define WB_TRIG_MUX_CH11_CTL_TRANSM_OUT_SEL_SHIFT 24
+#define WB_TRIG_MUX_CH11_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
+#define WB_TRIG_MUX_CH11_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)
+
+/* definitions for register: Channel 11 Dummy Register */
+
+/* definitions for register: Channel 12 Control */
+
+/* definitions for field: Receiver Source in reg: Channel 12 Control */
+#define WB_TRIG_MUX_CH12_CTL_RCV_SRC WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Select Receiver Input in reg: Channel 12 Control */
+#define WB_TRIG_MUX_CH12_CTL_RCV_IN_SEL_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_MUX_CH12_CTL_RCV_IN_SEL_SHIFT 8
+#define WB_TRIG_MUX_CH12_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_MUX_CH12_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for field: Transmitter Source in reg: Channel 12 Control */
+#define WB_TRIG_MUX_CH12_CTL_TRANSM_SRC WBGEN2_GEN_MASK(16, 1)
+
+/* definitions for field: Select Transmitter Output in reg: Channel 12 Control */
+#define WB_TRIG_MUX_CH12_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
+#define WB_TRIG_MUX_CH12_CTL_TRANSM_OUT_SEL_SHIFT 24
+#define WB_TRIG_MUX_CH12_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
+#define WB_TRIG_MUX_CH12_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)
+
+/* definitions for register: Channel 12 Dummy Register */
+
+/* definitions for register: Channel 13 Control */
+
+/* definitions for field: Receiver Source in reg: Channel 13 Control */
+#define WB_TRIG_MUX_CH13_CTL_RCV_SRC WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Select Receiver Input in reg: Channel 13 Control */
+#define WB_TRIG_MUX_CH13_CTL_RCV_IN_SEL_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_MUX_CH13_CTL_RCV_IN_SEL_SHIFT 8
+#define WB_TRIG_MUX_CH13_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_MUX_CH13_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for field: Transmitter Source in reg: Channel 13 Control */
+#define WB_TRIG_MUX_CH13_CTL_TRANSM_SRC WBGEN2_GEN_MASK(16, 1)
+
+/* definitions for field: Select Transmitter Output in reg: Channel 13 Control */
+#define WB_TRIG_MUX_CH13_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
+#define WB_TRIG_MUX_CH13_CTL_TRANSM_OUT_SEL_SHIFT 24
+#define WB_TRIG_MUX_CH13_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
+#define WB_TRIG_MUX_CH13_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)
+
+/* definitions for register: Channel 13 Dummy Register */
+
+/* definitions for register: Channel 14 Control */
+
+/* definitions for field: Receiver Source in reg: Channel 14 Control */
+#define WB_TRIG_MUX_CH14_CTL_RCV_SRC WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Select Receiver Input in reg: Channel 14 Control */
+#define WB_TRIG_MUX_CH14_CTL_RCV_IN_SEL_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_MUX_CH14_CTL_RCV_IN_SEL_SHIFT 8
+#define WB_TRIG_MUX_CH14_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_MUX_CH14_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for field: Transmitter Source in reg: Channel 14 Control */
+#define WB_TRIG_MUX_CH14_CTL_TRANSM_SRC WBGEN2_GEN_MASK(16, 1)
+
+/* definitions for field: Select Transmitter Output in reg: Channel 14 Control */
+#define WB_TRIG_MUX_CH14_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
+#define WB_TRIG_MUX_CH14_CTL_TRANSM_OUT_SEL_SHIFT 24
+#define WB_TRIG_MUX_CH14_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
+#define WB_TRIG_MUX_CH14_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)
+
+/* definitions for register: Channel 14 Dummy Register */
+
+/* definitions for register: Channel 15 Control */
+
+/* definitions for field: Receiver Source in reg: Channel 15 Control */
+#define WB_TRIG_MUX_CH15_CTL_RCV_SRC WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Select Receiver Input in reg: Channel 15 Control */
+#define WB_TRIG_MUX_CH15_CTL_RCV_IN_SEL_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_MUX_CH15_CTL_RCV_IN_SEL_SHIFT 8
+#define WB_TRIG_MUX_CH15_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_MUX_CH15_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for field: Transmitter Source in reg: Channel 15 Control */
+#define WB_TRIG_MUX_CH15_CTL_TRANSM_SRC WBGEN2_GEN_MASK(16, 1)
+
+/* definitions for field: Select Transmitter Output in reg: Channel 15 Control */
+#define WB_TRIG_MUX_CH15_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
+#define WB_TRIG_MUX_CH15_CTL_TRANSM_OUT_SEL_SHIFT 24
+#define WB_TRIG_MUX_CH15_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
+#define WB_TRIG_MUX_CH15_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)
+
+/* definitions for register: Channel 15 Dummy Register */
+
+/* definitions for register: Channel 16 Control */
+
+/* definitions for field: Receiver Source in reg: Channel 16 Control */
+#define WB_TRIG_MUX_CH16_CTL_RCV_SRC WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Select Receiver Input in reg: Channel 16 Control */
+#define WB_TRIG_MUX_CH16_CTL_RCV_IN_SEL_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_MUX_CH16_CTL_RCV_IN_SEL_SHIFT 8
+#define WB_TRIG_MUX_CH16_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_MUX_CH16_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for field: Transmitter Source in reg: Channel 16 Control */
+#define WB_TRIG_MUX_CH16_CTL_TRANSM_SRC WBGEN2_GEN_MASK(16, 1)
+
+/* definitions for field: Select Transmitter Output in reg: Channel 16 Control */
+#define WB_TRIG_MUX_CH16_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
+#define WB_TRIG_MUX_CH16_CTL_TRANSM_OUT_SEL_SHIFT 24
+#define WB_TRIG_MUX_CH16_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
+#define WB_TRIG_MUX_CH16_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)
+
+/* definitions for register: Channel 16 Dummy Register */
+
+/* definitions for register: Channel 17 Control */
+
+/* definitions for field: Receiver Source in reg: Channel 17 Control */
+#define WB_TRIG_MUX_CH17_CTL_RCV_SRC WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Select Receiver Input in reg: Channel 17 Control */
+#define WB_TRIG_MUX_CH17_CTL_RCV_IN_SEL_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_MUX_CH17_CTL_RCV_IN_SEL_SHIFT 8
+#define WB_TRIG_MUX_CH17_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_MUX_CH17_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for field: Transmitter Source in reg: Channel 17 Control */
+#define WB_TRIG_MUX_CH17_CTL_TRANSM_SRC WBGEN2_GEN_MASK(16, 1)
+
+/* definitions for field: Select Transmitter Output in reg: Channel 17 Control */
+#define WB_TRIG_MUX_CH17_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
+#define WB_TRIG_MUX_CH17_CTL_TRANSM_OUT_SEL_SHIFT 24
+#define WB_TRIG_MUX_CH17_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
+#define WB_TRIG_MUX_CH17_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)
+
+/* definitions for register: Channel 17 Dummy Register */
+
+/* definitions for register: Channel 18 Control */
+
+/* definitions for field: Receiver Source in reg: Channel 18 Control */
+#define WB_TRIG_MUX_CH18_CTL_RCV_SRC WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Select Receiver Input in reg: Channel 18 Control */
+#define WB_TRIG_MUX_CH18_CTL_RCV_IN_SEL_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_MUX_CH18_CTL_RCV_IN_SEL_SHIFT 8
+#define WB_TRIG_MUX_CH18_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_MUX_CH18_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for field: Transmitter Source in reg: Channel 18 Control */
+#define WB_TRIG_MUX_CH18_CTL_TRANSM_SRC WBGEN2_GEN_MASK(16, 1)
+
+/* definitions for field: Select Transmitter Output in reg: Channel 18 Control */
+#define WB_TRIG_MUX_CH18_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
+#define WB_TRIG_MUX_CH18_CTL_TRANSM_OUT_SEL_SHIFT 24
+#define WB_TRIG_MUX_CH18_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
+#define WB_TRIG_MUX_CH18_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)
+
+/* definitions for register: Channel 18 Dummy Register */
+
+/* definitions for register: Channel 19 Control */
+
+/* definitions for field: Receiver Source in reg: Channel 19 Control */
+#define WB_TRIG_MUX_CH19_CTL_RCV_SRC WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Select Receiver Input in reg: Channel 19 Control */
+#define WB_TRIG_MUX_CH19_CTL_RCV_IN_SEL_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_MUX_CH19_CTL_RCV_IN_SEL_SHIFT 8
+#define WB_TRIG_MUX_CH19_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_MUX_CH19_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for field: Transmitter Source in reg: Channel 19 Control */
+#define WB_TRIG_MUX_CH19_CTL_TRANSM_SRC WBGEN2_GEN_MASK(16, 1)
+
+/* definitions for field: Select Transmitter Output in reg: Channel 19 Control */
+#define WB_TRIG_MUX_CH19_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
+#define WB_TRIG_MUX_CH19_CTL_TRANSM_OUT_SEL_SHIFT 24
+#define WB_TRIG_MUX_CH19_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
+#define WB_TRIG_MUX_CH19_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)
+
+/* definitions for register: Channel 19 Dummy Register */
+
+/* definitions for register: Channel 20 Control */
+
+/* definitions for field: Receiver Source in reg: Channel 20 Control */
+#define WB_TRIG_MUX_CH20_CTL_RCV_SRC WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Select Receiver Input in reg: Channel 20 Control */
+#define WB_TRIG_MUX_CH20_CTL_RCV_IN_SEL_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_MUX_CH20_CTL_RCV_IN_SEL_SHIFT 8
+#define WB_TRIG_MUX_CH20_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_MUX_CH20_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for field: Transmitter Source in reg: Channel 20 Control */
+#define WB_TRIG_MUX_CH20_CTL_TRANSM_SRC WBGEN2_GEN_MASK(16, 1)
+
+/* definitions for field: Select Transmitter Output in reg: Channel 20 Control */
+#define WB_TRIG_MUX_CH20_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
+#define WB_TRIG_MUX_CH20_CTL_TRANSM_OUT_SEL_SHIFT 24
+#define WB_TRIG_MUX_CH20_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
+#define WB_TRIG_MUX_CH20_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)
+
+/* definitions for register: Channel 20 Dummy Register */
+
+/* definitions for register: Channel 21 Control */
+
+/* definitions for field: Receiver Source in reg: Channel 21 Control */
+#define WB_TRIG_MUX_CH21_CTL_RCV_SRC WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Select Receiver Input in reg: Channel 21 Control */
+#define WB_TRIG_MUX_CH21_CTL_RCV_IN_SEL_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_MUX_CH21_CTL_RCV_IN_SEL_SHIFT 8
+#define WB_TRIG_MUX_CH21_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_MUX_CH21_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for field: Transmitter Source in reg: Channel 21 Control */
+#define WB_TRIG_MUX_CH21_CTL_TRANSM_SRC WBGEN2_GEN_MASK(16, 1)
+
+/* definitions for field: Select Transmitter Output in reg: Channel 21 Control */
+#define WB_TRIG_MUX_CH21_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
+#define WB_TRIG_MUX_CH21_CTL_TRANSM_OUT_SEL_SHIFT 24
+#define WB_TRIG_MUX_CH21_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
+#define WB_TRIG_MUX_CH21_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)
+
+/* definitions for register: Channel 21 Dummy Register */
+
+/* definitions for register: Channel 22 Control */
+
+/* definitions for field: Receiver Source in reg: Channel 22 Control */
+#define WB_TRIG_MUX_CH22_CTL_RCV_SRC WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Select Receiver Input in reg: Channel 22 Control */
+#define WB_TRIG_MUX_CH22_CTL_RCV_IN_SEL_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_MUX_CH22_CTL_RCV_IN_SEL_SHIFT 8
+#define WB_TRIG_MUX_CH22_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_MUX_CH22_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for field: Transmitter Source in reg: Channel 22 Control */
+#define WB_TRIG_MUX_CH22_CTL_TRANSM_SRC WBGEN2_GEN_MASK(16, 1)
+
+/* definitions for field: Select Transmitter Output in reg: Channel 22 Control */
+#define WB_TRIG_MUX_CH22_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
+#define WB_TRIG_MUX_CH22_CTL_TRANSM_OUT_SEL_SHIFT 24
+#define WB_TRIG_MUX_CH22_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
+#define WB_TRIG_MUX_CH22_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)
+
+/* definitions for register: Channel 22 Dummy Register */
+
+/* definitions for register: Channel 23 Control */
+
+/* definitions for field: Receiver Source in reg: Channel 23 Control */
+#define WB_TRIG_MUX_CH23_CTL_RCV_SRC WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Select Receiver Input in reg: Channel 23 Control */
+#define WB_TRIG_MUX_CH23_CTL_RCV_IN_SEL_MASK WBGEN2_GEN_MASK(8, 8)
+#define WB_TRIG_MUX_CH23_CTL_RCV_IN_SEL_SHIFT 8
+#define WB_TRIG_MUX_CH23_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
+#define WB_TRIG_MUX_CH23_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
+
+/* definitions for field: Transmitter Source in reg: Channel 23 Control */
+#define WB_TRIG_MUX_CH23_CTL_TRANSM_SRC WBGEN2_GEN_MASK(16, 1)
+
+/* definitions for field: Select Transmitter Output in reg: Channel 23 Control */
+#define WB_TRIG_MUX_CH23_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
+#define WB_TRIG_MUX_CH23_CTL_TRANSM_OUT_SEL_SHIFT 24
+#define WB_TRIG_MUX_CH23_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
+#define WB_TRIG_MUX_CH23_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)
+
+/* definitions for register: Channel 23 Dummy Register */
+/* [0x0]: REG Channel 0 Control */
+#define WB_TRIG_MUX_REG_CH0_CTL 0x00000000
+/* [0x4]: REG Channel 0 Dummy Register */
+#define WB_TRIG_MUX_REG_CH0_DUMMY 0x00000004
+/* [0x8]: REG Channel 1 Control */
+#define WB_TRIG_MUX_REG_CH1_CTL 0x00000008
+/* [0xc]: REG Channel 1 Dummy Register */
+#define WB_TRIG_MUX_REG_CH1_DUMMY 0x0000000c
+/* [0x10]: REG Channel 2 Control */
+#define WB_TRIG_MUX_REG_CH2_CTL 0x00000010
+/* [0x14]: REG Channel 2 Dummy Register */
+#define WB_TRIG_MUX_REG_CH2_DUMMY 0x00000014
+/* [0x18]: REG Channel 3 Control */
+#define WB_TRIG_MUX_REG_CH3_CTL 0x00000018
+/* [0x1c]: REG Channel 3 Dummy Register */
+#define WB_TRIG_MUX_REG_CH3_DUMMY 0x0000001c
+/* [0x20]: REG Channel 4 Control */
+#define WB_TRIG_MUX_REG_CH4_CTL 0x00000020
+/* [0x24]: REG Channel 4 Dummy Register */
+#define WB_TRIG_MUX_REG_CH4_DUMMY 0x00000024
+/* [0x28]: REG Channel 5 Control */
+#define WB_TRIG_MUX_REG_CH5_CTL 0x00000028
+/* [0x2c]: REG Channel 5 Dummy Register */
+#define WB_TRIG_MUX_REG_CH5_DUMMY 0x0000002c
+/* [0x30]: REG Channel 6 Control */
+#define WB_TRIG_MUX_REG_CH6_CTL 0x00000030
+/* [0x34]: REG Channel 6 Dummy Register */
+#define WB_TRIG_MUX_REG_CH6_DUMMY 0x00000034
+/* [0x38]: REG Channel 7 Control */
+#define WB_TRIG_MUX_REG_CH7_CTL 0x00000038
+/* [0x3c]: REG Channel 7 Dummy Register */
+#define WB_TRIG_MUX_REG_CH7_DUMMY 0x0000003c
+/* [0x40]: REG Channel 8 Control */
+#define WB_TRIG_MUX_REG_CH8_CTL 0x00000040
+/* [0x44]: REG Channel 8 Dummy Register */
+#define WB_TRIG_MUX_REG_CH8_DUMMY 0x00000044
+/* [0x48]: REG Channel 9 Control */
+#define WB_TRIG_MUX_REG_CH9_CTL 0x00000048
+/* [0x4c]: REG Channel 9 Dummy Register */
+#define WB_TRIG_MUX_REG_CH9_DUMMY 0x0000004c
+/* [0x50]: REG Channel 10 Control */
+#define WB_TRIG_MUX_REG_CH10_CTL 0x00000050
+/* [0x54]: REG Channel 10 Dummy Register */
+#define WB_TRIG_MUX_REG_CH10_DUMMY 0x00000054
+/* [0x58]: REG Channel 11 Control */
+#define WB_TRIG_MUX_REG_CH11_CTL 0x00000058
+/* [0x5c]: REG Channel 11 Dummy Register */
+#define WB_TRIG_MUX_REG_CH11_DUMMY 0x0000005c
+/* [0x60]: REG Channel 12 Control */
+#define WB_TRIG_MUX_REG_CH12_CTL 0x00000060
+/* [0x64]: REG Channel 12 Dummy Register */
+#define WB_TRIG_MUX_REG_CH12_DUMMY 0x00000064
+/* [0x68]: REG Channel 13 Control */
+#define WB_TRIG_MUX_REG_CH13_CTL 0x00000068
+/* [0x6c]: REG Channel 13 Dummy Register */
+#define WB_TRIG_MUX_REG_CH13_DUMMY 0x0000006c
+/* [0x70]: REG Channel 14 Control */
+#define WB_TRIG_MUX_REG_CH14_CTL 0x00000070
+/* [0x74]: REG Channel 14 Dummy Register */
+#define WB_TRIG_MUX_REG_CH14_DUMMY 0x00000074
+/* [0x78]: REG Channel 15 Control */
+#define WB_TRIG_MUX_REG_CH15_CTL 0x00000078
+/* [0x7c]: REG Channel 15 Dummy Register */
+#define WB_TRIG_MUX_REG_CH15_DUMMY 0x0000007c
+/* [0x80]: REG Channel 16 Control */
+#define WB_TRIG_MUX_REG_CH16_CTL 0x00000080
+/* [0x84]: REG Channel 16 Dummy Register */
+#define WB_TRIG_MUX_REG_CH16_DUMMY 0x00000084
+/* [0x88]: REG Channel 17 Control */
+#define WB_TRIG_MUX_REG_CH17_CTL 0x00000088
+/* [0x8c]: REG Channel 17 Dummy Register */
+#define WB_TRIG_MUX_REG_CH17_DUMMY 0x0000008c
+/* [0x90]: REG Channel 18 Control */
+#define WB_TRIG_MUX_REG_CH18_CTL 0x00000090
+/* [0x94]: REG Channel 18 Dummy Register */
+#define WB_TRIG_MUX_REG_CH18_DUMMY 0x00000094
+/* [0x98]: REG Channel 19 Control */
+#define WB_TRIG_MUX_REG_CH19_CTL 0x00000098
+/* [0x9c]: REG Channel 19 Dummy Register */
+#define WB_TRIG_MUX_REG_CH19_DUMMY 0x0000009c
+/* [0xa0]: REG Channel 20 Control */
+#define WB_TRIG_MUX_REG_CH20_CTL 0x000000a0
+/* [0xa4]: REG Channel 20 Dummy Register */
+#define WB_TRIG_MUX_REG_CH20_DUMMY 0x000000a4
+/* [0xa8]: REG Channel 21 Control */
+#define WB_TRIG_MUX_REG_CH21_CTL 0x000000a8
+/* [0xac]: REG Channel 21 Dummy Register */
+#define WB_TRIG_MUX_REG_CH21_DUMMY 0x000000ac
+/* [0xb0]: REG Channel 22 Control */
+#define WB_TRIG_MUX_REG_CH22_CTL 0x000000b0
+/* [0xb4]: REG Channel 22 Dummy Register */
+#define WB_TRIG_MUX_REG_CH22_DUMMY 0x000000b4
+/* [0xb8]: REG Channel 23 Control */
+#define WB_TRIG_MUX_REG_CH23_CTL 0x000000b8
+/* [0xbc]: REG Channel 23 Dummy Register */
+#define WB_TRIG_MUX_REG_CH23_DUMMY 0x000000bc
+#endif
diff --git a/include/mem_layout_common.h b/include/mem_layout_common.h
index e354398571bb5a0b86fbebb91ca68840655badbc..73febe62e40708f65f5b17d59e1676ef07b0989a 100644
--- a/include/mem_layout_common.h
+++ b/include/mem_layout_common.h
@@ -37,6 +37,12 @@ extern "C" {
/* ACQ Components */
#define WB_ACQ_CORE_CTRL_RAW_REGS_OFFS 0x0000
+/* Trigger Interface Components */
+#define WB_TRIGGER_IFACE_RAW_REG_OFFS 0x0000
+
+/* Trigger Mux Components */
+#define WB_TRIGGER_MUX_RAW_REG_OFFS 0x0000
+
/* Large Memory RAW Addresses. It lives at address 0 */
#define LARGE_MEM_RAW_ADDR 0x00000000
diff --git a/include/rw_param.h b/include/rw_param.h
index 81f302b54f10fdd0322fc6a0074e890f2f5fdacc..5d2462b5f42b11aa8bf6f943776d3ecaa6958ee1 100644
--- a/include/rw_param.h
+++ b/include/rw_param.h
@@ -227,6 +227,59 @@ typedef int (*rw_param_format_fp) (uint32_t *param);
max, chk_funcp, fmt_funcp, clr_field, smio_thsafe_client_read_32, \
smio_thsafe_client_write_32)
+/* zmq message in SET_GET_PARAM_CHANNEL macro is:
+ * frame 0: operation code
+ * frame 1: rw R /W 1 = read mode, 0 = write mode
+ * frame 2: channel (0 to num_channels -1)
+ * frame 3: value to be written (rw = 0) or dummy value (rw = 1)
+ * */
+#define SET_GET_PARAM_CHANNEL_GEN(module, base_addr, prefix, reg, field, \
+ chan_offset, chan_num, single_bit, min, max, chk_funcp, fmt_funcp, clr_field, \
+ read_32_fp, write_32_fp) \
+ do { \
+ assert (owner); \
+ assert (args); \
+ DBE_DEBUG (DBG_SM_IO | DBG_LVL_TRACE, "[sm_io:rw_param:"#module"] " \
+ "Calling SET_GET_PARAM_"#reg"\n"); \
+ SMIO_OWNER_TYPE *self = SMIO_EXP_OWNER(owner); \
+ uint32_t rw = *(uint32_t *) EXP_MSG_ZMQ_FIRST_ARG(args); \
+ uint32_t chan = *(uint32_t *) EXP_MSG_ZMQ_NEXT_ARG(args); \
+ uint32_t value = *(uint32_t *) EXP_MSG_ZMQ_NEXT_ARG(args); \
+ DBE_DEBUG (DBG_SM_IO | DBG_LVL_TRACE, "[sm_io:rw_param:"#module"] " \
+ "SET_GET_PARAM_CHANNEL_"#reg": rw = %u, chan = %u\n", rw, chan); \
+ RW_REPLY_TYPE set_param_return; \
+ \
+ if (chan > chan_num-1) { \
+ return -RW_INV; \
+ } \
+ if (rw) { \
+ set_param_return = GET_PARAM_GEN(self, module, \
+ (base_addr + (chan*chan_offset)), \
+ prefix, reg, field, single_bit, value, fmt_funcp, read_32_fp); \
+ if (set_param_return != RW_OK) { \
+ return -set_param_return; \
+ } \
+ else { \
+ *(uint32_t *) ret = value; \
+ return sizeof(value); \
+ } \
+ } \
+ else { \
+ set_param_return = SET_PARAM_GEN(self, module, \
+ (base_addr + (chan*chan_offset)), \
+ prefix, reg, field, single_bit, value, min, max, chk_funcp, \
+ clr_field, read_32_fp, write_32_fp); \
+ return -set_param_return; \
+ } \
+ } while (0)
+
+#define SET_GET_PARAM_CHANNEL(module, base_addr, prefix, reg, field, chan_offset, \
+ chan_num, single_bit, min, max, chk_funcp, fmt_funcp, clr_field) \
+ SET_GET_PARAM_CHANNEL_GEN(module, base_addr, prefix, reg, field, \
+ chan_offset, chan_num, single_bit, min, max, chk_funcp, \
+ fmt_funcp, clr_field, smio_thsafe_client_read_32, \
+ smio_thsafe_client_write_32)
+
uint32_t check_param_limits (uint32_t value, uint32_t min, uint32_t max);
#endif
diff --git a/src/apps/ebpm/ebpm.c b/src/apps/ebpm/ebpm.c
index 680c027da22d076bf8f4eeeefdcfab7266ff2a1b..f1203a0e195ba480a10b34353cf1857a280dd5aa 100644
--- a/src/apps/ebpm/ebpm.c
+++ b/src/apps/ebpm/ebpm.c
@@ -884,6 +884,8 @@ static devio_err_e _spawn_be_platform_smios (void *pipe, zhashx_t *hints, uint32
/* AFCv3 spefific */
#if defined (__BOARD_AFCV3__)
uint32_t afc_diag_id = 0x51954750;
+ uint32_t trigger_iface_id = 0xbcbb78d2;
+ uint32_t trigger_mux_id = 0x84b6a5ac;
DBE_DEBUG (DBG_DEV_IO | DBG_LVL_INFO, "[ebpm] Spawning AFCv3 specific SMIOs ...\n");
@@ -928,6 +930,21 @@ static devio_err_e _spawn_be_platform_smios (void *pipe, zhashx_t *hints, uint32
if (err != DEVIO_SUCCESS) {
DBE_DEBUG (DBG_DEV_IO | DBG_LVL_FATAL, "[ebpm] devio_register_sm error!\n");
}
+
+ err = devio_register_sm (pipe, trigger_iface_id, WB_TRIGGER_IFACE_BASE_ADDR, 0);
+ if (err != DEVIO_SUCCESS) {
+ DBE_DEBUG (DBG_DEV_IO | DBG_LVL_FATAL, "[ebpm] devio_register_sm error!\n");
+ }
+
+ err = devio_register_sm (pipe, trigger_mux_id, WB_TRIGGER_MUX1_BASE_ADDR, 0);
+ if (err != DEVIO_SUCCESS) {
+ DBE_DEBUG (DBG_DEV_IO | DBG_LVL_FATAL, "[ebpm] devio_register_sm error!\n");
+ }
+
+ err = devio_register_sm (pipe, trigger_mux_id, WB_TRIGGER_MUX2_BASE_ADDR, 1);
+ if (err != DEVIO_SUCCESS) {
+ DBE_DEBUG (DBG_DEV_IO | DBG_LVL_FATAL, "[ebpm] devio_register_sm error!\n");
+ }
#endif
#else
#error "BE FPGA Board not supported!"
diff --git a/src/libs/libbpmclient/Makefile b/src/libs/libbpmclient/Makefile
index 2b36fec4f3dcdbb0cf49f14f6b2cbd3d4b44376d..7785c0a67801873b936bcceb09c86dada8f7851f 100644
--- a/src/libs/libbpmclient/Makefile
+++ b/src/libs/libbpmclient/Makefile
@@ -104,7 +104,9 @@ OBJS_EXTERNAL = ../../sm_io/modules/sm_io_codes.o \
../../sm_io/modules/fmc_active_clk/sm_io_fmc_active_clk_exports.o \
../../sm_io/modules/swap/sm_io_swap_exports.o \
../../sm_io/modules/rffe/sm_io_rffe_exports.o \
- ../../sm_io/modules/afc_diag/sm_io_afc_diag_exports.o
+ ../../sm_io/modules/afc_diag/sm_io_afc_diag_exports.o \
+ ../../sm_io/modules/trigger_iface/sm_io_trigger_iface_exports.o \
+ ../../sm_io/modules/trigger_mux/sm_io_trigger_mux_exports.o
# Project boards
boards_INCLUDE_DIRS = -I../../../include/boards/$(BOARD)
@@ -123,6 +125,8 @@ INCLUDE_DIRS = -I. -Iinclude \
-I../../sm_io/modules/dsp \
-I../../sm_io/modules/rffe \
-I../../sm_io/modules/afc_diag \
+ -I../../sm_io/modules/trigger_iface \
+ -I../../sm_io/modules/trigger_mux \
-I${PREFIX}/include
# Merge all flags. We expect tghese variables to be appended to the possible
@@ -156,6 +160,8 @@ $(LIBNAME)_SMIO_CODES = ../../sm_io/modules/fmc130m_4ch/sm_io_fmc130m_4ch_codes.
../../sm_io/modules/swap/sm_io_swap_codes.h \
../../sm_io/modules/rffe/sm_io_rffe_codes.h \
../../sm_io/modules/afc_diag/sm_io_afc_diag_codes.h \
+ ../../sm_io/modules/trigger_iface/sm_io_trigger_iface_codes.h \
+ ../../sm_io/modules/trigger_mux/sm_io_trigger_mux_codes.h \
../../sm_io/modules/sm_io_codes.h
$(LIBNAME)_SMIO_EXPORTS = ../../sm_io/modules/fmc130m_4ch/sm_io_fmc130m_4ch_exports.h \
@@ -166,7 +172,9 @@ $(LIBNAME)_SMIO_EXPORTS = ../../sm_io/modules/fmc130m_4ch/sm_io_fmc130m_4ch_expo
../../sm_io/modules/dsp/sm_io_dsp_exports.h \
../../sm_io/modules/swap/sm_io_swap_exports.h \
../../sm_io/modules/rffe/sm_io_rffe_exports.h \
- ../../sm_io/modules/afc_diag/sm_io_afc_diag_exports.h
+ ../../sm_io/modules/afc_diag/sm_io_afc_diag_exports.h \
+ ../../sm_io/modules/trigger_iface/sm_io_trigger_iface_exports.h \
+ ../../sm_io/modules/trigger_mux/sm_io_trigger_mux_exports.h
# Copy specific acq_chan.h defintions according to the BOARD MACRO
$(LIBNAME)_ACQ_HEADERS_BASENAME = acq_chan
diff --git a/src/libs/libbpmclient/include/bpm_client_core.h b/src/libs/libbpmclient/include/bpm_client_core.h
index 758f958eb4b1af763f49ae9b723d3a3b904cec33..f4d785799e7b84baa3c5f097667a2d094dfba527 100644
--- a/src/libs/libbpmclient/include/bpm_client_core.h
+++ b/src/libs/libbpmclient/include/bpm_client_core.h
@@ -912,6 +912,115 @@ bpm_client_err_e bpm_get_afc_diag_build_user_name (bpm_client_t *self, char *ser
bpm_client_err_e bpm_get_afc_diag_build_user_email (bpm_client_t *self, char *service,
struct _smio_afc_diag_revision_data_t *revision_data);
+/****************************** Trigger Functions ****************************/
+
+/* Trigger Direction functions */
+/* These set of functions write (set) or read (get) the trigger direction of
+ * a specified channel "chan".
+ * All of the functions returns BPM_CLIENT_SUCCESS if the parameter was
+ * correctly set or error (see bpm_client_err.h for all possible errors)*/
+bpm_client_err_e bpm_set_trigger_dir (bpm_client_t *self, char *service,
+ uint32_t chan, uint32_t dir);
+bpm_client_err_e bpm_get_trigger_dir (bpm_client_t *self, char *service,
+ uint32_t chan, uint32_t *dir);
+
+/* Trigger Direction Polarity functions */
+/* These set of functions write (set) or read (get) the trigger direction
+ * polarity of a specified channel "chan". When set to 0, the output
+ * direction signal is kept the same as the FPGA internal. When set to
+ * 1, the output direction signal is reversed.
+ * All of the functions returns BPM_CLIENT_SUCCESS if the parameter was
+ * correctly set or error (see bpm_client_err.h for all possible errors)*/
+bpm_client_err_e bpm_set_trigger_dir_pol (bpm_client_t *self, char *service,
+ uint32_t chan, uint32_t dir_pol);
+bpm_client_err_e bpm_get_trigger_dir_pol (bpm_client_t *self, char *service,
+ uint32_t chan, uint32_t *dir_pol);
+
+/* Trigger Receive/Transmit Counter Reset functions */
+/* These set of functions write (set) or read (get) the reset of the
+ * receiver or transmitter trigger counters of a specified channel "chan".
+ * All of the functions returns BPM_CLIENT_SUCCESS if the parameter was
+ * correctly set or error (see bpm_client_err.h for all possible errors)*/
+bpm_client_err_e bpm_set_trigger_rcv_count_rst (bpm_client_t *self, char *service,
+ uint32_t chan, uint32_t rcv_count_rst);
+bpm_client_err_e bpm_get_trigger_rcv_count_rst (bpm_client_t *self, char *service,
+ uint32_t chan, uint32_t *rcv_count_rst);
+bpm_client_err_e bpm_set_trigger_transm_count_rst (bpm_client_t *self, char *service,
+ uint32_t chan, uint32_t transm_count_rst);
+bpm_client_err_e bpm_get_trigger_transm_count_rst (bpm_client_t *self, char *service,
+ uint32_t chan, uint32_t *transm_count_rst);
+
+/* Trigger Receive/Transmit Debounce/Extension length functions */
+/* These set of functions write (set) or read (get) the debounce (for receiver) and
+ * pulse extension (for transmitter) for the triggers of a specified channel "chan".
+ * All of the functions returns BPM_CLIENT_SUCCESS if the parameter was
+ * correctly set or error (see bpm_client_err.h for all possible errors)*/
+bpm_client_err_e bpm_set_trigger_rcv_len (bpm_client_t *self, char *service,
+ uint32_t chan, uint32_t rcv_len);
+bpm_client_err_e bpm_get_trigger_rcv_len (bpm_client_t *self, char *service,
+ uint32_t chan, uint32_t *rcv_len);
+bpm_client_err_e bpm_set_trigger_transm_len (bpm_client_t *self, char *service,
+ uint32_t chan, uint32_t transm_len);
+bpm_client_err_e bpm_get_trigger_transm_len (bpm_client_t *self, char *service,
+ uint32_t chan, uint32_t *transm_len);
+
+/* Trigger Receive/Transmit Trigger Counter functions */
+/* These set of functions write (set) or read (get) the trigger counters
+ * of a specified channel "chan".
+ * All of the functions returns BPM_CLIENT_SUCCESS if the parameter was
+ * correctly set or error (see bpm_client_err.h for all possible errors)*/
+bpm_client_err_e bpm_set_trigger_count_rcv (bpm_client_t *self, char *service,
+ uint32_t chan, uint32_t count_rcv);
+bpm_client_err_e bpm_get_trigger_count_rcv (bpm_client_t *self, char *service,
+ uint32_t chan, uint32_t *count_rcv);
+bpm_client_err_e bpm_set_trigger_count_transm (bpm_client_t *self, char *service,
+ uint32_t chan, uint32_t count_transm);
+bpm_client_err_e bpm_get_trigger_count_transm (bpm_client_t *self, char *service,
+ uint32_t chan, uint32_t *count_transm);
+
+/**************************** Trigger Mux Functions ***************************/
+
+/* Trigger Receive Source functions */
+/* These set of functions write (set) or read (get) the trigger source for the
+ * receiver of a specified channel "chan".
+ * All of the functions returns BPM_CLIENT_SUCCESS if the parameter was
+ * correctly set or error (see bpm_client_err.h for all possible errors)*/
+bpm_client_err_e bpm_set_trigger_rcv_src (bpm_client_t *self, char *service,
+ uint32_t chan, uint32_t rcv_src);
+bpm_client_err_e bpm_get_trigger_rcv_src (bpm_client_t *self, char *service,
+ uint32_t chan, uint32_t *rcv_src);
+
+/* Trigger Receive Selection functions */
+/* These set of functions write (set) or read (get) the trigger selection for the
+ * receiver of a specified channel "chan".
+ * All of the functions returns BPM_CLIENT_SUCCESS if the parameter was
+ * correctly set or error (see bpm_client_err.h for all possible errors)*/
+bpm_client_err_e bpm_set_trigger_rcv_in_sel (bpm_client_t *self, char *service,
+ uint32_t chan, uint32_t rcv_in_sel);
+bpm_client_err_e bpm_get_trigger_rcv_in_sel (bpm_client_t *self, char *service,
+ uint32_t chan, uint32_t *rcv_in_sel);
+
+/* Trigger Transmit Source functions */
+/* These set of functions write (set) or read (get) the trigger source for the
+ * transmitter of a specified channel "chan".
+ * All of the functions returns BPM_CLIENT_SUCCESS if the parameter was
+ * correctly set or error (see bpm_client_err.h for all possible errors)*/
+bpm_client_err_e bpm_set_trigger_transm_src (bpm_client_t *self, char *service,
+ uint32_t chan, uint32_t transm_src);
+bpm_client_err_e bpm_get_trigger_transm_src (bpm_client_t *self, char *service,
+ uint32_t chan, uint32_t *transm_src);
+
+/* Trigger Transmit Selection functions */
+/* These set of functions write (set) or read (get) the trigger selection for the
+ * transmitter of a specified channel "chan".
+ * All of the functions returns BPM_CLIENT_SUCCESS if the parameter was
+ * correctly set or error (see bpm_client_err.h for all possible errors)*/
+bpm_client_err_e bpm_set_trigger_transm_out_sel (bpm_client_t *self, char *service,
+ uint32_t chan, uint32_t transm_out_sel);
+bpm_client_err_e bpm_get_trigger_transm_out_sel (bpm_client_t *self, char *service,
+ uint32_t chan, uint32_t *transm_out_sel);
+
+/****************************** Helper Functions ****************************/
/* Helper Function */
/* This function execute the given function *func in a disp_op_t
diff --git a/src/libs/libbpmclient/include/bpm_client_rw_param.h b/src/libs/libbpmclient/include/bpm_client_rw_param.h
index 9619a5d694ba00182a697c13274eddb88468b516..4ac2300cd78f28dbd063e3df8324733c9b6ed082 100644
--- a/src/libs/libbpmclient/include/bpm_client_rw_param.h
+++ b/src/libs/libbpmclient/include/bpm_client_rw_param.h
@@ -56,33 +56,50 @@ extern "C" {
bpm_client_err_e PARAM_FUNC_CLIENT_NAME_READ(reg) (bpm_client_t *self, \
char *service, uint32_t *param1, uint32_t *param2)
+#define PARAM_FUNC_CLIENT_WRITE_READ(reg, param1, param_out) \
+ bpm_client_err_e PARAM_FUNC_CLIENT_NAME_READ(reg) (bpm_client_t *self, \
+ char *service, uint32_t param1, uint32_t *param_out)
+
#define PARAM_FUNC_CLIENT_READ_GEN(param) \
bpm_client_err_e PARAM_FUNC_CLIENT_NAME_READ(param) (bpm_client_t *self, \
char *service, void *param, size_t size)
/* Low-level protocol functions */
bpm_client_err_e param_client_send_gen_rw (bpm_client_t *self, char *service,
- uint32_t operation, uint32_t rw, void *param, size_t size);
+ uint32_t operation, uint32_t rw, void *param1, size_t size1,
+ void *param2, size_t size2);
bpm_client_err_e param_client_recv_rw (bpm_client_t *self, char *service,
zmsg_t **report);
/* Write functions */
+bpm_client_err_e param_client_write_gen (bpm_client_t *self, char *service,
+ uint32_t operation, uint32_t rw, void *param1, size_t size1,
+ void *param2, size_t size2);
bpm_client_err_e param_client_write_raw (bpm_client_t *self, char *service,
uint32_t operation, uint32_t param1, uint32_t param2);
+
bpm_client_err_e param_client_write (bpm_client_t *self, char *service,
- uint32_t operation, uint32_t param);
+ uint32_t operation, uint32_t param1);
+bpm_client_err_e param_client_write2 (bpm_client_t *self, char *service,
+ uint32_t operation, uint32_t param1, uint32_t param2);
bpm_client_err_e param_client_write_double (bpm_client_t *self, char *service,
- uint32_t operation, double param);
-bpm_client_err_e param_client_write_gen (bpm_client_t *self, char *service,
- uint32_t operation, uint32_t param1, void *param2, size_t size);
+ uint32_t operation, double param1);
+bpm_client_err_e param_client_write_double2 (bpm_client_t *self, char *service,
+ uint32_t operation, double param1, double param2);
/* Read functions */
+bpm_client_err_e param_client_read_gen (bpm_client_t *self, char *service,
+ uint32_t operation, uint32_t rw, void *param1, size_t size1,
+ void *param2, size_t size2, void *param_out, size_t size_out);
+
bpm_client_err_e param_client_read (bpm_client_t *self, char *service,
uint32_t operation, uint32_t *param_out);
-bpm_client_err_e param_client_read_gen (bpm_client_t *self, char *service,
- uint32_t operation, uint32_t param1, void *param_out, size_t size);
+bpm_client_err_e param_client_write_read (bpm_client_t *self, char *service,
+ uint32_t operation, uint32_t param1, uint32_t *param_out);
bpm_client_err_e param_client_read_double (bpm_client_t *self, char *service,
uint32_t operation, double *param_out);
+bpm_client_err_e param_client_write_read_double (bpm_client_t *self, char *service,
+ uint32_t operation, double param1, double *param_out);
/* Utility functions */
zmsg_t *param_client_recv_timeout (bpm_client_t *self);
diff --git a/src/libs/libbpmclient/src/bpm_client_core.c b/src/libs/libbpmclient/src/bpm_client_core.c
index c9c34d9dabe0b379c6cb1b08e2919799c3678802..ce112abc0a31691a2af49a63c97f85e3e1544e0d 100644
--- a/src/libs/libbpmclient/src/bpm_client_core.c
+++ b/src/libs/libbpmclient/src/bpm_client_core.c
@@ -1794,7 +1794,7 @@ bpm_client_err_e bpm_set_rffe_data (bpm_client_t *self, char *service,
{
uint32_t rw = WRITE_MODE;
return param_client_write_gen (self, service, RFFE_OPCODE_SET_GET_DATA,
- rw, rffe_data_block, sizeof (*rffe_data_block));
+ rw, rffe_data_block, sizeof (*rffe_data_block), NULL, 0);
}
bpm_client_err_e bpm_get_rffe_data (bpm_client_t *self, char *service,
@@ -1802,7 +1802,8 @@ bpm_client_err_e bpm_get_rffe_data (bpm_client_t *self, char *service,
{
uint32_t rw = READ_MODE;
return param_client_read_gen (self, service, RFFE_OPCODE_SET_GET_DATA,
- rw, rffe_data_block, sizeof (*rffe_data_block));
+ rw, rffe_data_block, sizeof (*rffe_data_block), NULL, 0,
+ rffe_data_block, sizeof (*rffe_data_block));
}
/* RFFE get version */
@@ -1811,7 +1812,8 @@ bpm_client_err_e bpm_get_rffe_version (bpm_client_t *self, char *service,
{
uint32_t rw = READ_MODE;
return param_client_read_gen (self, service, RFFE_OPCODE_SET_GET_VERSION,
- rw, rffe_version, sizeof (*rffe_version));
+ rw, rffe_version, sizeof (*rffe_version), NULL, 0,
+ rffe_version, sizeof (*rffe_version));
}
/* RFFE get/set switching level */
@@ -1861,7 +1863,8 @@ bpm_client_err_e bpm_get_afc_diag_build_revision (bpm_client_t *self, char *serv
{
uint32_t rw = READ_MODE;
return param_client_read_gen (self, service, AFC_DIAG_OPCODE_GET_BUILD_REVISION,
- rw, revision_data, sizeof (*revision_data));
+ rw, revision_data, sizeof (*revision_data), NULL, 0,
+ revision_data, sizeof (*revision_data));
}
/* Build Date */
@@ -1870,7 +1873,8 @@ bpm_client_err_e bpm_get_afc_diag_build_date (bpm_client_t *self, char *service,
{
uint32_t rw = READ_MODE;
return param_client_read_gen (self, service, AFC_DIAG_OPCODE_GET_BUILD_DATE,
- rw, revision_data, sizeof (*revision_data));
+ rw, revision_data, sizeof (*revision_data), NULL, 0,
+ revision_data, sizeof (*revision_data));
}
/* Build User Name */
@@ -1879,7 +1883,8 @@ bpm_client_err_e bpm_get_afc_diag_build_user_name (bpm_client_t *self, char *ser
{
uint32_t rw = READ_MODE;
return param_client_read_gen (self, service, AFC_DIAG_OPCODE_GET_BUILD_USER_NAME,
- rw, revision_data, sizeof (*revision_data));
+ rw, revision_data, sizeof (*revision_data), NULL, 0,
+ revision_data, sizeof (*revision_data));
}
/* Build User Email */
@@ -1888,7 +1893,168 @@ bpm_client_err_e bpm_get_afc_diag_build_user_email (bpm_client_t *self, char *se
{
uint32_t rw = READ_MODE;
return param_client_read_gen (self, service, AFC_DIAG_OPCODE_GET_BUILD_USER_EMAIL,
- rw, revision_data, sizeof (*revision_data));
+ rw, revision_data, sizeof (*revision_data), NULL, 0,
+ revision_data, sizeof (*revision_data));
+}
+
+/********************** Trigger Interface Functions ********************/
+
+/* Trigger direction */
+PARAM_FUNC_CLIENT_WRITE2(trigger_dir, chan, dir)
+{
+ return param_client_write2 (self, service, TRIGGER_IFACE_OPCODE_DIR,
+ chan, dir);
+}
+
+PARAM_FUNC_CLIENT_WRITE_READ(trigger_dir, chan, dir)
+{
+ return param_client_write_read (self, service, TRIGGER_IFACE_OPCODE_DIR,
+ chan, dir);
+}
+
+/* Trigger direction */
+PARAM_FUNC_CLIENT_WRITE2(trigger_dir_pol, chan, dir_pol)
+{
+ return param_client_write2 (self, service, TRIGGER_IFACE_OPCODE_DIR_POL,
+ chan, dir_pol);
+}
+
+PARAM_FUNC_CLIENT_WRITE_READ(trigger_dir_pol, chan, dir_pol)
+{
+ return param_client_write_read (self, service, TRIGGER_IFACE_OPCODE_DIR_POL,
+ chan, dir_pol);
+}
+
+/* Trigger receive counter reset */
+PARAM_FUNC_CLIENT_WRITE2(trigger_rcv_count_rst, chan, rcv_count_rst)
+{
+ return param_client_write2 (self, service, TRIGGER_IFACE_OPCODE_RCV_COUNT_RST,
+ chan, rcv_count_rst);
+}
+
+PARAM_FUNC_CLIENT_WRITE_READ(trigger_rcv_count_rst, chan, rcv_count_rst)
+{
+ return param_client_write_read (self, service, TRIGGER_IFACE_OPCODE_RCV_COUNT_RST,
+ chan, rcv_count_rst);
+}
+
+/* Trigger transmit counter reset */
+PARAM_FUNC_CLIENT_WRITE2(trigger_transm_count_rst, chan, transm_count_rst)
+{
+ return param_client_write2 (self, service, TRIGGER_IFACE_OPCODE_TRANSM_COUNT_RST,
+ chan, transm_count_rst);
+}
+
+PARAM_FUNC_CLIENT_WRITE_READ(trigger_transm_count_rst, chan, transm_count_rst)
+{
+ return param_client_write_read (self, service, TRIGGER_IFACE_OPCODE_TRANSM_COUNT_RST,
+ chan, transm_count_rst);
+}
+
+/* Trigger receive length debounce */
+PARAM_FUNC_CLIENT_WRITE2(trigger_rcv_len, chan, rcv_len)
+{
+ return param_client_write2 (self, service, TRIGGER_IFACE_OPCODE_RCV_LEN,
+ chan, rcv_len);
+}
+
+PARAM_FUNC_CLIENT_WRITE_READ(trigger_rcv_len, chan, rcv_len)
+{
+ return param_client_write_read (self, service, TRIGGER_IFACE_OPCODE_RCV_LEN,
+ chan, rcv_len);
+}
+
+/* Trigger transmit length debounce */
+PARAM_FUNC_CLIENT_WRITE2(trigger_transm_len, chan, transm_len)
+{
+ return param_client_write2 (self, service, TRIGGER_IFACE_OPCODE_TRANSM_LEN,
+ chan, transm_len);
+}
+
+PARAM_FUNC_CLIENT_WRITE_READ(trigger_transm_len, chan, transm_len)
+{
+ return param_client_write_read (self, service, TRIGGER_IFACE_OPCODE_TRANSM_LEN,
+ chan, transm_len);
+}
+
+/* Trigger count_receive */
+PARAM_FUNC_CLIENT_WRITE2(trigger_count_rcv, chan, count_rcv)
+{
+ return param_client_write2 (self, service, TRIGGER_IFACE_OPCODE_COUNT_RCV,
+ chan, count_rcv);
+}
+
+PARAM_FUNC_CLIENT_WRITE_READ(trigger_count_rcv, chan, count_rcv)
+{
+ return param_client_write_read (self, service, TRIGGER_IFACE_OPCODE_COUNT_RCV,
+ chan, count_rcv);
+}
+
+/* Trigger count transmit */
+PARAM_FUNC_CLIENT_WRITE2(trigger_count_transm, chan, count_transm)
+{
+ return param_client_write2 (self, service, TRIGGER_IFACE_OPCODE_COUNT_TRANSM,
+ chan, count_transm);
+}
+
+PARAM_FUNC_CLIENT_WRITE_READ(trigger_count_transm, chan, count_transm)
+{
+ return param_client_write_read (self, service, TRIGGER_IFACE_OPCODE_COUNT_TRANSM,
+ chan, count_transm);
+}
+
+/********************** Trigger Mux Functions ********************/
+
+/* Trigger receive source */
+PARAM_FUNC_CLIENT_WRITE2(trigger_rcv_src, chan, rcv_src)
+{
+ return param_client_write2 (self, service, TRIGGER_MUX_OPCODE_RCV_SRC,
+ chan, rcv_src);
+}
+
+PARAM_FUNC_CLIENT_WRITE_READ(trigger_rcv_src, chan, rcv_src)
+{
+ return param_client_write_read (self, service, TRIGGER_MUX_OPCODE_RCV_SRC,
+ chan, rcv_src);
+}
+
+/* Trigger receive in selection */
+PARAM_FUNC_CLIENT_WRITE2(trigger_rcv_in_sel, chan, rcv_in_sel)
+{
+ return param_client_write2 (self, service, TRIGGER_MUX_OPCODE_RCV_IN_SEL,
+ chan, rcv_in_sel);
+}
+
+PARAM_FUNC_CLIENT_WRITE_READ(trigger_rcv_in_sel, chan, rcv_in_sel)
+{
+ return param_client_write_read (self, service, TRIGGER_MUX_OPCODE_RCV_IN_SEL,
+ chan, rcv_in_sel);
+}
+
+/* Trigger transmit source */
+PARAM_FUNC_CLIENT_WRITE2(trigger_transm_src, chan, transm_src)
+{
+ return param_client_write2 (self, service, TRIGGER_MUX_OPCODE_TRANSM_SRC,
+ chan, transm_src);
+}
+
+PARAM_FUNC_CLIENT_WRITE_READ(trigger_transm_src, chan, transm_src)
+{
+ return param_client_write_read (self, service, TRIGGER_MUX_OPCODE_TRANSM_SRC,
+ chan, transm_src);
+}
+
+/* Trigger transmit selection */
+PARAM_FUNC_CLIENT_WRITE2(trigger_transm_out_sel, chan, transm_out_sel)
+{
+ return param_client_write2 (self, service, TRIGGER_MUX_OPCODE_TRANSM_OUT_SEL,
+ chan, transm_out_sel);
+}
+
+PARAM_FUNC_CLIENT_WRITE_READ(trigger_transm_out_sel, chan, transm_out_sel)
+{
+ return param_client_write_read (self, service, TRIGGER_MUX_OPCODE_TRANSM_OUT_SEL,
+ chan, transm_out_sel);
}
/**************** Helper Function ****************/
diff --git a/src/libs/libbpmclient/src/bpm_client_rw_param.c b/src/libs/libbpmclient/src/bpm_client_rw_param.c
index dd10d1616d777343e9f87acf2b0889ec95cbc4ff..7f8cd9d633940a53feb770170a126f0f67bccdde 100644
--- a/src/libs/libbpmclient/src/bpm_client_rw_param.c
+++ b/src/libs/libbpmclient/src/bpm_client_rw_param.c
@@ -35,12 +35,13 @@
bpm_client_err_str (err_type))
bpm_client_err_e param_client_send_gen_rw (bpm_client_t *self, char *service,
- uint32_t operation, uint32_t rw, void *param, size_t size)
+ uint32_t operation, uint32_t rw, void *param1, size_t size1,
+ void *param2, size_t size2)
{
bpm_client_err_e err = BPM_CLIENT_SUCCESS;
- ASSERT_TEST(param != NULL, "param_client_send_gen_rw (): parameter cannot be NULL",
- err_param_null, BPM_CLIENT_ERR_INV_PARAM);
+ ASSERT_TEST(param1 != NULL, "param_client_send_gen_rw (): parameter cannot be NULL",
+ err_param1_null, BPM_CLIENT_ERR_INV_PARAM);
mlm_client_t *client = bpm_get_mlm_client (self);
ASSERT_TEST(client != NULL, "Could not get BPM client handler", err_get_handler,
@@ -50,7 +51,10 @@ bpm_client_err_e param_client_send_gen_rw (bpm_client_t *self, char *service,
ASSERT_ALLOC(request, err_send_msg_alloc, BPM_CLIENT_ERR_ALLOC);
zmsg_addmem (request, &operation, sizeof (operation));
zmsg_addmem (request, &rw, sizeof (rw));
- zmsg_addmem (request, param, size);
+ zmsg_addmem (request, param1, size1);
+ if (param2 != NULL) {
+ zmsg_addmem (request, param2, size2);
+ }
/* Get poller and timeout from client */
uint32_t timeout = bpm_client_get_timeout (self);
@@ -61,7 +65,7 @@ bpm_client_err_e param_client_send_gen_rw (bpm_client_t *self, char *service,
err_send_msg_alloc:
err_get_handler:
-err_param_null:
+err_param1_null:
return err;
}
@@ -87,7 +91,8 @@ err_get_handler:
}
bpm_client_err_e param_client_write_gen (bpm_client_t *self, char *service,
- uint32_t operation, uint32_t param1, void *param2, size_t size)
+ uint32_t operation, uint32_t rw, void *param1, size_t size1,
+ void *param2, size_t size2)
{
assert (self);
assert (service);
@@ -95,8 +100,8 @@ bpm_client_err_e param_client_write_gen (bpm_client_t *self, char *service,
bpm_client_err_e err = BPM_CLIENT_SUCCESS;
zmsg_t *report;
- err = param_client_send_gen_rw (self, service, operation, param1, param2,
- size);
+ err = param_client_send_gen_rw (self, service, operation, rw, param1,
+ size1, param2, size2);
ASSERT_TEST(err == BPM_CLIENT_SUCCESS, "Could not send message", err_send_msg);
err = param_client_recv_rw (self, service, &report);
ASSERT_TEST(err == BPM_CLIENT_SUCCESS, "Could not receive message", err_recv_msg);
@@ -131,7 +136,7 @@ bpm_client_err_e param_client_write_raw (bpm_client_t *self, char *service,
uint32_t operation, uint32_t param1, uint32_t param2)
{
return param_client_write_gen (self, service, operation, param1, ¶m2,
- sizeof (param2));
+ sizeof (param2), NULL, 0);
}
bpm_client_err_e param_client_write (bpm_client_t *self, char *service,
@@ -139,7 +144,7 @@ bpm_client_err_e param_client_write (bpm_client_t *self, char *service,
{
uint32_t rw = WRITE_MODE;
return param_client_write_gen (self, service, operation, rw, ¶m,
- sizeof (param));
+ sizeof (param), NULL, 0);
}
bpm_client_err_e param_client_write_double (bpm_client_t *self, char *service,
@@ -147,11 +152,28 @@ bpm_client_err_e param_client_write_double (bpm_client_t *self, char *service,
{
uint32_t rw = WRITE_MODE;
return param_client_write_gen (self, service, operation, rw, ¶m,
- sizeof (param));
+ sizeof (param), NULL, 0);
+}
+
+bpm_client_err_e param_client_write2 (bpm_client_t *self, char *service,
+ uint32_t operation, uint32_t param1, uint32_t param2)
+{
+ uint32_t rw = WRITE_MODE;
+ return param_client_write_gen (self, service, operation, rw, ¶m1,
+ sizeof (param1), ¶m2, sizeof (param2));
+}
+
+bpm_client_err_e param_client_write_double2 (bpm_client_t *self, char *service,
+ uint32_t operation, double param1, double param2)
+{
+ uint32_t rw = WRITE_MODE;
+ return param_client_write_gen (self, service, operation, rw, ¶m1,
+ sizeof (param1), ¶m2, sizeof (param2));
}
bpm_client_err_e param_client_read_gen (bpm_client_t *self, char *service,
- uint32_t operation, uint32_t param1, void *param_out, size_t size)
+ uint32_t operation, uint32_t rw, void *param1, size_t size1,
+ void *param2, size_t size2, void *param_out, size_t size_out)
{
assert (self);
assert (service);
@@ -163,8 +185,9 @@ bpm_client_err_e param_client_read_gen (bpm_client_t *self, char *service,
* message strucuture and the server will check for strict consistency
* (number of arguments and size) of all parameters. So, use the size of
* the passed parameter here */
- err = param_client_send_gen_rw (self, service, operation, param1,
- param_out /* in read mode this value will be ignored */, size);
+ err = param_client_send_gen_rw (self, service, operation, rw,
+ param1, size1,
+ param2, size2);
ASSERT_TEST(err == BPM_CLIENT_SUCCESS, "Could not send message", err_send_msg);
err = param_client_recv_rw (self, service, &report);
ASSERT_TEST(err == BPM_CLIENT_SUCCESS, "Could not receive message", err_recv_msg);
@@ -205,11 +228,11 @@ bpm_client_err_e param_client_read_gen (bpm_client_t *self, char *service,
err_msg_fmt);
/* We accept any payload that is less than the specified size */
- ASSERT_TEST(zframe_size (data_out_frm) <= size,
+ ASSERT_TEST(zframe_size (data_out_frm) <= size_out,
"Wrong <payload> parameter size", err_msg_fmt);
/* Copy the message contents to the user */
- memcpy (param_out, zframe_data (data_out_frm), size);
+ memcpy (param_out, zframe_data (data_out_frm), size_out);
}
err_msg_fmt:
@@ -232,7 +255,7 @@ bpm_client_err_e param_client_read (bpm_client_t *self, char *service,
{
uint32_t rw = READ_MODE;
return param_client_read_gen (self, service, operation, rw, param_out,
- sizeof (*param_out));
+ sizeof (*param_out), NULL, 0, param_out, sizeof (*param_out));
}
bpm_client_err_e param_client_read_double (bpm_client_t *self, char *service,
@@ -240,9 +263,24 @@ bpm_client_err_e param_client_read_double (bpm_client_t *self, char *service,
{
uint32_t rw = READ_MODE;
return param_client_read_gen (self, service, operation, rw, param_out,
- sizeof (*param_out));
+ sizeof (*param_out), NULL, 0, param_out, sizeof (*param_out));
+}
+
+bpm_client_err_e param_client_write_read (bpm_client_t *self, char *service,
+ uint32_t operation, uint32_t param1, uint32_t *param_out)
+{
+ uint32_t rw = READ_MODE;
+ return param_client_read_gen (self, service, operation, rw, ¶m1,
+ sizeof (param1), ¶m1, sizeof (param1), param_out, sizeof (*param_out));
}
+bpm_client_err_e param_client_write_read_double (bpm_client_t *self, char *service,
+ uint32_t operation, double param1, double *param_out)
+{
+ uint32_t rw = READ_MODE;
+ return param_client_read_gen (self, service, operation, rw, ¶m1,
+ sizeof (param1), ¶m1, sizeof (param1), param_out, sizeof (*param_out));
+}
/********************* Utility functions ************************************/
/* Wait for message to arrive up to timeout msecs */
diff --git a/src/libs/libdisptable/src/disptable_core.c b/src/libs/libdisptable/src/disptable_core.c
index a58f61717f61cfb29e8515744a93b9b444896ea3..1cf1c660f62444a166f836d4d51fd5c4800623de 100644
--- a/src/libs/libdisptable/src/disptable_core.c
+++ b/src/libs/libdisptable/src/disptable_core.c
@@ -469,17 +469,11 @@ static disp_table_err_e _disp_table_set_ret_op (disp_op_handler_t *disp_op_handl
goto err_exit;
}
- DBE_DEBUG (DBG_HAL_UTILS | DBG_LVL_TRACE,
- "[disp_table] _disp_table_set_ret_op: Setting return value ...\n");
-
/* FIXME: This shouldn't happen, as this type of error is caught on
* initialization of the dispatch function */
ASSERT_ALLOC (disp_op_handler->ret, err_ret_alloc, DISP_TABLE_ERR_ALLOC);
*ret = disp_op_handler->ret;
- DBE_DEBUG (DBG_HAL_UTILS | DBG_LVL_TRACE,
- "[disp_table] _disp_table_set_ret_op: Return value set\n");
-
err_ret_alloc:
err_exit:
return err;
diff --git a/src/libs/libllio/src/ops/ll_io_pcie.c b/src/libs/libllio/src/ops/ll_io_pcie.c
index a119acc1e4598aeba0077a5023489a418f080efb..d389db4ca04adaee39b002e314b06829ef959cb5 100644
--- a/src/libs/libllio/src/ops/ll_io_pcie.c
+++ b/src/libs/libllio/src/ops/ll_io_pcie.c
@@ -191,6 +191,8 @@ static int pcie_open (llio_t *self, llio_endpoint_t *endpoint)
/* Reset FPGA */
_pcie_reset_fpga (self);
+ /* Reset PCIe Timeout */
+ _pcie_timeout_reset (self);
return err;
diff --git a/src/sm_io/chips/sm_ch_ad9510.c b/src/sm_io/chips/sm_ch_ad9510.c
index 7c42c6355b3868fe154a4e62679b2a6029e9bd2f..55537155d28d51c8f7944891bcdd4489bf6c78c3 100644
--- a/src/sm_io/chips/sm_ch_ad9510.c
+++ b/src/sm_io/chips/sm_ch_ad9510.c
@@ -734,8 +734,9 @@ static smch_err_e _smch_ad9510_init (smch_ad9510_t *self)
ASSERT_TEST(rw_err == sizeof(uint8_t), "Could not write to AD9510_REG_CFG_SERIAL",
err_smpr_write, SMCH_ERR_RW_SMPR);
- _smch_ad9510_reg_update (self);
- /* Wait for reset to complete */
+ /* According to AD9510 datasheet Rev. B, page 46, table 25, regester 0x00 (CFG_SERIAL),
+ * does not need to be updated by setting the "update registers" bit. We still wait our default
+ * ammount of time to be sure the chip is indeed reset */
SMCH_AD9510_WAIT_DFLT;
/* Clear reset */
@@ -743,7 +744,10 @@ static smch_err_e _smch_ad9510_init (smch_ad9510_t *self)
rw_err = _smch_ad9510_write_8 (self, AD9510_REG_CFG_SERIAL, &data);
ASSERT_TEST(rw_err == sizeof(uint8_t), "Could not write to AD9510_REG_CFG_SERIAL",
err_smpr_write, SMCH_ERR_RW_SMPR);
- _smch_ad9510_reg_update (self);
+
+ /* According to AD9510 datasheet Rev. B, page 46, table 25, regester 0x00 (CFG_SERIAL),
+ * does not need to be updated by setting the "update registers" bit. We still wait our default
+ * ammount of time to be sure the chip is indeed reset */
/* Wait for reset to complete */
SMCH_AD9510_WAIT_DFLT;
diff --git a/src/sm_io/chips/sm_ch_si57x.c b/src/sm_io/chips/sm_ch_si57x.c
index 10f86d4b18c2ef70a2cc456f8ca08c5aa16be1e1..167475aba1278765845b99645aa56d2a487f15cd 100644
--- a/src/sm_io/chips/sm_ch_si57x.c
+++ b/src/sm_io/chips/sm_ch_si57x.c
@@ -394,8 +394,8 @@ static smch_err_e _smch_si57x_get_defaults (smch_si57x_t *self, double fout)
uint8_t data = SI57X_CONTROL_RECALL;
_smch_si57x_write_8 (self, SI57X_REG_CONTROL, &data);
- /* Si57x takes up to 30ms to return to initial conditions */
- SMCH_SI57X_WAIT(30000);
+ /* Si57x takes up to 30ms to return to initial conditions. To be safe, use 300ms */
+ SMCH_SI57X_WAIT(300000);
/* Read dividers */
err = _smch_si57x_get_divs (self, &self->rfreq, &self->n1, &self->hs_div);
diff --git a/src/sm_io/modules/acq/sm_io_acq_exp.c b/src/sm_io/modules/acq/sm_io_acq_exp.c
index f85feeeb2119fc3dd86deab588dcefbc511d2207..1319d11aad5831cfed8e4e4fbeaf9c75d41d11fb 100644
--- a/src/sm_io/modules/acq/sm_io_acq_exp.c
+++ b/src/sm_io/modules/acq/sm_io_acq_exp.c
@@ -114,8 +114,10 @@ static int _acq_data_acquire (void *owner, void *args, void *ret)
return -ACQ_NUM_CHAN_OOR;
}
- /* number of samples required is out of the maximum limit */
- uint32_t max_samples_multishot = ACQ_CORE_MULTISHOT_MEM_SIZE/acq->acq_buf[chan].sample_size;
+ /* number of samples required is out of the maximum limit. Maixmum number of samples
+ * in multishot mode is simply the maximum number of samples of the DPRAM. The DPRAM
+ * size is calculated to fit the largest sample in the design, so we are safe. */
+ uint32_t max_samples_multishot = ACQ_CORE_MULTISHOT_MEM_SIZE;
if (((num_shots == ACQ_CORE_MIN_NUM_SHOTS) &&
(num_samples_pre + num_samples_post > acq->acq_buf[chan].max_samples)) ||
((num_shots > ACQ_CORE_MIN_NUM_SHOTS) &&
diff --git a/src/sm_io/modules/fmc250m_4ch/sm_io_fmc250m_4ch_defaults.c b/src/sm_io/modules/fmc250m_4ch/sm_io_fmc250m_4ch_defaults.c
index 1bfd002d9ab0b4f9da90ea823a4559624a943243..a0d836e776ce69b7f0bd188c0159ebbdea69f620 100644
--- a/src/sm_io/modules/fmc250m_4ch/sm_io_fmc250m_4ch_defaults.c
+++ b/src/sm_io/modules/fmc250m_4ch/sm_io_fmc250m_4ch_defaults.c
@@ -51,8 +51,10 @@ smio_err_e fmc250m_4ch_config_defaults (char *broker_endp, char *service,
bpm_client_err_e client_err = BPM_CLIENT_SUCCESS;
smio_err_e err = SMIO_SUCCESS;
- bpm_client_t *config_client = bpm_client_new_log_mode (broker_endp, 0,
- log_file_name, SMIO_FMC250M_4CH_LIBBPMCLIENT_LOG_MODE);
+ /* For some reason, the default timeout is not enough for FMC250M SMIO. See github issue
+ * #119 */
+ bpm_client_t *config_client = bpm_client_new_log_mode_time (broker_endp, 0,
+ log_file_name, SMIO_FMC250M_4CH_LIBBPMCLIENT_LOG_MODE, 3000);
ASSERT_ALLOC(config_client, err_alloc_client);
client_err = bpm_set_rst_adcs (config_client, service, FMC250M_4CH_DFLT_RST_ADCS);
diff --git a/src/sm_io/modules/modules.mk b/src/sm_io/modules/modules.mk
index db170026cae78ff8cfadf24d187e7da533ad5999..b8871451e88a879f1503eb2eaa50f9e537dce354 100644
--- a/src/sm_io/modules/modules.mk
+++ b/src/sm_io/modules/modules.mk
@@ -6,7 +6,9 @@ include $(SRC_DIR)/sm_io/modules/fmc130m_4ch/fmc130m_4ch.mk \
$(SRC_DIR)/sm_io/modules/dsp/dsp.mk \
$(SRC_DIR)/sm_io/modules/swap/swap.mk \
$(SRC_DIR)/sm_io/modules/rffe/rffe.mk \
- $(SRC_DIR)/sm_io/modules/afc_diag/afc_diag.mk
+ $(SRC_DIR)/sm_io/modules/afc_diag/afc_diag.mk \
+ $(SRC_DIR)/sm_io/modules/trigger_iface/trigger_iface.mk \
+ $(SRC_DIR)/sm_io/modules/trigger_mux/trigger_mux.mk
sm_io_modules_DIR = $(SRC_DIR)/sm_io/modules
@@ -19,4 +21,6 @@ sm_io_modules_OBJS = $(sm_io_modules_DIR)/sm_io_codes.o \
$(sm_io_dsp_OBJS) \
$(sm_io_swap_OBJS) \
$(sm_io_rffe_OBJS) \
- $(sm_io_afc_diag_OBJS)
+ $(sm_io_afc_diag_OBJS) \
+ $(sm_io_trigger_iface_OBJS) \
+ $(sm_io_trigger_mux_OBJS)
diff --git a/src/sm_io/modules/sm_io_codes.c b/src/sm_io/modules/sm_io_codes.c
index 4a83fbb09edd5a077d1c2b888866759cfb90b081..b82d48e00e0e2bdb3167a9f9f232a28ba7d7c681 100644
--- a/src/sm_io/modules/sm_io_codes.c
+++ b/src/sm_io/modules/sm_io_codes.c
@@ -17,6 +17,8 @@ const disp_op_t **smio_exp_ops [] = {
swap_exp_ops,
rffe_exp_ops,
afc_diag_exp_ops,
+ trigger_iface_exp_ops,
+ trigger_mux_exp_ops,
NULL
};
diff --git a/src/sm_io/modules/sm_io_codes.h b/src/sm_io/modules/sm_io_codes.h
index 99c8b1ab354673b83e278e8bcf8c2c521db76901..a7e8d8d27ef476a12a488dd0f34fa7ed57bbbea6 100644
--- a/src/sm_io/modules/sm_io_codes.h
+++ b/src/sm_io/modules/sm_io_codes.h
@@ -31,6 +31,8 @@ typedef struct _smio_rffe_version_t smio_rffe_version_t;
#include "sm_io_swap_codes.h"
#include "sm_io_rffe_codes.h"
#include "sm_io_afc_diag_codes.h"
+#include "sm_io_trigger_iface_codes.h"
+#include "sm_io_trigger_mux_codes.h"
/* Include all function descriptors */
#include "sm_io_fmc130m_4ch_exports.h"
@@ -42,6 +44,8 @@ typedef struct _smio_rffe_version_t smio_rffe_version_t;
#include "sm_io_swap_exports.h"
#include "sm_io_rffe_exports.h"
#include "sm_io_afc_diag_exports.h"
+#include "sm_io_trigger_iface_exports.h"
+#include "sm_io_trigger_mux_exports.h"
/* Merge all function descriptors in a single structure */
extern const disp_op_t **smio_exp_ops [];
diff --git a/src/sm_io/modules/trigger_iface/sm_io_trigger_iface_codes.h b/src/sm_io/modules/trigger_iface/sm_io_trigger_iface_codes.h
new file mode 100644
index 0000000000000000000000000000000000000000..df9d2434ffa3c8ceab7b95a9f1a65ca2cea61f26
--- /dev/null
+++ b/src/sm_io/modules/trigger_iface/sm_io_trigger_iface_codes.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2016 LNLS (www.lnls.br)
+ * Author: Lucas Russo <lucas.russo@lnls.br>
+ *
+ * Released according to the GNU GPL, version 3 or any later version.
+ */
+
+#ifndef _SM_IO_TRIGGER_IFACE_CODES_H_
+#define _SM_IO_TRIGGER_IFACE_CODES_H_
+
+/* Messaging OPCODES */
+#define TRIGGER_IFACE_OPCODE_TYPE uint32_t
+#define TRIGGER_IFACE_OPCODE_SIZE (sizeof (TRIGGER_IFACE_OPCODE_TYPE))
+
+#define TRIGGER_IFACE_OPCODE_DIR 0
+#define TRIGGER_IFACE_NAME_DIR "trigger_iface_dir"
+#define TRIGGER_IFACE_OPCODE_DIR_POL 1
+#define TRIGGER_IFACE_NAME_DIR_POL "trigger_iface_dir_pol"
+#define TRIGGER_IFACE_OPCODE_RCV_COUNT_RST 2
+#define TRIGGER_IFACE_NAME_RCV_COUNT_RST "trigger_iface_rcv_count_rst"
+#define TRIGGER_IFACE_OPCODE_TRANSM_COUNT_RST 3
+#define TRIGGER_IFACE_NAME_TRANSM_COUNT_RST "trigger_iface_transm_count_rst"
+#define TRIGGER_IFACE_OPCODE_RCV_LEN 4
+#define TRIGGER_IFACE_NAME_RCV_LEN "trigger_iface_rcv_len"
+#define TRIGGER_IFACE_OPCODE_TRANSM_LEN 5
+#define TRIGGER_IFACE_NAME_TRANSM_LEN "trigger_iface_transm_len"
+#define TRIGGER_IFACE_OPCODE_COUNT_RCV 6
+#define TRIGGER_IFACE_NAME_COUNT_RCV "trigger_iface_count_rcv"
+#define TRIGGER_IFACE_OPCODE_COUNT_TRANSM 7
+#define TRIGGER_IFACE_NAME_COUNT_TRANSM "trigger_iface_count_transm"
+#define TRIGGER_IFACE_OPCODE_END 8
+
+/* Messaging Reply OPCODES */
+#define TRIGGER_IFACE_REPLY_TYPE uint32_t
+#define TRIGGER_IFACE_REPLY_SIZE (sizeof (TRIGGER_IFACE_REPLY_TYPE))
+
+#define TRIGGER_IFACE_OK 0 /* Operation was successful */
+#define TRIGGER_IFACE_ERR 1 /* Could not set/get value */
+#define TRIGGER_IFACE_UNINPL 2 /* Unimplemented function or operation */
+#define TRIGGER_IFACE_REPLY_END 3 /* End marker */
+
+#endif
diff --git a/src/sm_io/modules/trigger_iface/sm_io_trigger_iface_core.c b/src/sm_io/modules/trigger_iface/sm_io_trigger_iface_core.c
new file mode 100644
index 0000000000000000000000000000000000000000..0f39a6178a5ce25aad24f00a7fbea9a96aaf185d
--- /dev/null
+++ b/src/sm_io/modules/trigger_iface/sm_io_trigger_iface_core.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2016 LNLS (www.lnls.br)
+ * Author: Lucas Russo <lucas.russo@lnls.br>
+ *
+ * Released according to the GNU GPL, version 3 or any later version.
+ */
+
+#include "bpm_server.h"
+/* Private headers */
+#include "sm_io_trigger_iface_defaults.h"
+#include "sm_io_trigger_iface_core.h"
+
+/* Undef ASSERT_ALLOC to avoid conflicting with other ASSERT_ALLOC */
+#ifdef ASSERT_TEST
+#undef ASSERT_TEST
+#endif
+#define ASSERT_TEST(test_boolean, err_str, err_goto_label, /* err_core */ ...) \
+ ASSERT_HAL_TEST(test_boolean, SM_IO, "[sm_io_trigger_iface_core]", \
+ err_str, err_goto_label, /* err_core */ __VA_ARGS__)
+
+#ifdef ASSERT_ALLOC
+#undef ASSERT_ALLOC
+#endif
+#define ASSERT_ALLOC(ptr, err_goto_label, /* err_core */ ...) \
+ ASSERT_HAL_ALLOC(ptr, SM_IO, "[sm_io_trigger_iface_core]", \
+ smio_err_str(SMIO_ERR_ALLOC), \
+ err_goto_label, /* err_core */ __VA_ARGS__)
+
+#ifdef CHECK_ERR
+#undef CHECK_ERR
+#endif
+#define CHECK_ERR(err, err_type) \
+ CHECK_HAL_ERR(err, SM_IO, "[sm_io_trigger_iface_core]", \
+ smio_err_str (err_type))
+
+/* Creates a new instance of Device Information */
+smio_trigger_iface_t * smio_trigger_iface_new (smio_t *parent)
+{
+ (void) parent;
+
+ smio_trigger_iface_t *self = (smio_trigger_iface_t *) zmalloc (sizeof *self);
+ ASSERT_ALLOC(self, err_self_alloc);
+
+ return self;
+
+err_self_alloc:
+ return NULL;
+}
+
+/* Destroy an instance of the Device Information */
+smio_err_e smio_trigger_iface_destroy (smio_trigger_iface_t **self_p)
+{
+ assert (self_p);
+
+ if (*self_p) {
+ smio_trigger_iface_t *self = *self_p;
+
+ free (self);
+ *self_p = NULL;
+ }
+
+ return SMIO_SUCCESS;
+}
+
diff --git a/src/sm_io/modules/trigger_iface/sm_io_trigger_iface_core.h b/src/sm_io/modules/trigger_iface/sm_io_trigger_iface_core.h
new file mode 100644
index 0000000000000000000000000000000000000000..13c57845731b1dcd5b58d5629d16ebb82f81e42f
--- /dev/null
+++ b/src/sm_io/modules/trigger_iface/sm_io_trigger_iface_core.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2016 LNLS (www.lnls.br)
+ * Author: Lucas Russo <lucas.russo@lnls.br>
+ *
+ * Released according to the GNU GPL, version 3 or any later version.
+*/
+
+#ifndef _SM_IO_TRIGGER_IFACE_CORE_H_
+#define _SM_IO_TRIGGER_IFACE_CORE_H_
+
+typedef struct {
+ const uint32_t example;
+} smio_trigger_iface_t;
+
+/***************** Our methods *****************/
+
+/* Creates a new instance of the smio realization */
+smio_trigger_iface_t * smio_trigger_iface_new (smio_t *parent);
+/* Destroys the smio realizationn */
+smio_err_e smio_trigger_iface_destroy (smio_trigger_iface_t **self_p);
+
+#endif
diff --git a/src/sm_io/modules/trigger_iface/sm_io_trigger_iface_defaults.c b/src/sm_io/modules/trigger_iface/sm_io_trigger_iface_defaults.c
new file mode 100644
index 0000000000000000000000000000000000000000..836b642b33457658099e2b501bcb5a45845db03b
--- /dev/null
+++ b/src/sm_io/modules/trigger_iface/sm_io_trigger_iface_defaults.c
@@ -0,0 +1,78 @@
+/*
+ * Copyright (C) 2016 LNLS (www.lnls.br)
+ * Author: Lucas Russo <lucas.russo@lnls.br>
+ *
+ * Released according to the GNU GPL, version 3 or any later version.
+ */
+
+#include "bpm_server.h"
+/* Private headers */
+#include "sm_io_trigger_iface_defaults.h"
+
+/* Undef ASSERT_ALLOC to avoid conflicting with other ASSERT_ALLOC */
+#ifdef ASSERT_TEST
+#undef ASSERT_TEST
+#endif
+#define ASSERT_TEST(test_boolean, err_str, err_goto_label, /* err_core */ ...) \
+ ASSERT_HAL_TEST(test_boolean, SM_IO, "[sm_io:trigger_iface_defaults]", \
+ err_str, err_goto_label, /* err_core */ __VA_ARGS__)
+
+#ifdef ASSERT_ALLOC
+#undef ASSERT_ALLOC
+#endif
+#define ASSERT_ALLOC(ptr, err_goto_label, /* err_core */ ...) \
+ ASSERT_HAL_ALLOC(ptr, SM_IO, "[sm_io:trigger_iface_defaults]", \
+ smio_err_str(SMIO_ERR_ALLOC), \
+ err_goto_label, /* err_core */ __VA_ARGS__)
+
+#ifdef CHECK_ERR
+#undef CHECK_ERR
+#endif
+#define CHECK_ERR(err, err_type) \
+ CHECK_HAL_ERR(err, SM_IO, "[sm_io:trigger_iface_defaults]", \
+ smio_err_str (err_type))
+
+#define SMIO_TRIGGER_IFACE_LIBBPMCLIENT_LOG_MODE "a"
+#define SMIO_TRIGGER_IFACE_MAX_CHAN 24
+
+/* We use the actual libclient to send and configure our default values,
+ * maintaining internal consistency. So, in fact, we are sending ourselves
+ * a message containing the default values. Because of this approach, we
+ * only get to default our values when the functions are already exported
+ * to the broker, which happens on a late stage. This could cause a fast
+ * client to get an inconsistent state from our server */
+/* TODO: Avoid exporting the functions before we have initialized
+ * our server with the default values */
+smio_err_e trigger_iface_config_defaults (char *broker_endp, char *service,
+ const char *log_file_name)
+{
+ (void) log_file_name;
+ DBE_DEBUG (DBG_SM_IO | DBG_LVL_INFO, "[sm_io:trigger_iface_defaults] Configuring SMIO "
+ "TRIGGER_IFACE with default values ...\n");
+ bpm_client_err_e client_err = BPM_CLIENT_SUCCESS;
+ smio_err_e err = SMIO_SUCCESS;
+
+ bpm_client_t *config_client = bpm_client_new_log_mode (broker_endp, 0,
+ log_file_name, SMIO_TRIGGER_IFACE_LIBBPMCLIENT_LOG_MODE);
+ ASSERT_ALLOC(config_client, err_alloc_client);
+
+ uint32_t chan;
+ for (chan = 0; chan < SMIO_TRIGGER_IFACE_MAX_CHAN; ++chan) {
+ client_err = bpm_set_trigger_dir (config_client, service, chan, TRIGGER_IFACE_DFLT_DIR);
+ client_err |= bpm_set_trigger_dir_pol (config_client, service, chan, TRIGGER_IFACE_DFLT_DIR_POL);
+ client_err |= bpm_set_trigger_rcv_count_rst (config_client, service, chan, TRIGGER_IFACE_DFLT_RCV_RST);
+ client_err |= bpm_set_trigger_transm_count_rst (config_client, service, chan, TRIGGER_IFACE_DFLT_TRANSM_RST);
+ client_err |= bpm_set_trigger_rcv_len (config_client, service, chan, TRIGGER_IFACE_DFLT_RCV_LEN);
+ client_err |= bpm_set_trigger_transm_len (config_client, service, chan, TRIGGER_IFACE_DFLT_TRANSM_LEN);
+ }
+
+ ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could set trigger defaults",
+ err_param_set, SMIO_ERR_CONFIG_DFLT);
+
+err_param_set:
+ bpm_client_destroy (&config_client);
+err_alloc_client:
+ DBE_DEBUG (DBG_SM_IO | DBG_LVL_INFO, "[sm_io:trigger_iface_defaults] Exiting Config thread %s\n",
+ service);
+ return err;
+}
diff --git a/src/sm_io/modules/trigger_iface/sm_io_trigger_iface_defaults.h b/src/sm_io/modules/trigger_iface/sm_io_trigger_iface_defaults.h
new file mode 100644
index 0000000000000000000000000000000000000000..b4c6b17f4b3c5a6758159434dc91e2cd90f6491f
--- /dev/null
+++ b/src/sm_io/modules/trigger_iface/sm_io_trigger_iface_defaults.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2016 LNLS (www.lnls.br)
+ * Author: Lucas Russo <lucas.russo@lnls.br>
+ *
+ * Released according to the GNU GPL, version 3 or any later version.
+ */
+
+#ifndef _TRIGGER_IFACE_DEFAULTS_H_
+#define _TRIGGER_IFACE_DEFAULTS_H_
+
+#include "sm_io_err.h"
+
+#define TRIGGER_IFACE_DFLT_DIR 1 /* Input */
+#define TRIGGER_IFACE_DFLT_DIR_POL 1 /* Reversed polarity */
+#define TRIGGER_IFACE_DFLT_RCV_RST 1 /* Pulse Reset */
+#define TRIGGER_IFACE_DFLT_TRANSM_RST 1 /* Pulse Reset */
+#define TRIGGER_IFACE_DFLT_RCV_LEN 1 /* Debounce Length */
+#define TRIGGER_IFACE_DFLT_TRANSM_LEN 1 /* Pulse Extension Length */
+
+smio_err_e trigger_iface_config_defaults (char *broker_endp, char *service,
+ const char *log_file_name);
+
+#endif
+
diff --git a/src/sm_io/modules/trigger_iface/sm_io_trigger_iface_exp.c b/src/sm_io/modules/trigger_iface/sm_io_trigger_iface_exp.c
new file mode 100644
index 0000000000000000000000000000000000000000..23e4526152bcd9d736c61bb6c34bf1cca21b2767
--- /dev/null
+++ b/src/sm_io/modules/trigger_iface/sm_io_trigger_iface_exp.c
@@ -0,0 +1,278 @@
+/*
+ * Copyright (C) 2016 LNLS (www.lnls.br)
+ * Author: Lucas Russo <lucas.russo@lnls.br>
+ *
+ * Released according to the GNU GPL, version 3 or any later version.
+ */
+
+#include "bpm_server.h"
+/* Private headers */
+#include "sm_io_trigger_iface_codes.h"
+#include "sm_io_trigger_iface_defaults.h"
+#include "sm_io_trigger_iface_exports.h"
+#include "sm_io_trigger_iface_core.h"
+#include "sm_io_trigger_iface_exp.h"
+#include "hw/wb_trigger_iface_regs.h"
+
+/* Undef ASSERT_ALLOC to avoid conflicting with other ASSERT_ALLOC */
+#ifdef ASSERT_TEST
+#undef ASSERT_TEST
+#endif
+#define ASSERT_TEST(test_boolean, err_str, err_goto_label, /* err_core */ ...) \
+ ASSERT_HAL_TEST(test_boolean, SM_IO, "[sm_io:trigger_iface_exp]", \
+ err_str, err_goto_label, /* err_core */ __VA_ARGS__)
+
+#ifdef ASSERT_ALLOC
+#undef ASSERT_ALLOC
+#endif
+#define ASSERT_ALLOC(ptr, err_goto_label, /* err_core */ ...) \
+ ASSERT_HAL_ALLOC(ptr, SM_IO, "[sm_io:trigger_iface_exp]", \
+ smio_err_str(SMIO_ERR_ALLOC), \
+ err_goto_label, /* err_core */ __VA_ARGS__)
+
+#ifdef CHECK_ERR
+#undef CHECK_ERR
+#endif
+#define CHECK_ERR(err, err_type) \
+ CHECK_HAL_ERR(err, SM_IO, "[sm_io:trigger_iface_exp]", \
+ smio_err_str (err_type))
+
+/* This must match the FPGA maximum number of channels */
+#define TRIGGER_IFACE_NUM_CHAN 24
+#define TRIGGER_IFACE_CHAN_OFFSET 0x00c /* 3 32-bit registers */
+
+/*****************************************************************/
+/************ Specific TRIGGER INTERFACE Operations **************/
+/*****************************************************************/
+
+#define BPM_TRIGGER_IFACE_DIR_MIN 0 /* Bidirection Buffer set to Output */
+#define BPM_TRIGGER_IFACE_DIR_MAX 1 /* Bidirection Buffer set to Input */
+RW_PARAM_FUNC(trigger_iface, dir) {
+ SET_GET_PARAM_CHANNEL(trigger_iface, WB_TRIGGER_IFACE_RAW_REG_OFFS, WB_TRIG_IFACE,
+ CH0_CTL, DIR, TRIGGER_IFACE_CHAN_OFFSET, TRIGGER_IFACE_NUM_CHAN, SINGLE_BIT_PARAM,
+ BPM_TRIGGER_IFACE_DIR_MIN, BPM_TRIGGER_IFACE_DIR_MAX, NO_CHK_FUNC,
+ NO_FMT_FUNC, SET_FIELD);
+}
+
+#define BPM_TRIGGER_IFACE_DIR_POL_MIN 0 /* Direction polarity kept */
+#define BPM_TRIGGER_IFACE_DIR_POL_MAX 1 /* Direction polarity reversed */
+RW_PARAM_FUNC(trigger_iface, dir_pol) {
+ SET_GET_PARAM_CHANNEL(trigger_iface, WB_TRIGGER_IFACE_RAW_REG_OFFS, WB_TRIG_IFACE,
+ CH0_CTL, DIR_POL, TRIGGER_IFACE_CHAN_OFFSET, TRIGGER_IFACE_NUM_CHAN, SINGLE_BIT_PARAM,
+ BPM_TRIGGER_IFACE_DIR_POL_MIN, BPM_TRIGGER_IFACE_DIR_POL_MAX, NO_CHK_FUNC,
+ NO_FMT_FUNC, SET_FIELD);
+}
+
+#define BPM_TRIGGER_IFACE_RCV_COUNT_RST_MIN 0 /* Receive Counter Reset */
+#define BPM_TRIGGER_IFACE_RCV_COUNT_RST_MAX 1 /* Receive Counter Reset */
+RW_PARAM_FUNC(trigger_iface, rcv_count_rst) {
+ SET_GET_PARAM_CHANNEL(trigger_iface, WB_TRIGGER_IFACE_RAW_REG_OFFS, WB_TRIG_IFACE,
+ CH0_CTL, RCV_COUNT_RST, TRIGGER_IFACE_CHAN_OFFSET, TRIGGER_IFACE_NUM_CHAN, SINGLE_BIT_PARAM,
+ BPM_TRIGGER_IFACE_RCV_COUNT_RST_MIN, BPM_TRIGGER_IFACE_RCV_COUNT_RST_MAX, NO_CHK_FUNC,
+ NO_FMT_FUNC, SET_FIELD);
+}
+
+#define BPM_TRIGGER_IFACE_TRANSM_COUNT_RST_MIN 0 /* Transmit Counter Reset */
+#define BPM_TRIGGER_IFACE_TRANSM_COUNT_RST_MAX 1 /* Transmit Counter Reset */
+RW_PARAM_FUNC(trigger_iface, transm_count_rst) {
+ SET_GET_PARAM_CHANNEL(trigger_iface, WB_TRIGGER_IFACE_RAW_REG_OFFS, WB_TRIG_IFACE,
+ CH0_CTL, TRANSM_COUNT_RST, TRIGGER_IFACE_CHAN_OFFSET, TRIGGER_IFACE_NUM_CHAN, SINGLE_BIT_PARAM,
+ BPM_TRIGGER_IFACE_TRANSM_COUNT_RST_MIN, BPM_TRIGGER_IFACE_TRANSM_COUNT_RST_MAX, NO_CHK_FUNC,
+ NO_FMT_FUNC, SET_FIELD);
+}
+
+#define BPM_TRIGGER_IFACE_RCV_LEN_MIN 0 /* Receiver Debounce Length */
+#define BPM_TRIGGER_IFACE_RCV_LEN_MAX ((1 << 8) -1) /* Receiver Debounce Length */
+RW_PARAM_FUNC(trigger_iface, rcv_len) {
+ SET_GET_PARAM_CHANNEL(trigger_iface, WB_TRIGGER_IFACE_RAW_REG_OFFS, WB_TRIG_IFACE,
+ CH0_CFG, RCV_LEN, TRIGGER_IFACE_CHAN_OFFSET, TRIGGER_IFACE_NUM_CHAN, MULT_BIT_PARAM,
+ BPM_TRIGGER_IFACE_RCV_LEN_MIN, BPM_TRIGGER_IFACE_RCV_LEN_MAX, NO_CHK_FUNC,
+ NO_FMT_FUNC, SET_FIELD);
+}
+
+#define BPM_TRIGGER_IFACE_TRANSM_LEN_MIN 0 /* Receiver Debounce Length */
+#define BPM_TRIGGER_IFACE_TRANSM_LEN_MAX ((1 << 8) -1) /* Receiver Debounce Length */
+RW_PARAM_FUNC(trigger_iface, transm_len) {
+ SET_GET_PARAM_CHANNEL(trigger_iface, WB_TRIGGER_IFACE_RAW_REG_OFFS, WB_TRIG_IFACE,
+ CH0_CFG, TRANSM_LEN, TRIGGER_IFACE_CHAN_OFFSET, TRIGGER_IFACE_NUM_CHAN, MULT_BIT_PARAM,
+ /* no minimum value */, /* no maximum value */, NO_CHK_FUNC,
+ NO_FMT_FUNC, SET_FIELD);
+}
+
+RW_PARAM_FUNC(trigger_iface, count_rcv) {
+ SET_GET_PARAM_CHANNEL(trigger_iface, WB_TRIGGER_IFACE_RAW_REG_OFFS, WB_TRIG_IFACE,
+ CH0_COUNT, RCV, TRIGGER_IFACE_CHAN_OFFSET, TRIGGER_IFACE_NUM_CHAN, MULT_BIT_PARAM,
+ /* no minimum value */, /* no maximum value */, NO_CHK_FUNC,
+ NO_FMT_FUNC, SET_FIELD);
+}
+
+RW_PARAM_FUNC(trigger_iface, count_transm) {
+ SET_GET_PARAM_CHANNEL(trigger_iface, WB_TRIGGER_IFACE_RAW_REG_OFFS, WB_TRIG_IFACE,
+ CH0_COUNT, TRANSM, TRIGGER_IFACE_CHAN_OFFSET, TRIGGER_IFACE_NUM_CHAN, MULT_BIT_PARAM,
+ /* no minimum value */, /* no maximum value */, NO_CHK_FUNC,
+ NO_FMT_FUNC, SET_FIELD);
+}
+
+/* Exported function pointers */
+const disp_table_func_fp trigger_iface_exp_fp [] = {
+ RW_PARAM_FUNC_NAME(trigger_iface, dir),
+ RW_PARAM_FUNC_NAME(trigger_iface, dir_pol),
+ RW_PARAM_FUNC_NAME(trigger_iface, rcv_count_rst),
+ RW_PARAM_FUNC_NAME(trigger_iface, transm_count_rst),
+ RW_PARAM_FUNC_NAME(trigger_iface, rcv_len),
+ RW_PARAM_FUNC_NAME(trigger_iface, transm_len),
+ RW_PARAM_FUNC_NAME(trigger_iface, count_rcv),
+ RW_PARAM_FUNC_NAME(trigger_iface, count_transm),
+ NULL
+};
+
+/************************************************************/
+/***************** Export methods functions *****************/
+/************************************************************/
+
+static smio_err_e _trigger_iface_do_op (void *owner, void *msg);
+
+/* Attach an instance of sm_io to dev_io function pointer */
+smio_err_e trigger_iface_attach (smio_t *self, devio_t *parent)
+{
+ (void) self;
+ (void) parent;
+ return SMIO_ERR_FUNC_NOT_IMPL;
+}
+
+/* Deattach an instance of sm_io to dev_io function pointer */
+smio_err_e trigger_iface_deattach (smio_t *self)
+{
+ (void) self;
+ return SMIO_ERR_FUNC_NOT_IMPL;
+}
+
+/* Export (register) sm_io to handle operations function pointer */
+smio_err_e trigger_iface_export_ops (smio_t *self,
+ const disp_op_t** smio_exp_ops)
+{
+ (void) self;
+ (void) smio_exp_ops;
+ return SMIO_ERR_FUNC_NOT_IMPL;
+}
+
+/* Unexport (unregister) sm_io to handle operations function pointer */
+smio_err_e trigger_iface_unexport_ops (smio_t *self)
+{
+ (void) self;
+ return SMIO_ERR_FUNC_NOT_IMPL;
+}
+
+
+/* Generic wrapper for receiving opcodes and arguments to specific funtions function pointer */
+/* FIXME: Code repetition! _devio_do_smio_op () function does almost the same!!! */
+smio_err_e _trigger_iface_do_op (void *owner, void *msg)
+{
+ (void) owner;
+ (void) msg;
+ return SMIO_ERR_FUNC_NOT_IMPL;
+}
+
+smio_err_e trigger_iface_do_op (void *self, void *msg)
+{
+ return _trigger_iface_do_op (self, msg);
+}
+
+const smio_ops_t trigger_iface_ops = {
+ .attach = trigger_iface_attach, /* Attach sm_io instance to dev_io */
+ .deattach = trigger_iface_deattach, /* Deattach sm_io instance to dev_io */
+ .export_ops = trigger_iface_export_ops, /* Export sm_io operations to dev_io */
+ .unexport_ops = trigger_iface_unexport_ops, /* Unexport sm_io operations to dev_io */
+ .do_op = trigger_iface_do_op /* Generic wrapper for handling specific operations */
+};
+
+/************************************************************/
+/****************** Bootstrap Operations ********************/
+/************************************************************/
+
+smio_err_e trigger_iface_init (smio_t * self)
+{
+ DBE_DEBUG (DBG_SM_IO | DBG_LVL_TRACE, "[sm_io:trigger_iface_exp] Initializing trigger_iface\n");
+
+ smio_err_e err = SMIO_SUCCESS;
+
+ err = smio_set_id (self, TRIGGER_IFACE_SDB_DEVID);
+ ASSERT_TEST(err == SMIO_SUCCESS, "Could not set SMIO id", err_set_id);
+ err = smio_set_name (self, TRIGGER_IFACE_SDB_NAME);
+ ASSERT_TEST(err == SMIO_SUCCESS, "Could not set SMIO name", err_set_name);
+
+ /* Set SMIO ops pointers */
+ err = smio_set_ops (self, &trigger_iface_ops);
+ ASSERT_TEST(err == SMIO_SUCCESS, "Could not set SMIO operations",
+ err_smio_set_ops);
+ err = smio_set_thsafe_client_ops (self, &smio_thsafe_client_zmq_ops);
+ ASSERT_TEST(err == SMIO_SUCCESS, "Could not set SMIO thsafe operations",
+ err_smio_set_thsafe_ops);
+
+ /* Fill the disp_op_t description structure with the callbacks. */
+
+ /* disp_op_t structure is const and all of the functions performing on it
+ * obviously receives a const argument, but here (and only on the SMIO
+ * initialization) we need to make an exception if we want to keep the
+ * functions' description and the function pointers separate */
+ err = smio_init_exp_ops (self, (disp_op_t **) trigger_iface_exp_ops,
+ trigger_iface_exp_fp);
+ ASSERT_TEST(err == SMIO_SUCCESS, "Could not fill SMIO "
+ "function descriptors with the callbacks", err_fill_desc);
+
+ err = smio_set_exp_ops (self, trigger_iface_exp_ops);
+ ASSERT_TEST(err == SMIO_SUCCESS, "Could not set SMIO exported operations",
+ err_smio_set_exp_ops);
+
+ /* Initialize specific structure */
+ smio_trigger_iface_t *smio_handler = smio_trigger_iface_new (self);
+ ASSERT_ALLOC(smio_handler, err_smio_handler_alloc, SMIO_ERR_ALLOC);
+ err = smio_set_handler (self, smio_handler);
+ ASSERT_TEST(err == SMIO_SUCCESS, "Could not set SMIO handler",
+ err_smio_set_handler);
+
+ return err;
+
+err_smio_set_handler:
+ smio_trigger_iface_destroy (&smio_handler);
+err_smio_handler_alloc:
+ smio_set_exp_ops (self, NULL);
+err_smio_set_exp_ops:
+err_fill_desc:
+ smio_set_thsafe_client_ops (self, NULL);
+err_smio_set_thsafe_ops:
+ smio_set_ops (self, NULL);
+err_smio_set_ops:
+err_set_name:
+err_set_id:
+ return err;
+}
+
+/* Destroy sm_io instance of trigger_iface */
+smio_err_e trigger_iface_shutdown (smio_t *self)
+{
+ DBE_DEBUG (DBG_SM_IO | DBG_LVL_TRACE, "[sm_io:trigger_iface_exp] Shutting down trigger_iface\n");
+
+ smio_err_e err = SMIO_SUCCESS;
+ smio_trigger_iface_t *trig_iface = smio_get_handler (self);
+ ASSERT_TEST(trig_iface != NULL, "Could not get trig_iface handler",
+ err_trig_iface_handler, SMIO_ERR_ALLOC /* FIXME: improve return code */);
+
+ /* Destroy SMIO instance */
+ smio_trigger_iface_destroy (&trig_iface);
+ /* Nullify operation pointers */
+ smio_set_exp_ops (self, NULL);
+ smio_set_thsafe_client_ops (self, NULL);
+ smio_set_ops (self, NULL);
+
+err_trig_iface_handler:
+ return err;
+}
+
+const smio_bootstrap_ops_t trigger_iface_bootstrap_ops = {
+ .init = trigger_iface_init,
+ .shutdown = trigger_iface_shutdown,
+ .config_defaults = trigger_iface_config_defaults
+};
+
+SMIO_MOD_DECLARE(TRIGGER_IFACE_SDB_DEVID, TRIGGER_IFACE_SDB_NAME, trigger_iface_bootstrap_ops)
diff --git a/src/sm_io/modules/trigger_iface/sm_io_trigger_iface_exp.h b/src/sm_io/modules/trigger_iface/sm_io_trigger_iface_exp.h
new file mode 100644
index 0000000000000000000000000000000000000000..12f381da86dd1025cdfbd2aef56233b29bd57e7b
--- /dev/null
+++ b/src/sm_io/modules/trigger_iface/sm_io_trigger_iface_exp.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2016 LNLS (www.lnls.br)
+ * Author: Lucas Russo <lucas.russo@lnls.br>
+ *
+ * Released according to the GNU GPL, version 3 or any later version.
+ */
+
+#ifndef _TRIGGER_IFACE_H_
+#define _TRIGGER_IFACE_H_
+
+/* Known modules IDs (from SDB records defined in FPGA) */
+#define TRIGGER_IFACE_SDB_DEVID 0xbcbb78d2
+#define TRIGGER_IFACE_SDB_NAME "TRIGGER_IFACE"
+
+extern const smio_bootstrap_ops_t trigger_iface_bootstrap_ops;
+
+#endif
+
diff --git a/src/sm_io/modules/trigger_iface/sm_io_trigger_iface_exports.c b/src/sm_io/modules/trigger_iface/sm_io_trigger_iface_exports.c
new file mode 100644
index 0000000000000000000000000000000000000000..e8b638c10a4cf8ed9a81921e89d0afa40318caf8
--- /dev/null
+++ b/src/sm_io/modules/trigger_iface/sm_io_trigger_iface_exports.c
@@ -0,0 +1,129 @@
+/*
+ * Copyright (C) 2016 LNLS (www.lnls.br)
+ * Author: Lucas Russo <lucas.russo@lnls.br>
+ *
+ * Released according to the GNU GPL, version 3 or any later version.
+ */
+
+#include "sm_io_exports_helper.h"
+#include "sm_io_codes.h"
+
+/* Description SMIO TRIGGER_IFACE functions */
+
+disp_op_t trigger_iface_dir_exp = {
+ .name = TRIGGER_IFACE_NAME_DIR,
+ .opcode = TRIGGER_IFACE_OPCODE_DIR,
+ .retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ .retval_owner = DISP_OWNER_OTHER,
+ .args = {
+ DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ DISP_ARG_END
+ }
+};
+
+disp_op_t trigger_iface_dir_pol_exp = {
+ .name = TRIGGER_IFACE_NAME_DIR_POL,
+ .opcode = TRIGGER_IFACE_OPCODE_DIR_POL,
+ .retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ .retval_owner = DISP_OWNER_OTHER,
+ .args = {
+ DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ DISP_ARG_END
+ }
+};
+
+disp_op_t trigger_iface_rcv_count_rst_exp = {
+ .name = TRIGGER_IFACE_NAME_RCV_COUNT_RST,
+ .opcode = TRIGGER_IFACE_OPCODE_RCV_COUNT_RST,
+ .retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ .retval_owner = DISP_OWNER_OTHER,
+ .args = {
+ DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ DISP_ARG_END
+ }
+};
+
+disp_op_t trigger_iface_transm_count_rst_exp = {
+ .name = TRIGGER_IFACE_NAME_TRANSM_COUNT_RST,
+ .opcode = TRIGGER_IFACE_OPCODE_TRANSM_COUNT_RST,
+ .retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ .retval_owner = DISP_OWNER_OTHER,
+ .args = {
+ DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ DISP_ARG_END
+ }
+};
+
+disp_op_t trigger_iface_rcv_len_exp = {
+ .name = TRIGGER_IFACE_NAME_RCV_LEN,
+ .opcode = TRIGGER_IFACE_OPCODE_RCV_LEN,
+ .retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ .retval_owner = DISP_OWNER_OTHER,
+ .args = {
+ DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ DISP_ARG_END
+ }
+};
+
+disp_op_t trigger_iface_transm_len_exp = {
+ .name = TRIGGER_IFACE_NAME_TRANSM_LEN,
+ .opcode = TRIGGER_IFACE_OPCODE_TRANSM_LEN,
+ .retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ .retval_owner = DISP_OWNER_OTHER,
+ .args = {
+ DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ DISP_ARG_END
+ }
+};
+
+disp_op_t trigger_iface_count_rcv_exp = {
+ .name = TRIGGER_IFACE_NAME_COUNT_RCV,
+ .opcode = TRIGGER_IFACE_OPCODE_COUNT_RCV,
+ .retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ .retval_owner = DISP_OWNER_OTHER,
+ .args = {
+ DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ DISP_ARG_END
+ }
+};
+
+disp_op_t trigger_iface_count_transm_exp = {
+ .name = TRIGGER_IFACE_NAME_COUNT_TRANSM,
+ .opcode = TRIGGER_IFACE_OPCODE_COUNT_TRANSM,
+ .retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ .retval_owner = DISP_OWNER_OTHER,
+ .args = {
+ DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ DISP_ARG_END
+ }
+};
+
+/* Exported function description */
+const disp_op_t *trigger_iface_exp_ops [] = {
+ &trigger_iface_dir_exp,
+ &trigger_iface_dir_pol_exp,
+ &trigger_iface_rcv_count_rst_exp,
+ &trigger_iface_transm_count_rst_exp,
+ &trigger_iface_rcv_len_exp,
+ &trigger_iface_transm_len_exp,
+ &trigger_iface_count_rcv_exp,
+ &trigger_iface_count_transm_exp,
+ NULL
+};
+
diff --git a/src/sm_io/modules/trigger_iface/sm_io_trigger_iface_exports.h b/src/sm_io/modules/trigger_iface/sm_io_trigger_iface_exports.h
new file mode 100644
index 0000000000000000000000000000000000000000..597adaed81e63e35299f2480b0dfef6f9febd314
--- /dev/null
+++ b/src/sm_io/modules/trigger_iface/sm_io_trigger_iface_exports.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2016 LNLS (www.lnls.br)
+ * Author: Lucas Russo <lucas.russo@lnls.br>
+ *
+ * Released according to the GNU GPL, version 3 or any later version.
+ */
+
+#ifndef _SM_IO_TRIGGER_IFACE_EXPORTS_H_
+#define _SM_IO_TRIGGER_IFACE_EXPORTS_H_
+
+#include "disptable.h"
+
+extern disp_op_t trigger_iface_dir_exp;
+extern disp_op_t trigger_iface_dir_pol_exp;
+extern disp_op_t trigger_iface_rcv_count_rst_exp;
+extern disp_op_t trigger_iface_transm_count_rst_exp;
+extern disp_op_t trigger_iface_rcv_len_exp;
+extern disp_op_t trigger_iface_transm_len_exp;
+extern disp_op_t trigger_iface_count_rcv_exp;
+extern disp_op_t trigger_iface_count_transm_exp;
+
+extern const disp_op_t *trigger_iface_exp_ops [];
+
+#endif
+
diff --git a/src/sm_io/modules/trigger_iface/trigger_iface.mk b/src/sm_io/modules/trigger_iface/trigger_iface.mk
new file mode 100644
index 0000000000000000000000000000000000000000..1f3140fb6a96a169e4699fdb7419a9f1bb620548
--- /dev/null
+++ b/src/sm_io/modules/trigger_iface/trigger_iface.mk
@@ -0,0 +1,6 @@
+sm_io_trigger_iface_DIR = $(SRC_DIR)/sm_io/modules/trigger_iface
+
+sm_io_trigger_iface_OBJS = $(sm_io_trigger_iface_DIR)/sm_io_trigger_iface_core.o \
+ $(sm_io_trigger_iface_DIR)/sm_io_trigger_iface_exp.o \
+ $(sm_io_trigger_iface_DIR)/sm_io_trigger_iface_exports.o \
+ $(sm_io_trigger_iface_DIR)/sm_io_trigger_iface_defaults.o
diff --git a/src/sm_io/modules/trigger_mux/sm_io_trigger_mux_codes.h b/src/sm_io/modules/trigger_mux/sm_io_trigger_mux_codes.h
new file mode 100644
index 0000000000000000000000000000000000000000..8dc3576cb593f173d1de7c2708c037637f13c13b
--- /dev/null
+++ b/src/sm_io/modules/trigger_mux/sm_io_trigger_mux_codes.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2016 LNLS (www.lnls.br)
+ * Author: Lucas Russo <lucas.russo@lnls.br>
+ *
+ * Released according to the GNU GPL, version 3 or any later version.
+ */
+
+#ifndef _SM_IO_TRIGGER_MUX_CODES_H_
+#define _SM_IO_TRIGGER_MUX_CODES_H_
+
+/* Messaging OPCODES */
+#define TRIGGER_MUX_OPCODE_TYPE uint32_t
+#define TRIGGER_MUX_OPCODE_SIZE (sizeof (TRIGGER_MUX_OPCODE_TYPE))
+
+#define TRIGGER_MUX_OPCODE_RCV_SRC 0
+#define TRIGGER_MUX_NAME_RCV_SRC "trigger_mux_rcv_src"
+#define TRIGGER_MUX_OPCODE_RCV_IN_SEL 1
+#define TRIGGER_MUX_NAME_RCV_IN_SEL "trigger_mux_rcv_in_sel"
+#define TRIGGER_MUX_OPCODE_TRANSM_SRC 2
+#define TRIGGER_MUX_NAME_TRANSM_SRC "trigger_mux_transm_src"
+#define TRIGGER_MUX_OPCODE_TRANSM_OUT_SEL 3
+#define TRIGGER_MUX_NAME_TRANSM_OUT_SEL "trigger_mux_transm_out_sel"
+#define TRIGGER_MUX_OPCODE_END 4
+
+/* Messaging Reply OPCODES */
+#define TRIGGER_MUX_REPLY_TYPE uint32_t
+#define TRIGGER_MUX_REPLY_SIZE (sizeof (TRIGGER_MUX_REPLY_TYPE))
+
+#define TRIGGER_MUX_OK 0 /* Operation was successful */
+#define TRIGGER_MUX_ERR 1 /* Could not set/get value */
+#define TRIGGER_MUX_UNINPL 2 /* Unimplemented function or operation */
+#define TRIGGER_MUX_REPLY_END 3 /* End marker */
+
+#endif
diff --git a/src/sm_io/modules/trigger_mux/sm_io_trigger_mux_core.c b/src/sm_io/modules/trigger_mux/sm_io_trigger_mux_core.c
new file mode 100644
index 0000000000000000000000000000000000000000..c45c64d807700b138a5da7c76272c41820f155d4
--- /dev/null
+++ b/src/sm_io/modules/trigger_mux/sm_io_trigger_mux_core.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2016 LNLS (www.lnls.br)
+ * Author: Lucas Russo <lucas.russo@lnls.br>
+ *
+ * Released according to the GNU GPL, version 3 or any later version.
+ */
+
+#include "bpm_server.h"
+/* Private headers */
+#include "sm_io_trigger_mux_defaults.h"
+#include "sm_io_trigger_mux_core.h"
+
+/* Undef ASSERT_ALLOC to avoid conflicting with other ASSERT_ALLOC */
+#ifdef ASSERT_TEST
+#undef ASSERT_TEST
+#endif
+#define ASSERT_TEST(test_boolean, err_str, err_goto_label, /* err_core */ ...) \
+ ASSERT_HAL_TEST(test_boolean, SM_IO, "[sm_io_trigger_mux_core]", \
+ err_str, err_goto_label, /* err_core */ __VA_ARGS__)
+
+#ifdef ASSERT_ALLOC
+#undef ASSERT_ALLOC
+#endif
+#define ASSERT_ALLOC(ptr, err_goto_label, /* err_core */ ...) \
+ ASSERT_HAL_ALLOC(ptr, SM_IO, "[sm_io_trigger_mux_core]", \
+ smio_err_str(SMIO_ERR_ALLOC), \
+ err_goto_label, /* err_core */ __VA_ARGS__)
+
+#ifdef CHECK_ERR
+#undef CHECK_ERR
+#endif
+#define CHECK_ERR(err, err_type) \
+ CHECK_HAL_ERR(err, SM_IO, "[sm_io_trigger_mux_core]", \
+ smio_err_str (err_type))
+
+/* Creates a new instance of Device Information */
+smio_trigger_mux_t * smio_trigger_mux_new (smio_t *parent)
+{
+ (void) parent;
+
+ smio_trigger_mux_t *self = (smio_trigger_mux_t *) zmalloc (sizeof *self);
+ ASSERT_ALLOC(self, err_self_alloc);
+
+ return self;
+
+err_self_alloc:
+ return NULL;
+}
+
+/* Destroy an instance of the Device Information */
+smio_err_e smio_trigger_mux_destroy (smio_trigger_mux_t **self_p)
+{
+ assert (self_p);
+
+ if (*self_p) {
+ smio_trigger_mux_t *self = *self_p;
+
+ free (self);
+ *self_p = NULL;
+ }
+
+ return SMIO_SUCCESS;
+}
+
diff --git a/src/sm_io/modules/trigger_mux/sm_io_trigger_mux_core.h b/src/sm_io/modules/trigger_mux/sm_io_trigger_mux_core.h
new file mode 100644
index 0000000000000000000000000000000000000000..a243b9d22f4ad529b4b15dc2dfd80a80daea5a15
--- /dev/null
+++ b/src/sm_io/modules/trigger_mux/sm_io_trigger_mux_core.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2016 LNLS (www.lnls.br)
+ * Author: Lucas Russo <lucas.russo@lnls.br>
+ *
+ * Released according to the GNU GPL, version 3 or any later version.
+*/
+
+#ifndef _SM_IO_TRIGGER_MUX_CORE_H_
+#define _SM_IO_TRIGGER_MUX_CORE_H_
+
+typedef struct {
+ const uint32_t example;
+} smio_trigger_mux_t;
+
+/***************** Our methods *****************/
+
+/* Creates a new instance of the smio realization */
+smio_trigger_mux_t * smio_trigger_mux_new (smio_t *parent);
+/* Destroys the smio realizationn */
+smio_err_e smio_trigger_mux_destroy (smio_trigger_mux_t **self_p);
+
+#endif
diff --git a/src/sm_io/modules/trigger_mux/sm_io_trigger_mux_defaults.c b/src/sm_io/modules/trigger_mux/sm_io_trigger_mux_defaults.c
new file mode 100644
index 0000000000000000000000000000000000000000..3730e5b8bb574f9a1c4c829efce6aea926b15d3e
--- /dev/null
+++ b/src/sm_io/modules/trigger_mux/sm_io_trigger_mux_defaults.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) 2016 LNLS (www.lnls.br)
+ * Author: Lucas Russo <lucas.russo@lnls.br>
+ *
+ * Released according to the GNU GPL, version 3 or any later version.
+ */
+
+#include "bpm_server.h"
+/* Private headers */
+#include "sm_io_trigger_mux_defaults.h"
+
+/* Undef ASSERT_ALLOC to avoid conflicting with other ASSERT_ALLOC */
+#ifdef ASSERT_TEST
+#undef ASSERT_TEST
+#endif
+#define ASSERT_TEST(test_boolean, err_str, err_goto_label, /* err_core */ ...) \
+ ASSERT_HAL_TEST(test_boolean, SM_IO, "[sm_io:trigger_mux_defaults]", \
+ err_str, err_goto_label, /* err_core */ __VA_ARGS__)
+
+#ifdef ASSERT_ALLOC
+#undef ASSERT_ALLOC
+#endif
+#define ASSERT_ALLOC(ptr, err_goto_label, /* err_core */ ...) \
+ ASSERT_HAL_ALLOC(ptr, SM_IO, "[sm_io:trigger_mux_defaults]", \
+ smio_err_str(SMIO_ERR_ALLOC), \
+ err_goto_label, /* err_core */ __VA_ARGS__)
+
+#ifdef CHECK_ERR
+#undef CHECK_ERR
+#endif
+#define CHECK_ERR(err, err_type) \
+ CHECK_HAL_ERR(err, SM_IO, "[sm_io:trigger_mux_defaults]", \
+ smio_err_str (err_type))
+
+#define SMIO_TRIGGER_MUX_LIBBPMCLIENT_LOG_MODE "a"
+#define SMIO_TRIGGER_MUX_MAX_CHAN 24
+
+/* We use the actual libclient to send and configure our default values,
+ * maintaining internal consistency. So, in fact, we are sending ourselves
+ * a message containing the default values. Because of this approach, we
+ * only get to default our values when the functions are already exported
+ * to the broker, which happens on a late stage. This could cause a fast
+ * client to get an inconsistent state from our server */
+/* TODO: Avoid exporting the functions before we have initialized
+ * our server with the default values */
+smio_err_e trigger_mux_config_defaults (char *broker_endp, char *service,
+ const char *log_file_name)
+{
+ (void) log_file_name;
+ DBE_DEBUG (DBG_SM_IO | DBG_LVL_INFO, "[sm_io:trigger_mux_defaults] Configuring SMIO "
+ "TRIGGER_MUX with default values ...\n");
+ bpm_client_err_e client_err = BPM_CLIENT_SUCCESS;
+ smio_err_e err = SMIO_SUCCESS;
+
+ bpm_client_t *config_client = bpm_client_new_log_mode (broker_endp, 0,
+ log_file_name, SMIO_TRIGGER_MUX_LIBBPMCLIENT_LOG_MODE);
+ ASSERT_ALLOC(config_client, err_alloc_client);
+
+ uint32_t chan;
+ for (chan = 0; chan < SMIO_TRIGGER_MUX_MAX_CHAN; ++chan) {
+ client_err = bpm_set_trigger_rcv_src (config_client, service, chan, TRIGGER_MUX_DFLT_RCV_SRC);
+ client_err |= bpm_set_trigger_rcv_in_sel (config_client, service, chan, TRIGGER_MUX_DFLT_RCV_IN_SEL);
+ client_err |= bpm_set_trigger_transm_src (config_client, service, chan, TRIGGER_MUX_DFLT_TRANSM_SRC);
+ client_err |= bpm_set_trigger_transm_out_sel (config_client, service, chan, TRIGGER_MUX_DFLT_TRANSM_IN_SEL);
+ }
+
+ ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could set trigger mux defaults",
+ err_param_set, SMIO_ERR_CONFIG_DFLT);
+
+err_param_set:
+ bpm_client_destroy (&config_client);
+err_alloc_client:
+ DBE_DEBUG (DBG_SM_IO | DBG_LVL_INFO, "[sm_io:trigger_mux_defaults] Exiting Config thread %s\n",
+ service);
+ return err;
+}
diff --git a/src/sm_io/modules/trigger_mux/sm_io_trigger_mux_defaults.h b/src/sm_io/modules/trigger_mux/sm_io_trigger_mux_defaults.h
new file mode 100644
index 0000000000000000000000000000000000000000..db6e6e16f9b7cde01286da388cd7abc3764a60c1
--- /dev/null
+++ b/src/sm_io/modules/trigger_mux/sm_io_trigger_mux_defaults.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2016 LNLS (www.lnls.br)
+ * Author: Lucas Russo <lucas.russo@lnls.br>
+ *
+ * Released according to the GNU GPL, version 3 or any later version.
+ */
+
+#ifndef _TRIGGER_MUX_DEFAULTS_H_
+#define _TRIGGER_MUX_DEFAULTS_H_
+
+#include "sm_io_err.h"
+
+#define TRIGGER_MUX_DFLT_RCV_SRC 0 /* Trigger Backplane */
+#define TRIGGER_MUX_DFLT_RCV_IN_SEL 0 /* Trigger Index 0 */
+#define TRIGGER_MUX_DFLT_TRANSM_SRC 0 /* Trigger Backplane */
+#define TRIGGER_MUX_DFLT_TRANSM_IN_SEL 0 /* Trigger Index 0 */
+
+smio_err_e trigger_mux_config_defaults (char *broker_endp, char *service,
+ const char *log_file_name);
+
+#endif
+
diff --git a/src/sm_io/modules/trigger_mux/sm_io_trigger_mux_exp.c b/src/sm_io/modules/trigger_mux/sm_io_trigger_mux_exp.c
new file mode 100644
index 0000000000000000000000000000000000000000..a57ecb9ba6c2fff1ce8cb814b57c6f6d9a73c8ed
--- /dev/null
+++ b/src/sm_io/modules/trigger_mux/sm_io_trigger_mux_exp.c
@@ -0,0 +1,242 @@
+/*
+ * Copyright (C) 2016 LNLS (www.lnls.br)
+ * Author: Lucas Russo <lucas.russo@lnls.br>
+ *
+ * Released according to the GNU GPL, version 3 or any later version.
+ */
+
+#include "bpm_server.h"
+/* Private headers */
+#include "sm_io_trigger_mux_codes.h"
+#include "sm_io_trigger_mux_defaults.h"
+#include "sm_io_trigger_mux_exports.h"
+#include "sm_io_trigger_mux_core.h"
+#include "sm_io_trigger_mux_exp.h"
+#include "hw/wb_trigger_mux_regs.h"
+
+/* Undef ASSERT_ALLOC to avoid conflicting with other ASSERT_ALLOC */
+#ifdef ASSERT_TEST
+#undef ASSERT_TEST
+#endif
+#define ASSERT_TEST(test_boolean, err_str, err_goto_label, /* err_core */ ...) \
+ ASSERT_HAL_TEST(test_boolean, SM_IO, "[sm_io:trigger_mux_exp]", \
+ err_str, err_goto_label, /* err_core */ __VA_ARGS__)
+
+#ifdef ASSERT_ALLOC
+#undef ASSERT_ALLOC
+#endif
+#define ASSERT_ALLOC(ptr, err_goto_label, /* err_core */ ...) \
+ ASSERT_HAL_ALLOC(ptr, SM_IO, "[sm_io:trigger_mux_exp]", \
+ smio_err_str(SMIO_ERR_ALLOC), \
+ err_goto_label, /* err_core */ __VA_ARGS__)
+
+#ifdef CHECK_ERR
+#undef CHECK_ERR
+#endif
+#define CHECK_ERR(err, err_type) \
+ CHECK_HAL_ERR(err, SM_IO, "[sm_io:trigger_mux_exp]", \
+ smio_err_str (err_type))
+
+/* This must match the FPGA maximum number of channels */
+#define TRIGGER_MUX_NUM_CHAN 24
+#define TRIGGER_MUX_CHAN_OFFSET 0x008 /* 2 32-bit registers */
+
+/*****************************************************************/
+/************ Specific TRIGGER MUX Operations **************/
+/*****************************************************************/
+
+#define BPM_TRIGGER_MUX_RCV_SRC_MIN 0 /* Trigger Source Selection (= Trigger Backplane) */
+#define BPM_TRIGGER_MUX_RCV_SRC_MAX 1 /* Trigger Source Selection (= FPGA internal) */
+RW_PARAM_FUNC(trigger_mux, rcv_src) {
+ SET_GET_PARAM_CHANNEL(trigger_mux, WB_TRIGGER_MUX_RAW_REG_OFFS, WB_TRIG_MUX,
+ CH0_CTL, RCV_SRC, TRIGGER_MUX_CHAN_OFFSET, TRIGGER_MUX_NUM_CHAN, SINGLE_BIT_PARAM,
+ BPM_TRIGGER_MUX_RCV_SRC_MIN, BPM_TRIGGER_MUX_RCV_SRC_MAX, NO_CHK_FUNC,
+ NO_FMT_FUNC, SET_FIELD);
+}
+
+#define BPM_TRIGGER_MUX_RCV_IN_SEL_MIN 0 /* Minimum selection */
+#define BPM_TRIGGER_MUX_RCV_IN_SEL_MAX ((1 << 8) -1) /* Maximum selection */
+RW_PARAM_FUNC(trigger_mux, rcv_in_sel) {
+ SET_GET_PARAM_CHANNEL(trigger_mux, WB_TRIGGER_MUX_RAW_REG_OFFS, WB_TRIG_MUX,
+ CH0_CTL, RCV_IN_SEL, TRIGGER_MUX_CHAN_OFFSET, TRIGGER_MUX_NUM_CHAN, MULT_BIT_PARAM,
+ BPM_TRIGGER_MUX_RCV_IN_SEL_MIN, BPM_TRIGGER_MUX_RCV_IN_SEL_MAX, NO_CHK_FUNC,
+ NO_FMT_FUNC, SET_FIELD);
+}
+
+#define BPM_TRIGGER_MUX_TRANSM_SRC_MIN 0 /* Trigger Source Selection (= Trigger Backplane) */
+#define BPM_TRIGGER_MUX_TRANSM_SRC_MAX 1 /* Trigger Source Selection (= FPGA internal) */
+RW_PARAM_FUNC(trigger_mux, transm_src) {
+ SET_GET_PARAM_CHANNEL(trigger_mux, WB_TRIGGER_MUX_RAW_REG_OFFS, WB_TRIG_MUX,
+ CH0_CTL, TRANSM_SRC, TRIGGER_MUX_CHAN_OFFSET, TRIGGER_MUX_NUM_CHAN, SINGLE_BIT_PARAM,
+ BPM_TRIGGER_MUX_TRANSM_SRC_MIN, BPM_TRIGGER_MUX_TRANSM_SRC_MAX, NO_CHK_FUNC,
+ NO_FMT_FUNC, SET_FIELD);
+}
+
+#define BPM_TRIGGER_MUX_TRANSM_OUT_SEL_MIN 0 /* Minimum selection */
+#define BPM_TRIGGER_MUX_TRANSM_OUT_SEL_MAX ((1 << 8) -1) /* Maximum selection */
+RW_PARAM_FUNC(trigger_mux, transm_out_sel) {
+ SET_GET_PARAM_CHANNEL(trigger_mux, WB_TRIGGER_MUX_RAW_REG_OFFS, WB_TRIG_MUX,
+ CH0_CTL, TRANSM_OUT_SEL, TRIGGER_MUX_CHAN_OFFSET, TRIGGER_MUX_NUM_CHAN, MULT_BIT_PARAM,
+ BPM_TRIGGER_MUX_TRANSM_OUT_SEL_MIN, BPM_TRIGGER_MUX_TRANSM_OUT_SEL_MAX, NO_CHK_FUNC,
+ NO_FMT_FUNC, SET_FIELD);
+}
+
+/* Exported function pointers */
+const disp_table_func_fp trigger_mux_exp_fp [] = {
+ RW_PARAM_FUNC_NAME(trigger_mux, rcv_src),
+ RW_PARAM_FUNC_NAME(trigger_mux, rcv_in_sel),
+ RW_PARAM_FUNC_NAME(trigger_mux, transm_src),
+ RW_PARAM_FUNC_NAME(trigger_mux, transm_out_sel),
+ NULL
+};
+
+/************************************************************/
+/***************** Export methods functions *****************/
+/************************************************************/
+
+static smio_err_e _trigger_mux_do_op (void *owner, void *msg);
+
+/* Attach an instance of sm_io to dev_io function pointer */
+smio_err_e trigger_mux_attach (smio_t *self, devio_t *parent)
+{
+ (void) self;
+ (void) parent;
+ return SMIO_ERR_FUNC_NOT_IMPL;
+}
+
+/* Deattach an instance of sm_io to dev_io function pointer */
+smio_err_e trigger_mux_deattach (smio_t *self)
+{
+ (void) self;
+ return SMIO_ERR_FUNC_NOT_IMPL;
+}
+
+/* Export (register) sm_io to handle operations function pointer */
+smio_err_e trigger_mux_export_ops (smio_t *self,
+ const disp_op_t** smio_exp_ops)
+{
+ (void) self;
+ (void) smio_exp_ops;
+ return SMIO_ERR_FUNC_NOT_IMPL;
+}
+
+/* Unexport (unregister) sm_io to handle operations function pointer */
+smio_err_e trigger_mux_unexport_ops (smio_t *self)
+{
+ (void) self;
+ return SMIO_ERR_FUNC_NOT_IMPL;
+}
+
+
+/* Generic wrapper for receiving opcodes and arguments to specific funtions function pointer */
+/* FIXME: Code repetition! _devio_do_smio_op () function does almost the same!!! */
+smio_err_e _trigger_mux_do_op (void *owner, void *msg)
+{
+ (void) owner;
+ (void) msg;
+ return SMIO_ERR_FUNC_NOT_IMPL;
+}
+
+smio_err_e trigger_mux_do_op (void *self, void *msg)
+{
+ return _trigger_mux_do_op (self, msg);
+}
+
+const smio_ops_t trigger_mux_ops = {
+ .attach = trigger_mux_attach, /* Attach sm_io instance to dev_io */
+ .deattach = trigger_mux_deattach, /* Deattach sm_io instance to dev_io */
+ .export_ops = trigger_mux_export_ops, /* Export sm_io operations to dev_io */
+ .unexport_ops = trigger_mux_unexport_ops, /* Unexport sm_io operations to dev_io */
+ .do_op = trigger_mux_do_op /* Generic wrapper for handling specific operations */
+};
+
+/************************************************************/
+/****************** Bootstrap Operations ********************/
+/************************************************************/
+
+smio_err_e trigger_mux_init (smio_t * self)
+{
+ DBE_DEBUG (DBG_SM_IO | DBG_LVL_TRACE, "[sm_io:trigger_mux_exp] Initializing trigger_mux\n");
+
+ smio_err_e err = SMIO_SUCCESS;
+
+ err = smio_set_id (self, TRIGGER_MUX_SDB_DEVID);
+ ASSERT_TEST(err == SMIO_SUCCESS, "Could not set SMIO id", err_set_id);
+ err = smio_set_name (self, TRIGGER_MUX_SDB_NAME);
+ ASSERT_TEST(err == SMIO_SUCCESS, "Could not set SMIO name", err_set_name);
+
+ /* Set SMIO ops pointers */
+ err = smio_set_ops (self, &trigger_mux_ops);
+ ASSERT_TEST(err == SMIO_SUCCESS, "Could not set SMIO operations",
+ err_smio_set_ops);
+ err = smio_set_thsafe_client_ops (self, &smio_thsafe_client_zmq_ops);
+ ASSERT_TEST(err == SMIO_SUCCESS, "Could not set SMIO thsafe operations",
+ err_smio_set_thsafe_ops);
+
+ /* Fill the disp_op_t description structure with the callbacks. */
+
+ /* disp_op_t structure is const and all of the functions performing on it
+ * obviously receives a const argument, but here (and only on the SMIO
+ * initialization) we need to make an exception if we want to keep the
+ * functions' description and the function pointers separate */
+ err = smio_init_exp_ops (self, (disp_op_t **) trigger_mux_exp_ops,
+ trigger_mux_exp_fp);
+ ASSERT_TEST(err == SMIO_SUCCESS, "Could not fill SMIO "
+ "function descriptors with the callbacks", err_fill_desc);
+
+ err = smio_set_exp_ops (self, trigger_mux_exp_ops);
+ ASSERT_TEST(err == SMIO_SUCCESS, "Could not set SMIO exported operations",
+ err_smio_set_exp_ops);
+
+ /* Initialize specific structure */
+ smio_trigger_mux_t *smio_handler = smio_trigger_mux_new (self);
+ ASSERT_ALLOC(smio_handler, err_smio_handler_alloc, SMIO_ERR_ALLOC);
+ err = smio_set_handler (self, smio_handler);
+ ASSERT_TEST(err == SMIO_SUCCESS, "Could not set SMIO handler",
+ err_smio_set_handler);
+
+ return err;
+
+err_smio_set_handler:
+ smio_trigger_mux_destroy (&smio_handler);
+err_smio_handler_alloc:
+ smio_set_exp_ops (self, NULL);
+err_smio_set_exp_ops:
+err_fill_desc:
+ smio_set_thsafe_client_ops (self, NULL);
+err_smio_set_thsafe_ops:
+ smio_set_ops (self, NULL);
+err_smio_set_ops:
+err_set_name:
+err_set_id:
+ return err;
+}
+
+/* Destroy sm_io instance of trigger_mux */
+smio_err_e trigger_mux_shutdown (smio_t *self)
+{
+ DBE_DEBUG (DBG_SM_IO | DBG_LVL_TRACE, "[sm_io:trigger_mux_exp] Shutting down trigger_mux\n");
+
+ smio_err_e err = SMIO_SUCCESS;
+ smio_trigger_mux_t *trig_iface = smio_get_handler (self);
+ ASSERT_TEST(trig_iface != NULL, "Could not get trig_iface handler",
+ err_trig_iface_handler, SMIO_ERR_ALLOC /* FIXME: improve return code */);
+
+ /* Destroy SMIO instance */
+ smio_trigger_mux_destroy (&trig_iface);
+ /* Nullify operation pointers */
+ smio_set_exp_ops (self, NULL);
+ smio_set_thsafe_client_ops (self, NULL);
+ smio_set_ops (self, NULL);
+
+err_trig_iface_handler:
+ return err;
+}
+
+const smio_bootstrap_ops_t trigger_mux_bootstrap_ops = {
+ .init = trigger_mux_init,
+ .shutdown = trigger_mux_shutdown,
+ .config_defaults = trigger_mux_config_defaults
+};
+
+SMIO_MOD_DECLARE(TRIGGER_MUX_SDB_DEVID, TRIGGER_MUX_SDB_NAME, trigger_mux_bootstrap_ops)
diff --git a/src/sm_io/modules/trigger_mux/sm_io_trigger_mux_exp.h b/src/sm_io/modules/trigger_mux/sm_io_trigger_mux_exp.h
new file mode 100644
index 0000000000000000000000000000000000000000..2105a78f83247d5a38cc101006a2eb1687eb00b8
--- /dev/null
+++ b/src/sm_io/modules/trigger_mux/sm_io_trigger_mux_exp.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2016 LNLS (www.lnls.br)
+ * Author: Lucas Russo <lucas.russo@lnls.br>
+ *
+ * Released according to the GNU GPL, version 3 or any later version.
+ */
+
+#ifndef _TRIGGER_MUX_H_
+#define _TRIGGER_MUX_H_
+
+/* Known modules IDs (from SDB records defined in FPGA) */
+#define TRIGGER_MUX_SDB_DEVID 0x84b6a5ac
+#define TRIGGER_MUX_SDB_NAME "TRIGGER_MUX"
+
+extern const smio_bootstrap_ops_t trigger_mux_bootstrap_ops;
+
+#endif
+
diff --git a/src/sm_io/modules/trigger_mux/sm_io_trigger_mux_exports.c b/src/sm_io/modules/trigger_mux/sm_io_trigger_mux_exports.c
new file mode 100644
index 0000000000000000000000000000000000000000..a7ff161186719db8fa267e7202fe2b14f8958214
--- /dev/null
+++ b/src/sm_io/modules/trigger_mux/sm_io_trigger_mux_exports.c
@@ -0,0 +1,73 @@
+/*
+ * Copyright (C) 2016 LNLS (www.lnls.br)
+ * Author: Lucas Russo <lucas.russo@lnls.br>
+ *
+ * Released according to the GNU GPL, version 3 or any later version.
+ */
+
+#include "sm_io_exports_helper.h"
+#include "sm_io_codes.h"
+
+/* Description SMIO TRIGGER_MUX functions */
+
+disp_op_t trigger_mux_rcv_src_exp = {
+ .name = TRIGGER_MUX_NAME_RCV_SRC,
+ .opcode = TRIGGER_MUX_OPCODE_RCV_SRC,
+ .retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ .retval_owner = DISP_OWNER_OTHER,
+ .args = {
+ DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ DISP_ARG_END
+ }
+};
+
+disp_op_t trigger_mux_rcv_in_sel_exp = {
+ .name = TRIGGER_MUX_NAME_RCV_IN_SEL,
+ .opcode = TRIGGER_MUX_OPCODE_RCV_IN_SEL,
+ .retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ .retval_owner = DISP_OWNER_OTHER,
+ .args = {
+ DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ DISP_ARG_END
+ }
+};
+
+disp_op_t trigger_mux_transm_src_exp = {
+ .name = TRIGGER_MUX_NAME_TRANSM_SRC,
+ .opcode = TRIGGER_MUX_OPCODE_TRANSM_SRC,
+ .retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ .retval_owner = DISP_OWNER_OTHER,
+ .args = {
+ DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ DISP_ARG_END
+ }
+};
+
+disp_op_t trigger_mux_transm_out_sel_exp = {
+ .name = TRIGGER_MUX_NAME_TRANSM_OUT_SEL,
+ .opcode = TRIGGER_MUX_OPCODE_TRANSM_OUT_SEL,
+ .retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ .retval_owner = DISP_OWNER_OTHER,
+ .args = {
+ DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+ DISP_ARG_END
+ }
+};
+
+/* Exported function description */
+const disp_op_t *trigger_mux_exp_ops [] = {
+ &trigger_mux_rcv_src_exp,
+ &trigger_mux_rcv_in_sel_exp,
+ &trigger_mux_transm_src_exp,
+ &trigger_mux_transm_out_sel_exp,
+ NULL
+};
+
diff --git a/src/sm_io/modules/trigger_mux/sm_io_trigger_mux_exports.h b/src/sm_io/modules/trigger_mux/sm_io_trigger_mux_exports.h
new file mode 100644
index 0000000000000000000000000000000000000000..48cb56718e478c41b4620e770ef97f3cce9a71fe
--- /dev/null
+++ b/src/sm_io/modules/trigger_mux/sm_io_trigger_mux_exports.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2016 LNLS (www.lnls.br)
+ * Author: Lucas Russo <lucas.russo@lnls.br>
+ *
+ * Released according to the GNU GPL, version 3 or any later version.
+ */
+
+#ifndef _SM_IO_TRIGGER_MUX_EXPORTS_H_
+#define _SM_IO_TRIGGER_MUX_EXPORTS_H_
+
+#include "disptable.h"
+
+extern disp_op_t trigger_mux_rcv_src_exp;
+extern disp_op_t trigger_mux_rcv_in_sel_exp;
+extern disp_op_t trigger_mux_transm_src_exp;
+extern disp_op_t trigger_mux_transm_out_sel_exp;
+
+extern const disp_op_t *trigger_mux_exp_ops [];
+
+#endif
+
diff --git a/src/sm_io/modules/trigger_mux/trigger_mux.mk b/src/sm_io/modules/trigger_mux/trigger_mux.mk
new file mode 100644
index 0000000000000000000000000000000000000000..e3345fd78a954e5b16da332ae9ec9a5a94b5b4dd
--- /dev/null
+++ b/src/sm_io/modules/trigger_mux/trigger_mux.mk
@@ -0,0 +1,6 @@
+sm_io_trigger_mux_DIR = $(SRC_DIR)/sm_io/modules/trigger_mux
+
+sm_io_trigger_mux_OBJS = $(sm_io_trigger_mux_DIR)/sm_io_trigger_mux_core.o \
+ $(sm_io_trigger_mux_DIR)/sm_io_trigger_mux_exp.o \
+ $(sm_io_trigger_mux_DIR)/sm_io_trigger_mux_exports.o \
+ $(sm_io_trigger_mux_DIR)/sm_io_trigger_mux_defaults.o
diff --git a/src/sm_io/protocols/ops/sm_pr_i2c.c b/src/sm_io/protocols/ops/sm_pr_i2c.c
index e49739e63f4988be593983b6435e12898b3f95f3..902f1b5566b443a9764213c97578f22f15e0581b 100644
--- a/src/sm_io/protocols/ops/sm_pr_i2c.c
+++ b/src/sm_io/protocols/ops/sm_pr_i2c.c
@@ -486,14 +486,14 @@ static ssize_t _i2c_write_generic (smpr_t *self, uint8_t *data,
if (trans_size != size) {
DBE_DEBUG (DBG_SM_PR | DBG_LVL_WARN,
- "[sm_pr:i2c] _i2c_read_generic: Data size differs from Transfer size.\n"
- "\tChoosing the smallest value\n");
+ "[sm_pr:i2c] _i2c_write_generic: Data size differs from Transfer size.\n"
+ "\tChoosing the smallest value between trans_size (%u) and size (%lu)\n", trans_size, size);
}
/* Choose the smallest one */
trans_size = (trans_size > size) ? size : trans_size;
DBE_DEBUG (DBG_SM_PR | DBG_LVL_TRACE,
- "[sm_pr:i2c] _i2c_write_generic: Transmission size = %u bytes\n", trans_size);
+ "[sm_pr:i2c] _i2c_write_generic: Transmission size (flags) = %u bytes\n", trans_size);
/* Send actual data, byte by byte*/
uint32_t i;
@@ -572,7 +572,7 @@ static ssize_t _i2c_read_generic (smpr_t *self, uint8_t *data,
if (trans_size != size) {
DBE_DEBUG (DBG_SM_PR | DBG_LVL_WARN,
"[sm_pr:i2c] _i2c_read_generic: Data size differs from Transfer size.\n"
- "\tChoosing the smallest value\n");
+ "\tChoosing the smallest value between trans_size (%u) and size (%lu)\n", trans_size, size);
}
/* Choose the smallest one */