Beam Positoning Monitor - Gateware:master commitshttps://ohwr.org/project/bpm-gw/commits/master2018-10-03T20:44:21Zhttps://ohwr.org/project/bpm-gw/commit/e0a2f39fdff5f93c68d8d569f66df29900adf58eMerge branch 'devel'2018-10-03T20:44:21ZLucas Russolerwys@gmail.comhttps://ohwr.org/project/bpm-gw/commit/349c211e5bbcbd724756a76a8651d2b8502d13b6Merge branch 'phase-sync-trig' into devel2018-10-03T20:44:05ZLucas Russolerwys@gmail.comhttps://ohwr.org/project/bpm-gw/commit/ea193f70b571a06d9f8f65fcd6746bf23e7dcbbc.gitignore: add Xilinx Impact files2018-10-03T20:43:29ZLucas Russolerwys@gmail.comhttps://ohwr.org/project/bpm-gw/commit/9f10a102163cf9866f61b80bb8f372c64ef5d266ip_cores/dsp-cores: update submodule reference2018-10-03T20:42:43ZLucas Russolerwys@gmail.comhttps://ohwr.org/project/bpm-gw/commit/63d91b5695382e3785c8371bad1abe62df13e467Merge branch 'devel'2018-07-30T17:13:19ZLucas Russolerwys@gmail.comhttps://ohwr.org/project/bpm-gw/commit/02883a498a1e15ead05a3f3c216791db67ec2eb1ip_cores/dsp-cores: update submodule reference2018-07-27T18:55:38ZHenrique Silvahenrique.silva@lnls.brhttps://ohwr.org/project/bpm-gw/commit/e1caa4de21a63622446dd83637c24d4a5d6ebd0fdbe_bpm_gen.vhd: Include trigger to sync RFFE switching clock phase2018-07-27T18:48:45ZHenrique Silvahenrique.silva@lnls.br
The recv trigger channel 19 is connected now to the core that generates the RFFE switching clock (swap_freqgen) and is used to synchronize its phase.
The switching counter is reset upon a high-state detection on the trigger line.
One can use a MLVDS external trigger to sync all boards at the same timehttps://ohwr.org/project/bpm-gw/commit/6d833900f3164eddfd3f5c1269586efe19bdb907README.md: fix formatting of project organization section2018-07-02T17:59:37ZLucas Russolerwys@gmail.comhttps://ohwr.org/project/bpm-gw/commit/e35490a24574cd93ca3ece99dd2a702c47813a21README.md: fix typo on synthesis build script instruction2018-07-02T17:54:25ZLucas Russolerwys@gmail.com
The correct script to build is "build_bitstream_local.sh"https://ohwr.org/project/bpm-gw/commit/e54c2aad60610fd34eebecdd83a601e3e63035a6README.md: rename README to markdown extensions2018-07-02T17:52:10ZLucas Russolerwys@gmail.comhttps://ohwr.org/project/bpm-gw/commit/b130cef4d585eec38bbeb1f245994211ce7f33f6README: update sim/syn/project instructions2018-07-02T17:50:58ZLucas Russolerwys@gmail.com
The README was very outdated and the
simulations, synthesis and project organization
ahve chenged since then.https://ohwr.org/project/bpm-gw/commit/5c28f96f47c0007ef662b9b72bae093452b8ffbcMerge branch 'devel'2018-06-08T21:33:35ZLucas Russolerwys@gmail.comhttps://ohwr.org/project/bpm-gw/commit/0fbdadfb1d45e5fe8e94ded66a1373fbabe8616bMerge branch 'cic-sync' into devel2018-06-08T21:33:13ZLucas Russolerwys@gmail.comhttps://ohwr.org/project/bpm-gw/commit/57a15028792926a6e619d4a12c41a3778c5c3193ip_cores/dsp-cores: update submodule reference2018-06-08T20:59:59ZLucas Russolerwys@gmail.comhttps://ohwr.org/project/bpm-gw/commit/c00c28df66c1323792d213710a061e6506ad98b0Merge branch 'devel'2018-06-04T00:14:05ZLucas Russolerwys@gmail.comhttps://ohwr.org/project/bpm-gw/commit/89661d8dcc103c88615d2de81a44ac37e93b13c0ip_cores/dsp-cores: update submodule reference2018-06-02T02:56:13ZLucas Russolerwys@gmail.comhttps://ohwr.org/project/bpm-gw/commit/860d71ac2eb26f1d48c059dd793dbf5c908b4d47ip_cores/dsp-cores: update submodule reference2018-06-01T15:41:00ZLucas Russolerwys@gmail.comhttps://ohwr.org/project/bpm-gw/commit/99e041be582151b4b73a19cbb4a5e76a83adfd92.gitignore: add .hdlmake tcl generated files2018-06-01T14:42:45ZLucas Russolerwys@gmail.comhttps://ohwr.org/project/bpm-gw/commit/96e430fb6fff181b1f607b73e9643e8808ca2740.gitignore: add hdlmake generated stuff2018-06-01T13:20:09ZLucas Russolerwys@gmail.comhttps://ohwr.org/project/bpm-gw/commit/251252d787a8b923d7b9848017eeb3cf45f32565syn/*/dbe_pbpm: add language=vhdl as hdlmake 3 requires it2018-05-29T11:23:00ZLucas Russolerwys@gmail.comhttps://ohwr.org/project/bpm-gw/commit/25ae9ed8a6d82336f852593f8ab2694efe9e3914syn/*/dbe_bpm2_sr_uvx: add language=vhdl as hdlmake 3 requires it2018-05-29T11:22:17ZLucas Russolerwys@gmail.comhttps://ohwr.org/project/bpm-gw/commit/ffa311ed465547102103ad1d7982bca031e9ac8csyn/*/dbe_bpm2_sr_uvx: add language=vhdl as hdlmake 3 requires it2018-05-29T11:21:51ZLucas Russolerwys@gmail.comhttps://ohwr.org/project/bpm-gw/commit/c83293ea9ade7460f3a92822cdb76febfb757a18syn/*/dbe_bpm2_bo_sirius: add language=vhdl as hdlmake 3 requires it2018-05-29T11:21:28ZLucas Russolerwys@gmail.comhttps://ohwr.org/project/bpm-gw/commit/475d9a26b702c9017a104a4a0fa8f00751a02b10syn/*/dbe_bpm2_sr_sirius: add language=vhdl as hdlmake 3 requires it2018-05-29T11:19:21ZLucas Russolerwys@gmail.comhttps://ohwr.org/project/bpm-gw/commit/89b651b011def81eeb923ab3b317e82d35ed0d91top/*/dbe_bpm_gen: add Monit. 1 data rate to acquisition module2018-05-28T17:16:24ZLucas Russolerwys@gmail.comhttps://ohwr.org/project/bpm-gw/commit/b045bb35395f6fda81cbe89581732d6281187ba2ip_cores/dsp-cores: update submodule reference2018-05-28T17:16:01ZLucas Russolerwys@gmail.comhttps://ohwr.org/project/bpm-gw/commit/91ebf0c889653cf2858dea2ccd79657bedf01fc9Merge branch 'devel'2018-03-01T21:28:41ZLucas Russolerwys@gmail.comhttps://ohwr.org/project/bpm-gw/commit/1ecc01fd3ad2553e9a39e315664ee338e59a3545ip_cores/infra-cores: update submodule reference2018-03-01T20:11:33ZLucas Russolerwys@gmail.comhttps://ohwr.org/project/bpm-gw/commit/edf9d3047de89bdd10f1dbe7f77221efd2064c02top/*/dbe_bpm_gen: add missing trigger_common_pkg2018-01-26T12:43:53ZLucas Russolerwys@gmail.com
With recent changes, trigger_pkg was split
into common definitions and type, and
component declarations.https://ohwr.org/project/bpm-gw/commit/67d8def6eea0c57a720146f58076e85048236416ip_cores/infra-cores: update submodule reference2018-01-26T12:43:53ZLucas Russolerwys@gmail.comhttps://ohwr.org/project/bpm-gw/commit/d79cf4ed233e377c5aa455d0a064f74ded10b85aMerge branch 'devel'2017-11-12T01:00:08ZLucas Russolerwys@gmail.comhttps://ohwr.org/project/bpm-gw/commit/5b9fd4ca226579c324144bf853afb219e86c8409ip_cores/infra-cores: update submodule reference2017-11-07T14:01:13ZLucas Russolerwys@gmail.comhttps://ohwr.org/project/bpm-gw/commit/02429bd877b4cfaaf94d71c8944cae7b9437bf11top/*/dbe_bpm: remove area constraints from acq_core, as it worses timing2017-11-07T14:00:59ZLucas Russolerwys@gmail.comhttps://ohwr.org/project/bpm-gw/commit/e2d2544b3c08bde105faabefc84cd851b66ca616top/*/dbe_bpm2: remove area constraints from acq_core, as it worses timing2017-11-07T13:59:29ZLucas Russolerwys@gmail.comhttps://ohwr.org/project/bpm-gw/commit/a855687851960a475459985aba724211ba4e6bb5ip_cores/infra-cores: update submodule reference2017-11-01T15:45:03ZLucas Russolerwys@gmail.comhttps://ohwr.org/project/bpm-gw/commit/fe809371028374363b81006c02332423fc7c7b38top/*/dbe_bpm_gen: reduce multishot size to 40962017-11-01T15:44:24ZLucas Russolerwys@gmail.com
8192 was giving us timing problemshttps://ohwr.org/project/bpm-gw/commit/838752de535d888f3113bb23ca867bbd024a3986ip_cores/infra-cores: update submodule reference2017-10-31T11:07:29ZLucas Russolerwys@gmail.comhttps://ohwr.org/project/bpm-gw/commit/1c0524465a058cb0ef88dd0a374e67d15a5cb99ftop/afc_v3/*/dbe_bpm_gen/*: reduce multishot RAM from Post-Mortem acq_core2017-10-30T20:17:39ZLucas Russolerwys@gmail.com
In this way, we can save FPGA resources, as all acquisition
transactions from Post-Mortem are done via the external DDR.https://ohwr.org/project/bpm-gw/commit/39360ed51de5a630dbfdb03513dd40b6f2fa89e7ip_cores/infra-cores: update submodule reference2017-10-30T20:17:39ZLucas Russolerwys@gmail.comhttps://ohwr.org/project/bpm-gw/commit/dc6a9af280ea791529581438730a2dc1fa96cbbatop/*/dbe_bpm_gen: add missing infra_cores SDB info record2017-09-11T15:01:58ZLucas Russolerwys@gmail.com
Ever since we began using the infra_cores
submodule, the related SDB record is missing
from the top SDB layout.