Commit e1caa4de authored by Henrique Silva's avatar Henrique Silva

dbe_bpm_gen.vhd: Include trigger to sync RFFE switching clock phase

The recv trigger channel 19 is connected now to the core that generates the RFFE switching clock (swap_freqgen) and is used to synchronize its phase.
The switching counter is reset upon a high-state detection on the trigger line.
One can use a MLVDS external trigger to sync all boards at the same time
parent 6d833900
......@@ -706,8 +706,9 @@ architecture rtl of dbe_bpm_gen is
constant c_acq_monit_amp_id : natural := 16;
constant c_acq_monit_pos_id : natural := 17;
constant c_trigger_sw_clk_id : natural := 18;
constant c_phase_sync_trigger_id : natural := 19;
constant c_trig_num_channels : natural := 1;
constant c_trig_num_channels : natural := 2;
-- Number of channels per acquisition core
constant c_acq_num_channels : natural := 18; -- ADC + ADC SWAP + MIXER + TBT AMP + TBT POS +
-- FOFB AMP + FOFB POS + MONIT AMP + MONIT POS + MONIT1 AMP +
......@@ -2995,6 +2996,12 @@ begin
-----------------------------
rffe_swclk_o => dsp1_clk_rffe_swap,
-----------------------------
-- Synchronization trigger for RFFE swap clock
-----------------------------
sync_trig_i => trig_pulse_rcv(c_trig_mux_0_id, c_phase_sync_trigger_id).pulse,
-----------------------------
-- Debug signals
-----------------------------
......@@ -3213,6 +3220,12 @@ begin
-----------------------------
rffe_swclk_o => dsp2_clk_rffe_swap,
-----------------------------
-- Synchronization trigger for RFFE swap clock
-----------------------------
sync_trig_i => trig_pulse_rcv(c_trig_mux_1_id, c_phase_sync_trigger_id).pulse,
-----------------------------
-- Debug signals
-----------------------------
......
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