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Beam Positoning Monitor - Gateware
Commit d01c6e95 authored by Lucas Russo's avatar Lucas Russo
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Merge branch 'devel'

parents 68ccd175 24a5ac7d
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.gitignore
View file @ d01c6e95
*~
*.swp
*.orig
hdl/syn/*.runs*
######################
# Compilation files
######################
*Makefile
*transcript
*make_*
*_history
######################
# Modelsim
######################
*.wlf
work/
######################
# Temporary files
######################
*#*
######################
# Vivado files
######################
*.jou
*.log
*.str
*.xpr
*.edif
*.mif
.Xil/
\ No newline at end of file
dsp-cores @ 1bf1b924
Subproject commit 61127ed11e010b182e62239906f627a6caa50dbc
Subproject commit 1bf1b924c576334225a5df2c707ca8666d96a2c8
hdl/modules/dbe_common/Manifest.py
View file @ d01c6e95
modules = { "local" : ["reset_synch",
"pulse2level"] };
"pulse2level",
"trigger_rcv",
"counter_simple",
"extend_pulse_dyn",
"heartbeat"] };
files = [ "dbe_common_pkg.vhd" ];
hdl/modules/dbe_common/counter_simple/counter_simple.vhd 0 → 100644
View file @ d01c6e95
-------------------------------------------------------------------------------
-- Title : Simple counter
-- Project :
-------------------------------------------------------------------------------
-- File : counter.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2015-11-11
-- Last update: 2015-12-11
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Simple counter for testing, with clock enable
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-- This program is free software: you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public License
-- as published by the Free Software Foundation, either version 3 of
-- the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this program. If not, see
-- <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-11-11 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity counter_simple is
generic(
g_output_width : positive := 8
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
ce_i : in std_logic;
up_i : in std_logic;
down_i : in std_logic;
count_o : out std_logic_vector(g_output_width-1 downto 0)
);
end counter_simple;
architecture behavioural of counter_simple is
signal count : unsigned(g_output_width-1 downto 0) := to_unsigned(0, g_output_width);
begin
counter_simple : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
count <= to_unsigned(0, g_output_width);
else
if ce_i = '1' then
if up_i = '1' then
count <= count + 1;
elsif down_i = '1' then
count <= count - 1;
end if;
end if; --ce
end if; --rst
end if; -- clk
end process;
count_o <= std_logic_vector(count);
end architecture behavioural;
hdl/modules/dbe_common/dbe_common_pkg.vhd
View file @ d01c6e95
library ieee;
use ieee.std_logic_1164.all;
use ieee.NUMERIC_STD.all;
package dbe_common_pkg is
......@@ -37,4 +38,57 @@ package dbe_common_pkg is
);
end component;
component trigger_rcv is
generic (
g_glitch_len_width : positive;
g_sync_edge : string);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
len_i : in std_logic_vector(g_glitch_len_width-1 downto 0);
data_i : in std_logic;
pulse_o : out std_logic);
end component trigger_rcv;
component extend_pulse_dyn is
generic (
g_width_bus_size : natural);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
pulse_i : in std_logic;
pulse_width_i : in unsigned(g_width_bus_size-1 downto 0);
extended_o : out std_logic := '0');
end component extend_pulse_dyn;
component counter_simple is
generic (
g_output_width : positive);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
ce_i : in std_logic;
up_i : in std_logic;
down_i : in std_logic;
count_o : out std_logic_vector(g_output_width-1 downto 0));
end component counter_simple;
component heartbeat
generic
(
-- number of system clock cycles to count before blinking
g_clk_counts : natural := 100000000
);
port
(
-- 100 MHz system clock
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Heartbeat pulse output
heartbeat_o : out std_logic
);
end component;
end dbe_common_pkg;
hdl/modules/dbe_common/extend_pulse_dyn/extend_pulse_dyn.vhd 0 → 100644
View file @ d01c6e95
-------------------------------------------------------------------------------
-- Title : Dynamic pulse width extender
-- Project :
-------------------------------------------------------------------------------
-- File : extend_pulse_dyn.vhd
-- Author : Vitor Finotti Ferreira <vfinotti@finotti-Inspiron-7520>
-- Company : Brazilian Synchrotron Light Laboratory, LNLS/CNPEM
-- Created : 2016-01-22
-- Last update: 2016-01-27
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-- Synchronous pulse extender. Generates a pulse of dynamically programmable width upon
-- detection of a rising edge in the input. The code is based on
-- gc_extend_pulse.vhd created by Tomasz Wlostowskyt, from General Cores library.
-------------------------------------------------------------------------------
-- Copyright (c) 2016 Brazilian Synchrotron Light Laboratory, LNLS/CNPEM
-- This program is free software: you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public License
-- as published by the Free Software Foundation, either version 3 of
-- the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this program. If not, see
-- <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-dec-17 0.9 vfinotti Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.NUMERIC_STD.all;
entity extend_pulse_dyn is
generic (
-- output pulse width in clk_i cycles
g_width_bus_size : natural := 32
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
pulse_i : in std_logic;
pulse_width_i : in unsigned(g_width_bus_size-1 downto 0);
-- extended output pulse
extended_o : out std_logic := '0');
end extend_pulse_dyn;
architecture rtl of extend_pulse_dyn is
signal cntr : unsigned(g_width_bus_size-1 downto 0);
signal extended_int : std_logic;
begin -- rtl
extend : process (clk_i, rst_n_i)
begin -- process extend
if rst_n_i = '0' then -- asynchronous reset (active low)
extended_int <= '0';
cntr <= (others => '0');
elsif clk_i'event and clk_i = '1' then -- rising clock edge
if(pulse_i = '1') then
extended_int <= '1';
cntr <= pulse_width_i - 2;
elsif cntr /= to_unsigned(0, cntr'length) then
cntr <= cntr - 1;
else
extended_int <= '0';
end if;
end if;
end process extend;
extended_o <= pulse_i or extended_int;
end rtl;
hdl/modules/dbe_common/heartbeat/heartbeat.vhd 0 → 100755
View file @ d01c6e95
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Common cores
use work.genram_pkg.all;
entity heartbeat is
generic
(
-- number of system clock cycles to count before blinking
g_clk_counts : natural := 100000000
);
port
(
-- 100 MHz system clock
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Heartbeat pulse output
heartbeat_o : out std_logic
);
end heartbeat;
architecture rtl of heartbeat is
constant c_pps_counter_width : natural := f_log2_size(g_clk_counts);
signal hb : std_logic := '0';
signal pps_counter : unsigned(c_pps_counter_width-1 downto 0) :=
(others => '0');
begin
p_heartbeat : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
pps_counter <= to_unsigned(0, pps_counter'length);
hb <= '0';
else
if pps_counter = g_clk_counts-1 then
pps_counter <= to_unsigned(0, pps_counter'length);
hb <= not hb;
else
pps_counter <= pps_counter + 1;
end if;
end if;
end if;
end process;
heartbeat_o <= hb;
end rtl;
hdl/modules/dbe_common/trigger_rcv/trigger_rcv.vhd 0 → 100644
View file @ d01c6e95
-------------------------------------------------------------------------------
-- Title : Trigger receiver
-- Project :
-------------------------------------------------------------------------------
-- File : trigger_rcv.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2015-11-09
-- Last update: 2016-01-22
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Receives a signal from an FPGA port, debounces the signal and
-- outputs a pulse with a configurable clock width.
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-- This program is free software: you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public License
-- as published by the Free Software Foundation, either version 3 of
-- the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this program. If not, see
-- <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-11-09 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.gencores_pkg.all;
entity trigger_rcv is
generic (
-- Number of glicth filter registers
g_glitch_len_width : positive := 8;
-- Width of the output pulse after edge detection
g_sync_edge : string := "positive"
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
len_i : in std_logic_vector(g_glitch_len_width-1 downto 0);
data_i : in std_logic;
pulse_o : out std_logic
);
end entity trigger_rcv;
architecture structural of trigger_rcv is
signal deglitched : std_logic;
signal data_sync : std_logic := '0';
component gc_dyn_glitch_filt is
generic (
g_len_width : natural);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
len_i : in std_logic_vector(g_len_width-1 downto 0);
dat_i : in std_logic;
dat_o : out std_logic);
end component gc_dyn_glitch_filt;
component gc_sync_ffs is
generic (
g_sync_edge : string);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
data_i : in std_logic;
synced_o : out std_logic;
npulse_o : out std_logic;
ppulse_o : out std_logic);
end component gc_sync_ffs;
begin
-- Prevent matastability problems
cmp_input_sync : gc_sync_ffs
generic map(
g_sync_edge => "positive")
port map(
clk_i => clk_i,
rst_n_i => rst_n_i,
data_i => data_i,
synced_o => data_sync,
npulse_o => open,
ppulse_o => open);
cmp_deglitcher : gc_dyn_glitch_filt
generic map (
g_len_width => g_glitch_len_width)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
len_i => len_i,
dat_i => data_sync,
dat_o => deglitched);
cmp_edge_detector : gc_sync_ffs
generic map(
g_sync_edge => g_sync_edge)
port map(
clk_i => clk_i,
rst_n_i => rst_n_i,
data_i => deglitched,
synced_o => open,
npulse_o => open,
ppulse_o => pulse_o);
end architecture structural;
hdl/modules/dbe_wishbone/Manifest.py
View file @ d01c6e95
......@@ -2,14 +2,20 @@ files = [ "dbe_wishbone_pkg.vhd" ];
modules = { "local" : [
"wb_stream",
"wb_trigger_iface",
"wb_trigger_mux",
"wb_trigger",
"wb_fmc150",
"wb_fmc516",
"wb_fmc130m_4ch",
"wb_fmc250m_4ch",
"wb_ethmac_adapter",
"wb_ethmac",
"wb_dbe_periph",
"wb_rs232_syscon",
"wb_acq_core",
"wb_acq_core_mux",
"wb_pcie"
"wb_pcie",
"wb_fmc_adc_common",
"wb_fmc_active_clk"
] };
hdl/modules/dbe_wishbone/wb_acq_core/acq_core_pkg.vhd
View file @ d01c6e95
......@@ -751,7 +751,21 @@ package acq_core_pkg is
axis_s2mm_pld_tkeep_o : out std_logic_vector(g_ddr_payload_width/8-1 downto 0);
axis_s2mm_pld_tlast_o : out std_logic;
axis_s2mm_pld_tvalid_o : out std_logic;
axis_s2mm_pld_tready_i : in std_logic
axis_s2mm_pld_tready_i : in std_logic;
axis_s2mm_rstn_o : out std_logic;
axis_s2mm_halt_o : out std_logic;
axis_s2mm_halt_cmplt_i : in std_logic;
axis_s2mm_allow_addr_req_o : out std_logic;
axis_s2mm_addr_req_posted_i : in std_logic;
axis_s2mm_wr_xfer_cmplt_i : in std_logic;
axis_s2mm_ld_nxt_len_i : in std_logic;
axis_s2mm_wr_len_i : in std_logic_vector(7 downto 0);
-- Debug Outputs
dbg_ddr_addr_cnt_axis_o : out std_logic_vector(g_ddr_addr_width-1 downto 0);
dbg_ddr_addr_init_o : out std_logic_vector(g_ddr_addr_width-1 downto 0);
dbg_ddr_addr_max_o : out std_logic_vector(g_ddr_addr_width-1 downto 0)
);
end component;
......
hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_axis_write.vhd
View file @ d01c6e95
......@@ -93,7 +93,21 @@ port
axis_s2mm_pld_tkeep_o : out std_logic_vector(g_ddr_payload_width/8-1 downto 0);
axis_s2mm_pld_tlast_o : out std_logic;
axis_s2mm_pld_tvalid_o : out std_logic;
axis_s2mm_pld_tready_i : in std_logic
axis_s2mm_pld_tready_i : in std_logic;
axis_s2mm_rstn_o : out std_logic;
axis_s2mm_halt_o : out std_logic;
axis_s2mm_halt_cmplt_i : in std_logic;
axis_s2mm_allow_addr_req_o : out std_logic;
axis_s2mm_addr_req_posted_i : in std_logic;
axis_s2mm_wr_xfer_cmplt_i : in std_logic;
axis_s2mm_ld_nxt_len_i : in std_logic;
axis_s2mm_wr_len_i : in std_logic_vector(7 downto 0);
-- Debug Outputs
dbg_ddr_addr_cnt_axis_o : out std_logic_vector(g_ddr_addr_width-1 downto 0);
dbg_ddr_addr_init_o : out std_logic_vector(g_ddr_addr_width-1 downto 0);
dbg_ddr_addr_max_o : out std_logic_vector(g_ddr_addr_width-1 downto 0)
);
end acq_ddr3_axis_write;
......@@ -267,6 +281,12 @@ architecture rtl of acq_ddr3_axis_write is
signal ddr_rdy_cmd : std_logic;
signal ddr_rdy_pld : std_logic;
-- Halt/Rst signals
type t_hrst_state is (IDLE, HALT_GEN, WAIT_HALT_CMPLT, RST_GEN, RST1, RST2, RST3);
signal ddr_axis_rstn : std_logic := '1';
signal ddr_axis_halt : std_logic := '0';
signal hrst_state : t_hrst_state := IDLE;
begin
assert (g_ddr_payload_width = 256 or g_ddr_payload_width = 512)
......@@ -498,6 +518,10 @@ begin
if rising_edge(ext_clk_i) then
if ext_rst_n_i = '0' then
ddr_addr_cnt_axis <= to_unsigned(0, ddr_addr_cnt_axis'length);
-- FIXME: Reset the init/end register cause fast acquisition
-- data path to fail on hw or sw trigger acquisitions.
-- This might be related to the fact that these addresses
-- might not be properly configured.
else
if wr_start_i = '1' then
......@@ -522,6 +546,11 @@ begin
-- To Flow Control module
ddr_addr_in_axis <= std_logic_vector(ddr_addr_cnt_axis);
-- Debug outputs
dbg_ddr_addr_cnt_axis_o <= std_logic_vector(ddr_addr_cnt_axis);
dbg_ddr_addr_init_o <= std_logic_vector(ddr_addr_init);
dbg_ddr_addr_max_o <= std_logic_vector(ddr_addr_max);
-----------------------------------------------------------------------------
-- Store DDR Trigger address
-----------------------------------------------------------------------------
......@@ -752,6 +781,77 @@ begin
fc_data_id_cmd <= fc_dout(c_acq_header_id_top_idx+c_fc_header_bot_idx downto
c_acq_header_id_bot_idx+c_fc_header_bot_idx);
-----------------------------------------------------------------------------
-- AXIS Soft Shutdown Interface
-----------------------------------------------------------------------------
-- We reset on two situations: a regular reset (startup or reset trigger) or
-- when we abort an acquisition (fsm_stop signal). For this to work seamlessly
-- with AXIS interface, we must drive the halt/rst signals properly
-- First, generate halt signal to force AXIS datamover to shutdown its engine.
-- We can use the same as rst, as it's long enough
-- Secondly, we must look into axis_S2mm_halt_cmplt_i signal. When it completes
-- its shutdown (asserted high),. we must then reset the AXIS core using
-- axis_s2mm_rstn_o signal
-- AXIS Halt/Rst state machine.
p_axis_halt_rst_fsm : process(ext_clk_i)
begin
if rising_edge(ext_clk_i) then
case hrst_state is
-- Waits for a halt command to start
when IDLE =>
ddr_axis_rstn <= '1';
ddr_axis_halt <= '0';
if ext_rst_n_i = '0' then
hrst_state <= HALT_GEN;
end if;
when HALT_GEN =>
ddr_axis_halt <= '1';
hrst_state <= WAIT_HALT_CMPLT;
when WAIT_HALT_CMPLT =>
-- Wait for AXIS core to gracefully shutdown then reset the core
-- and deasserts halt
if axis_s2mm_halt_cmplt_i = '1' then
ddr_axis_halt <= '0';
hrst_state <= RST_GEN;
end if;
-- Generates a reset for the core
when RST_GEN =>
ddr_axis_rstn <= '0';
hrst_state <= RST1;
-- Wait for a minimum of 3 clock cycles for a successful reset
-- (axi datamover v5.1, page 16, table 2-6, about m_axi_s2mm_aresetn)
when RST1 =>
hrst_state <= RST2;
when RST2 =>
hrst_state <= RST3;
-- Deasserts rst and go back to the beginning
when RST3 =>
ddr_axis_rstn <= '1';
hrst_state <= IDLE;
when others =>
ddr_axis_rstn <= '1';
ddr_axis_halt <= '0';
hrst_state <= IDLE;
end case;
end if;
end process;
axis_s2mm_rstn_o <= ddr_axis_rstn;
axis_s2mm_halt_o <= ddr_axis_halt;
-----------------------------------------------------------------------------
-- AXIS Interface
-----------------------------------------------------------------------------
......@@ -792,6 +892,9 @@ begin
axis_s2mm_cmd_tdata_o(c_axis_cmd_tdata_pad_top_idx downto
c_axis_cmd_tdata_pad_bot_idx) <= (others => '0'); -- cmd_pad
-- We always allow address request
axis_s2mm_allow_addr_req_o <= '1';
fc_eop_pld <= '1' when fc_dout(c_eop_high downto c_eop_low) = "1" else '0';
-- To/From AXIS Memory Mapped to Stream Commands
......
hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd
View file @ d01c6e95
......@@ -476,9 +476,11 @@ begin
-- Used only for passthrough mode
fifo_in_valid_full <= '1' when fifo_in_valid_cnt = lmt_full_pkt_size else '0';
-- Fifo valid input. We use only the first FIFO full, for precaution and simplicity
fifo_fc_wr_en <= pt_wr_en_i and pt_dvalid_i and not(fifo_in_valid_full) and not(fifo_fc_wr_full(0));
fifo_fc_dpram_wr_en <= dpram_dvalid_i and not(fifo_fc_wr_full(0));
-- Fifo valid input. We use only the first FIFO full, for precaution and simplicity.
-- Don't add "fifo_fc_wr_full" to the condition to write on FIFO. The data will
-- be lost anyway and we can improve timing closure.
fifo_fc_wr_en <= pt_wr_en_i and pt_dvalid_i and not(fifo_in_valid_full);
fifo_fc_dpram_wr_en <= dpram_dvalid_i;
-- Only count when in pre_trigger or post_trigger and we haven't acquire
-- enough samples
......
hdl/modules/dbe_wishbone/wb_acq_core/acq_fsm.vhd
View file @ d01c6e95
......@@ -131,10 +131,12 @@ architecture rtl of acq_fsm is
-- Pre/Post trigger and shots counters
signal pre_trig_cnt : unsigned(c_acq_samples_size-1 downto 0);
signal pre_trig_cnt_max : unsigned(c_acq_samples_size-1 downto 0);
signal pre_trig_done : std_logic;
signal wait_trig_skip_r : std_logic;
signal wait_trig_skip_done : std_logic;
signal post_trig_cnt : unsigned(c_acq_samples_size-1 downto 0);
signal post_trig_cnt_max : unsigned(c_acq_samples_size-1 downto 0);
signal post_trig_done : std_logic;
signal samples_cnt : unsigned(c_acq_samples_size-1 downto 0);
signal shots_cnt : unsigned(15 downto 0);
......@@ -189,23 +191,33 @@ begin
begin
if rising_edge(fs_clk_i) then
if fs_rst_n_i = '0' then
pre_trig_cnt <= to_unsigned(1, pre_trig_cnt'length);
pre_trig_cnt <= to_unsigned(0, pre_trig_cnt'length);
pre_trig_cnt_max <= to_unsigned(0, pre_trig_cnt_max'length);
pre_trig_done <= '0';
else
if (acq_start_i = '1' or pre_trig_done = '1') then
pre_trig_cnt <= to_unsigned(0, pre_trig_cnt'length);
pre_trig_done <= '0';
if pre_trig_samples_i = to_unsigned(0, pre_trig_samples_i'length) then
pre_trig_cnt <= (others => '0');
pre_trig_cnt_max <= to_unsigned(0, pre_trig_cnt_max'length);
else
pre_trig_cnt <= pre_trig_samples_i - 1;
pre_trig_cnt_max <= pre_trig_samples_i-1;
end if;
elsif (acq_in_pre_trig = '1' and acq_dvalid_i = '1') then
pre_trig_cnt <= pre_trig_cnt - 1;
pre_trig_cnt <= pre_trig_cnt + 1;
-- Will increment
if pre_trig_cnt = pre_trig_cnt_max then
pre_trig_done <= '1';
end if;
else
pre_trig_done <= '0';
end if;
end if;
end if;
end process;
pre_trig_done <= '1' when (pre_trig_cnt = to_unsigned(0, pre_trig_cnt'length) and
acq_dvalid_i = '1' and acq_in_pre_trig = '1') else '0';
acq_pre_trig_done_o <= pre_trig_done;
------------------------------------------------------------------------------
......@@ -238,22 +250,32 @@ begin
if rising_edge(fs_clk_i) then
if fs_rst_n_i = '0' then
post_trig_cnt <= to_unsigned(1, post_trig_cnt'length);
post_trig_cnt_max <= to_unsigned(1, post_trig_cnt_max'length);
post_trig_done <= '0';
else
if (acq_start = '1' or post_trig_done = '1') then
post_trig_cnt <= to_unsigned(0, post_trig_cnt'length);
post_trig_done <= '0';
if post_trig_samples_i = to_unsigned(0, post_trig_samples_i'length) then
post_trig_cnt <= (others => '0');
post_trig_cnt_max <= to_unsigned(1, post_trig_cnt_max'length);
else
post_trig_cnt <= post_trig_samples_i - 1;
post_trig_cnt_max <= post_trig_samples_i-1;
end if;
elsif (acq_in_post_trig = '1' and acq_dvalid_i = '1') then
post_trig_cnt <= post_trig_cnt - 1;
post_trig_cnt <= post_trig_cnt + 1;
-- Will increment
if post_trig_cnt = post_trig_cnt_max then
post_trig_done <= '1';
end if;
else
post_trig_done <= '0';
end if;
end if;
end if;
end process;
post_trig_done <= '1' when (post_trig_cnt = to_unsigned(0, post_trig_cnt'length) and
(acq_dvalid_i = '1' or wait_trig_skip_r = '1') and acq_in_post_trig = '1') else '0';
acq_post_trig_done_o <= post_trig_done;
------------------------------------------------------------------------------
......
hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd
View file @ d01c6e95
......@@ -156,6 +156,15 @@ port
axis_s2mm_pld_tvalid_o : out std_logic;
axis_s2mm_pld_tready_i : in std_logic := '0';
axis_s2mm_rstn_o : out std_logic;
axis_s2mm_halt_o : out std_logic;
axis_s2mm_halt_cmplt_i : in std_logic := '0';
axis_s2mm_allow_addr_req_o : out std_logic;
axis_s2mm_addr_req_posted_i : in std_logic := '0';
axis_s2mm_wr_xfer_cmplt_i : in std_logic := '0';
axis_s2mm_ld_nxt_len_i : in std_logic := '0';
axis_s2mm_wr_len_i : in std_logic_vector(7 downto 0) := (others => '0');
axis_mm2s_cmd_tdata_o : out std_logic_vector(71 downto 0);
axis_mm2s_cmd_tvalid_o : out std_logic;
axis_mm2s_cmd_tready_i : in std_logic := '0';
......@@ -376,6 +385,10 @@ architecture rtl of wb_acq_core is
signal test_data_en : std_logic;
signal ddr_trig_addr : std_logic_vector(g_ddr_addr_width-1 downto 0);
-- Debug outputs
signal dbg_ddr_addr_cnt_axis : std_logic_vector(30 downto 0);
signal dbg_ddr_addr_init : std_logic_vector(30 downto 0);
signal dbg_ddr_addr_max : std_logic_vector(30 downto 0);
------------------------------------------------------------------------------
-- Components
------------------------------------------------------------------------------
......@@ -1070,7 +1083,21 @@ begin
axis_s2mm_pld_tkeep_o => axis_s2mm_pld_tkeep_o,
axis_s2mm_pld_tlast_o => axis_s2mm_pld_tlast_o,
axis_s2mm_pld_tvalid_o => axis_s2mm_pld_tvalid_o,
axis_s2mm_pld_tready_i => axis_s2mm_pld_tready_i
axis_s2mm_pld_tready_i => axis_s2mm_pld_tready_i,
axis_s2mm_rstn_o => axis_s2mm_rstn_o,
axis_s2mm_halt_o => axis_s2mm_halt_o,
axis_s2mm_halt_cmplt_i => axis_s2mm_halt_cmplt_i,
axis_s2mm_allow_addr_req_o => axis_s2mm_allow_addr_req_o,
axis_s2mm_addr_req_posted_i => axis_s2mm_addr_req_posted_i,
axis_s2mm_wr_xfer_cmplt_i => axis_s2mm_wr_xfer_cmplt_i,
axis_s2mm_ld_nxt_len_i => axis_s2mm_ld_nxt_len_i,
axis_s2mm_wr_len_i => axis_s2mm_wr_len_i,
-- Debug Outputs
dbg_ddr_addr_cnt_axis_o => dbg_ddr_addr_cnt_axis,
dbg_ddr_addr_init_o => dbg_ddr_addr_init,
dbg_ddr_addr_max_o => dbg_ddr_addr_max
);
end generate;
......
hdl/modules/dbe_wishbone/wb_acq_core/xwb_acq_core.vhd
View file @ d01c6e95
......@@ -258,6 +258,15 @@ begin
axis_s2mm_cmd_tvalid_o => axis_s2mm_cmd_ma_o.tvalid,
axis_s2mm_cmd_tready_i => axis_s2mm_cmd_ma_i.tready,
axis_s2mm_rstn_o => axis_s2mm_cmd_ma_o.rstn,
axis_s2mm_halt_o => axis_s2mm_cmd_ma_o.halt,
axis_s2mm_halt_cmplt_i => axis_s2mm_cmd_ma_i.halt_cmplt,
axis_s2mm_allow_addr_req_o => axis_s2mm_cmd_ma_o.allow_addr_req,
axis_s2mm_addr_req_posted_i => axis_s2mm_cmd_ma_i.addr_req_posted,
axis_s2mm_wr_xfer_cmplt_i => axis_s2mm_cmd_ma_i.wr_xfer_cmplt,
axis_s2mm_ld_nxt_len_i => axis_s2mm_cmd_ma_i.ld_nxt_len,
axis_s2mm_wr_len_i => axis_s2mm_cmd_ma_i.wr_len,
axis_s2mm_pld_tdata_o => axis_s2mm_pld_ma_o.tdata,
axis_s2mm_pld_tkeep_o => axis_s2mm_pld_ma_o.tkeep,
axis_s2mm_pld_tlast_o => axis_s2mm_pld_ma_o.tlast,
......
hdl/modules/dbe_wishbone/wb_acq_core_mux/wb_acq_core_mux.vhd
View file @ d01c6e95
......@@ -173,6 +173,8 @@ architecture rtl of wb_acq_core_mux is
-- AXI Data mover signals
signal axi_rst_n_array : std_logic_vector(c_num_max_acq_cores-1 downto 0);
signal axis_s2mm_rst_n_array_or : std_logic_vector(c_num_max_acq_cores-1 downto 0);
signal axis_mm2s_rst_n_array_or : std_logic_vector(c_num_max_acq_cores-1 downto 0);
signal axis_mm2s_cmd_mo_array : t_axis_cmd_master_out_array(g_acq_num_cores-1 downto 0);
signal axis_mm2s_cmd_mi_array : t_axis_cmd_master_in_array(g_acq_num_cores-1 downto 0);
......@@ -300,6 +302,15 @@ begin
axis_s2mm_cmd_tvalid_o => axis_s2mm_cmd_mo_array(i).tvalid,
axis_s2mm_cmd_tready_i => axis_s2mm_cmd_mi_array(i).tready,
axis_s2mm_rstn_o => axis_s2mm_cmd_mo_array(i).rstn,
axis_s2mm_halt_o => axis_s2mm_cmd_mo_array(i).halt,
axis_s2mm_halt_cmplt_i => axis_s2mm_cmd_mi_array(i).halt_cmplt,
axis_s2mm_allow_addr_req_o => axis_s2mm_cmd_mo_array(i).allow_addr_req,
axis_s2mm_addr_req_posted_i => axis_s2mm_cmd_mi_array(i).addr_req_posted,
axis_s2mm_wr_xfer_cmplt_i => axis_s2mm_cmd_mi_array(i).wr_xfer_cmplt,
axis_s2mm_ld_nxt_len_i => axis_s2mm_cmd_mi_array(i).ld_nxt_len,
axis_s2mm_wr_len_i => axis_s2mm_cmd_mi_array(i).wr_len,
axis_s2mm_pld_tdata_o => axis_s2mm_pld_mo_array(i).tdata,
axis_s2mm_pld_tkeep_o => axis_s2mm_pld_mo_array(i).tkeep,
axis_s2mm_pld_tlast_o => axis_s2mm_pld_mo_array(i).tlast,
......@@ -336,15 +347,25 @@ begin
port map (
-- Memory Mapped to Stream
m_axi_mm2s_aclk => ext_clk_i,
m_axi_mm2s_aresetn => axi_rst_n_array(i),
m_axi_mm2s_aresetn => axis_mm2s_rst_n_array_or(i),
mm2s_err => open,
m_axis_mm2s_cmdsts_aclk => ext_clk_i,
m_axis_mm2s_cmdsts_aresetn => axi_rst_n_array(i),
m_axis_mm2s_cmdsts_aresetn => axis_mm2s_rst_n_array_or(i),
s_axis_mm2s_cmd_tvalid => axis_mm2s_cmd_mo_array(i).tvalid,
s_axis_mm2s_cmd_tready => axis_mm2s_cmd_mi_array(i).tready,
s_axis_mm2s_cmd_tdata => axis_mm2s_cmd_mo_array(i).tdata,
s2mm_halt => axis_s2mm_cmd_mo_array(i).halt,
s2mm_halt_cmplt => axis_s2mm_cmd_mi_array(i).halt_cmplt,
s2mm_allow_addr_req => axis_s2mm_cmd_mo_array(i).allow_addr_req,
s2mm_addr_req_posted => axis_s2mm_cmd_mi_array(i).addr_req_posted,
s2mm_wr_xfer_cmplt => axis_s2mm_cmd_mi_array(i).wr_xfer_cmplt,
s2mm_ld_nxt_len => axis_s2mm_cmd_mi_array(i).ld_nxt_len,
s2mm_wr_len => axis_s2mm_cmd_mi_array(i).wr_len,
s2mm_dbg_sel => c_axi_dbg_sel_zeros,
s2mm_dbg_data => open,
m_axis_mm2s_sts_tvalid => open,
m_axis_mm2s_sts_tready => c_axi_sl_one,
m_axis_mm2s_sts_tdata => open,
......@@ -374,10 +395,10 @@ begin
-- Stream to Memory Mapped
m_axi_s2mm_aclk => ext_clk_i,
m_axi_s2mm_aresetn => axi_rst_n_array(i),
m_axi_s2mm_aresetn => axis_s2mm_rst_n_array_or(i),
s2mm_err => open,
m_axis_s2mm_cmdsts_awclk => ext_clk_i,
m_axis_s2mm_cmdsts_aresetn => axi_rst_n_array(i),
m_axis_s2mm_cmdsts_aresetn => axis_s2mm_rst_n_array_or(i),
s_axis_s2mm_cmd_tvalid => axis_s2mm_cmd_mo_array(i).tvalid,
s_axis_s2mm_cmd_tready => axis_s2mm_cmd_mi_array(i).tready,
......@@ -413,6 +434,9 @@ begin
s_axis_s2mm_tvalid => axis_s2mm_pld_mo_array(i).tvalid,
s_axis_s2mm_tready => axis_s2mm_pld_mi_array(i).tready
);
axis_s2mm_rst_n_array_or(i) <= axi_rst_n_array(i) and axis_s2mm_cmd_mo_array(i).rstn;
axis_mm2s_rst_n_array_or(i) <= axi_rst_n_array(i);
end generate;
-- Assign dummy data to other unassigned records. We just need to assign signals
......
hdl/modules/dbe_wishbone/wb_dbe_periph/wb_dbe_periph.vhd
View file @ d01c6e95
......@@ -3,6 +3,7 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dbe_common_pkg.all;
use work.dbe_wishbone_pkg.all;
use work.wishbone_pkg.all;
......@@ -14,6 +15,7 @@ generic(
g_address_granularity : t_wishbone_address_granularity := WORD;
g_cntr_period : integer := 100000; -- 100MHz clock, ms granularity
g_num_leds : natural := 8;
g_with_led_heartbeat : t_boolean_array ; -- must match g_num_leds width
g_num_buttons : natural := 8
);
port(
......@@ -79,6 +81,9 @@ architecture rtl of wb_dbe_periph is
signal cbar_master_in : t_wishbone_master_in_array(c_slaves-1 downto 0);
signal cbar_master_out : t_wishbone_master_out_array(c_slaves-1 downto 0);
signal led_gpio_out_int : std_logic_vector(g_num_leds-1 downto 0) := (others => '0');
signal led_heartbeat_out_int : std_logic_vector(g_num_leds-1 downto 0) := (others => '0');
begin
cmp_interconnect : xwb_sdb_crossbar
......@@ -149,11 +154,35 @@ begin
--gpio_b : inout std_logic_vector(g_num_pins-1 downto 0);
gpio_out_o => led_out_o,
gpio_out_o => led_gpio_out_int,
gpio_in_i => led_in_i,
gpio_oen_o => led_oen_o
);
gen_leds_heartbeat : for i in g_num_leds-1 downto 0 generate
gen_with_heartbeat : if g_with_led_heartbeat(i) generate
-- Heartbeat module controls the Blue LED
cmp_blue_led : heartbeat
port map
(
clk_i => clk_sys_i,
rst_n_i => rst_n_i,
heartbeat_o => led_heartbeat_out_int(i)
);
end generate;
gen_without_heartbeat : if not g_with_led_heartbeat(i) generate
led_heartbeat_out_int(i) <= '0';
end generate;
end generate;
gen_leds_outputs : for i in g_num_leds-1 downto 0 generate
led_out_o(i) <= led_gpio_out_int(i) or led_heartbeat_out_int(i);
end generate;
-- Slave 2 is the Button driver
cmp_buttons : xwb_gpio_port
generic map(
......
hdl/modules/dbe_wishbone/wb_dbe_periph/xwb_dbe_periph.vhd
View file @ d01c6e95
......@@ -14,6 +14,7 @@ generic(
g_address_granularity : t_wishbone_address_granularity := WORD;
g_cntr_period : integer := 100000; -- 100MHz clock, ms granularity
g_num_leds : natural := 8;
g_with_led_heartbeat : t_boolean_array ; -- must match g_num_leds width
g_num_buttons : natural := 8
);
port(
......@@ -52,6 +53,7 @@ begin
g_address_granularity => g_address_granularity,
g_cntr_period => g_cntr_period,
g_num_leds => g_num_leds,
g_with_led_heartbeat => g_with_led_heartbeat,
g_num_buttons => g_num_buttons
)
port map(
......
hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wbgen/build_wb.sh
View file @ d01c6e95
#!/bin/bash
wbgen2 -V fmc_130m_4ch_regs.vhd -H record -p fmc_130m_4ch_regs_pkg.vhd -K ../../../../sim/regs/wb_fmc130m_4ch_regs.vh -s struct -C fmc130m_4ch_regs.h -f html -D doc/fmc130m_4ch_regs_wb.html fmc_130m_4ch_regs.wb
wbgen2 -V fmc_130m_4ch_regs.vhd -H record -p fmc_130m_4ch_regs_pkg.vhd -K ../../../../sim/regs/wb_fmc130m_4ch_regs.vh -s defines -C wb_fmc130m_4ch_regs.h -f html -D doc/fmc130m_4ch_regs_wb.html fmc_130m_4ch_regs.wb
hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wbgen/fmc_130m_4ch_regs.wb
View file @ d01c6e95
......@@ -5,101 +5,6 @@ peripheral {
prefix = "wb_fmc_130m_4ch_csr";
reg {
name = "FMC Status";
prefix = "fmc_status";
field {
name = "FMC Present";
prefix = "prsnt";
description = "FMC PRSNT_M2C Pin\n0 - FMC card present\n1 - no FMC card on carrier";
type = BIT;
--size = 1;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Power Good from mezzanine";
prefix = "pg_m2c";
description = "FMC Power Good Pin\nNot used";
type = BIT;
--size = 1;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Clock Direction";
prefix = "clk_dir";
description = "Clock direction (RES1)";
type = BIT;
--size = 1;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Firware ID";
prefix = "firmware_id";
description = "Should be 0x01332A11 on read (20130321)";
type = SLV;
size = 29;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Trigger control";
prefix = "trigger";
field {
name = "DIR";
prefix = "dir";
description = "Trigger direction\n0 - output\n1 - input";
type = BIT;
--size = 1;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Termination Control";
prefix = "term";
description = "Trigger termination 50 ohm\n0 - disable\n1 - enable";
type = BIT;
--size = 1;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Trigger Value";
prefix = "trig_val";
description = "Trigger value (when used in output mode)";
type = BIT;
--size = 1;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's.";
prefix = "reserved";
type = SLV;
size = 29;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "ADC LTC2208 control register (4 chips)";
prefix = "adc";
......@@ -156,117 +61,6 @@ peripheral {
};
reg {
name = "Clock distribution control register";
prefix = "clk_distrib";
field {
name = "SI571_OE";
prefix = "si571_oe";
description = "Si571 output enable pin, check datasheet for proper voltage standard and signal polarity";
type = BIT;
--size = 1;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "PLL_FUNCTION";
prefix = "pll_function";
description = "AD9510 function pin (behaviour depends on configuration of chip, output from FPGA)";
type = BIT;
--size = 1;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "PLL_STATUS";
prefix = "pll_status";
description = "AD9510 status pin - for monitoring PLL status and sync (behaviour depends on configuration of chip, input to FPGA)";
type = BIT;
--size = 1;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "CLK_SEL";
prefix = "clk_sel";
description = "TS3USB221 clock select (for FMC REFIN line)\n0 - clock from external source (MMCX J4)\n1 - clock from FPGA (FMC_CLK line)";
type = BIT;
--size = 1;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's.";
prefix = "reserved";
type = SLV;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Monitor and FMC status control register";
prefix = "monitor";
field {
name = "Temperate Alarm";
prefix = "temp_alarm";
description = "Temperature alarm from LM75 chips";
type = BIT;
--size = 1;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Led 1";
prefix = "led1";
description = "FMC LED1 (blue) - configuration in progress indicator\n0 - LED off\1 - LED on";
type = BIT;
--size = 1;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Led 2";
prefix = "led2";
description = "FMC LED2 (red) - data acquisition in progress indicator\n0 - LED off\1 - LED on";
type = BIT;
--size = 1;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Led 3";
prefix = "led3";
description = "FMC LED3 (green) - trigger status indicator\n0 - LED off\1 - LED on";
type = BIT;
--size = 1;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's.";
prefix = "reserved";
type = SLV;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "FPGA control";
......@@ -344,13 +138,13 @@ peripheral {
};
field {
name = "Enable test data";
description = "Write the address counter value instead of ADC data to Wishbone Streaming Interface";
prefix = "test_data_en";
name = "Temperature Alarm";
prefix = "temp_alarm";
description = "Temperature alarm from LM75 chips";
type = BIT;
align = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
--size = 1;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
......
hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wbgen/fmc_130m_4ch_regs_pkg.vhd
View file @ d01c6e95
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fmc_130m_4ch_regs_pkg.vhd
-- Author : auto-generated by wbgen2 from fmc_130m_4ch_regs.wb
-- Created : Mon Aug 26 18:37:02 2013
-- Created : Mon Apr 18 15:10:45 2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_130m_4ch_regs.wb
......@@ -20,21 +20,13 @@ package wb_fmc_130m_4ch_csr_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_wb_fmc_130m_4ch_csr_in_registers is record
fmc_status_prsnt_i : std_logic;
fmc_status_pg_m2c_i : std_logic;
fmc_status_clk_dir_i : std_logic;
fmc_status_firmware_id_i : std_logic_vector(28 downto 0);
trigger_reserved_i : std_logic_vector(28 downto 0);
adc_reserved_i : std_logic_vector(27 downto 0);
clk_distrib_pll_status_i : std_logic;
clk_distrib_reserved_i : std_logic_vector(27 downto 0);
monitor_temp_alarm_i : std_logic;
monitor_reserved_i : std_logic_vector(27 downto 0);
fpga_ctrl_fmc_idelay0_rdy_i : std_logic;
fpga_ctrl_fmc_idelay1_rdy_i : std_logic;
fpga_ctrl_fmc_idelay2_rdy_i : std_logic;
fpga_ctrl_fmc_idelay3_rdy_i : std_logic;
fpga_ctrl_reserved1_i : std_logic_vector(1 downto 0);
fpga_ctrl_temp_alarm_i : std_logic;
fpga_ctrl_reserved2_i : std_logic_vector(22 downto 0);
idelay0_cal_val_i : std_logic_vector(4 downto 0);
idelay0_cal_reserved_i : std_logic_vector(8 downto 0);
......@@ -54,21 +46,13 @@ package wb_fmc_130m_4ch_csr_wbgen2_pkg is
end record;
constant c_wb_fmc_130m_4ch_csr_in_registers_init_value: t_wb_fmc_130m_4ch_csr_in_registers := (
fmc_status_prsnt_i => '0',
fmc_status_pg_m2c_i => '0',
fmc_status_clk_dir_i => '0',
fmc_status_firmware_id_i => (others => '0'),
trigger_reserved_i => (others => '0'),
adc_reserved_i => (others => '0'),
clk_distrib_pll_status_i => '0',
clk_distrib_reserved_i => (others => '0'),
monitor_temp_alarm_i => '0',
monitor_reserved_i => (others => '0'),
fpga_ctrl_fmc_idelay0_rdy_i => '0',
fpga_ctrl_fmc_idelay1_rdy_i => '0',
fpga_ctrl_fmc_idelay2_rdy_i => '0',
fpga_ctrl_fmc_idelay3_rdy_i => '0',
fpga_ctrl_reserved1_i => (others => '0'),
fpga_ctrl_temp_alarm_i => '0',
fpga_ctrl_reserved2_i => (others => '0'),
idelay0_cal_val_i => (others => '0'),
idelay0_cal_reserved_i => (others => '0'),
......@@ -90,22 +74,12 @@ package wb_fmc_130m_4ch_csr_wbgen2_pkg is
-- Output registers (WB slave -> user design)
type t_wb_fmc_130m_4ch_csr_out_registers is record
trigger_dir_o : std_logic;
trigger_term_o : std_logic;
trigger_trig_val_o : std_logic;
adc_rand_o : std_logic;
adc_dith_o : std_logic;
adc_shdn_o : std_logic;
adc_pga_o : std_logic;
clk_distrib_si571_oe_o : std_logic;
clk_distrib_pll_function_o : std_logic;
clk_distrib_clk_sel_o : std_logic;
monitor_led1_o : std_logic;
monitor_led2_o : std_logic;
monitor_led3_o : std_logic;
fpga_ctrl_fmc_idelay_rst_o : std_logic;
fpga_ctrl_fmc_fifo_rst_o : std_logic;
fpga_ctrl_test_data_en_o : std_logic;
idelay0_cal_update_o : std_logic;
idelay0_cal_line_o : std_logic_vector(16 downto 0);
idelay0_cal_val_o : std_logic_vector(4 downto 0);
......@@ -128,22 +102,12 @@ package wb_fmc_130m_4ch_csr_wbgen2_pkg is
end record;
constant c_wb_fmc_130m_4ch_csr_out_registers_init_value: t_wb_fmc_130m_4ch_csr_out_registers := (
trigger_dir_o => '0',
trigger_term_o => '0',
trigger_trig_val_o => '0',
adc_rand_o => '0',
adc_dith_o => '0',
adc_shdn_o => '0',
adc_pga_o => '0',
clk_distrib_si571_oe_o => '0',
clk_distrib_pll_function_o => '0',
clk_distrib_clk_sel_o => '0',
monitor_led1_o => '0',
monitor_led2_o => '0',
monitor_led3_o => '0',
fpga_ctrl_fmc_idelay_rst_o => '0',
fpga_ctrl_fmc_fifo_rst_o => '0',
fpga_ctrl_test_data_en_o => '0',
idelay0_cal_update_o => '0',
idelay0_cal_line_o => (others => '0'),
idelay0_cal_val_o => (others => '0'),
......@@ -172,11 +136,11 @@ end package;
package body wb_fmc_130m_4ch_csr_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if(x = 'X' or x = 'U') then
return '0';
if x = '1' then
return '1';
else
return x;
end if;
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
......@@ -193,21 +157,13 @@ end function;
function "or" (left, right: t_wb_fmc_130m_4ch_csr_in_registers) return t_wb_fmc_130m_4ch_csr_in_registers is
variable tmp: t_wb_fmc_130m_4ch_csr_in_registers;
begin
tmp.fmc_status_prsnt_i := f_x_to_zero(left.fmc_status_prsnt_i) or f_x_to_zero(right.fmc_status_prsnt_i);
tmp.fmc_status_pg_m2c_i := f_x_to_zero(left.fmc_status_pg_m2c_i) or f_x_to_zero(right.fmc_status_pg_m2c_i);
tmp.fmc_status_clk_dir_i := f_x_to_zero(left.fmc_status_clk_dir_i) or f_x_to_zero(right.fmc_status_clk_dir_i);
tmp.fmc_status_firmware_id_i := f_x_to_zero(left.fmc_status_firmware_id_i) or f_x_to_zero(right.fmc_status_firmware_id_i);
tmp.trigger_reserved_i := f_x_to_zero(left.trigger_reserved_i) or f_x_to_zero(right.trigger_reserved_i);
tmp.adc_reserved_i := f_x_to_zero(left.adc_reserved_i) or f_x_to_zero(right.adc_reserved_i);
tmp.clk_distrib_pll_status_i := f_x_to_zero(left.clk_distrib_pll_status_i) or f_x_to_zero(right.clk_distrib_pll_status_i);
tmp.clk_distrib_reserved_i := f_x_to_zero(left.clk_distrib_reserved_i) or f_x_to_zero(right.clk_distrib_reserved_i);
tmp.monitor_temp_alarm_i := f_x_to_zero(left.monitor_temp_alarm_i) or f_x_to_zero(right.monitor_temp_alarm_i);
tmp.monitor_reserved_i := f_x_to_zero(left.monitor_reserved_i) or f_x_to_zero(right.monitor_reserved_i);
tmp.fpga_ctrl_fmc_idelay0_rdy_i := f_x_to_zero(left.fpga_ctrl_fmc_idelay0_rdy_i) or f_x_to_zero(right.fpga_ctrl_fmc_idelay0_rdy_i);
tmp.fpga_ctrl_fmc_idelay1_rdy_i := f_x_to_zero(left.fpga_ctrl_fmc_idelay1_rdy_i) or f_x_to_zero(right.fpga_ctrl_fmc_idelay1_rdy_i);
tmp.fpga_ctrl_fmc_idelay2_rdy_i := f_x_to_zero(left.fpga_ctrl_fmc_idelay2_rdy_i) or f_x_to_zero(right.fpga_ctrl_fmc_idelay2_rdy_i);
tmp.fpga_ctrl_fmc_idelay3_rdy_i := f_x_to_zero(left.fpga_ctrl_fmc_idelay3_rdy_i) or f_x_to_zero(right.fpga_ctrl_fmc_idelay3_rdy_i);
tmp.fpga_ctrl_reserved1_i := f_x_to_zero(left.fpga_ctrl_reserved1_i) or f_x_to_zero(right.fpga_ctrl_reserved1_i);
tmp.fpga_ctrl_temp_alarm_i := f_x_to_zero(left.fpga_ctrl_temp_alarm_i) or f_x_to_zero(right.fpga_ctrl_temp_alarm_i);
tmp.fpga_ctrl_reserved2_i := f_x_to_zero(left.fpga_ctrl_reserved2_i) or f_x_to_zero(right.fpga_ctrl_reserved2_i);
tmp.idelay0_cal_val_i := f_x_to_zero(left.idelay0_cal_val_i) or f_x_to_zero(right.idelay0_cal_val_i);
tmp.idelay0_cal_reserved_i := f_x_to_zero(left.idelay0_cal_reserved_i) or f_x_to_zero(right.idelay0_cal_reserved_i);
......
hdl/modules/dbe_wishbone/wb_fmc250m_4ch/Manifest.py 0 → 100644
View file @ d01c6e95
files = [ "wb_fmc250m_4ch.vhd",
"xwb_fmc250m_4ch.vhd",
"wbgen/wb_fmc250m_4ch_regs_pkg.vhd",
"wbgen/wb_fmc250m_4ch_regs.vhd"
];
hdl/modules/dbe_wishbone/wb_fmc250m_4ch/wb_fmc250m_4ch.vhd 0 → 100644
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hdl/modules/dbe_wishbone/wb_fmc250m_4ch/wbgen/build_wb.sh 0 → 100755
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#!/bin/bash
wbgen2 -V wb_fmc250m_4ch_regs.vhd -H record -p wb_fmc250m_4ch_regs_pkg.vhd -K ../../../../sim/regs/wb_fmc250m_4ch_regs.vh -s defines -C wb_fmc250m_4ch_regs.h -f html -D doc/fmc250m_4ch_regs_wb.html wb_fmc250m_4ch_regs.wb
hdl/modules/dbe_wishbone/wb_fmc250m_4ch/xwb_fmc250m_4ch.vhd 0 → 100644
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hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd
View file @ d01c6e95
......@@ -1555,13 +1555,12 @@ begin
-- Green FMC front led
cmp_led1_extende_pulse : gc_extend_pulse
generic map (
-- Input clock = 100MHz
-- 20000000 clock pulses = 0.2s pulse
-- 20000000 clock pulses
g_width => 20000000
)
port map (
clk_i => sys_clk_i,
rst_n_i => sys_rst_sync_n,
clk_i => fs_clk(c_ref_clk),
rst_n_i => fs_rst_sync_n(c_ref_clk),
-- input pulse (synchronous to clk_i)
pulse_i => m2c_trig_sync,
-- extended output pulse
......
hdl/modules/dbe_wishbone/wb_fmc_active_clk/Manifest.py 0 → 100644
View file @ d01c6e95
files = [ "wb_fmc_active_clk.vhd",
"xwb_fmc_active_clk.vhd",
"wbgen/wb_fmc_active_clk_regs_pkg.vhd",
"wbgen/wb_fmc_active_clk_regs.vhd"
];
hdl/modules/dbe_wishbone/wb_fmc_active_clk/wbgen/build_wb.sh 0 → 100755
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#!/bin/bash
wbgen2 -V wb_fmc_active_clk_regs.vhd -H record -p wb_fmc_active_clk_regs_pkg.vhd -K ../../../../sim/regs/wb_fmc_active_clk_regs.vh -s defines -C wb_fmc_active_clk_regs.h -f html -D doc/fmc_active_clk_regs_wb.html wb_fmc_active_clk_regs.wb
hdl/modules/dbe_wishbone/wb_fmc_active_clk/wbgen/wb_fmc_active_clk_regs.h 0 → 100644
View file @ d01c6e95
/*
Register definitions for slave core: FMC Active Clock registers
* File : wb_fmc_active_clk_regs.h
* Author : auto-generated by wbgen2 from wb_fmc_active_clk_regs.wb
* Created : Mon Apr 18 10:20:28 2016
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmc_active_clk_regs.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_WB_FMC_ACTIVE_CLK_REGS_WB
#define __WBGEN2_REGDEFS_WB_FMC_ACTIVE_CLK_REGS_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Clock distribution control register */
/* definitions for field: Si 571 Output Enable in reg: Clock distribution control register */
#define WB_FMC_ACTIVE_CLK_CSR_CLK_DISTRIB_SI571_OE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: AD9510 PLL function in reg: Clock distribution control register */
#define WB_FMC_ACTIVE_CLK_CSR_CLK_DISTRIB_PLL_FUNCTION WBGEN2_GEN_MASK(1, 1)
/* definitions for field: AD9510 PLL Status in reg: Clock distribution control register */
#define WB_FMC_ACTIVE_CLK_CSR_CLK_DISTRIB_PLL_STATUS WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Reference Clock Selection in reg: Clock distribution control register */
#define WB_FMC_ACTIVE_CLK_CSR_CLK_DISTRIB_CLK_SEL WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Reserved in reg: Clock distribution control register */
#define WB_FMC_ACTIVE_CLK_CSR_CLK_DISTRIB_RESERVED_MASK WBGEN2_GEN_MASK(4, 28)
#define WB_FMC_ACTIVE_CLK_CSR_CLK_DISTRIB_RESERVED_SHIFT 4
#define WB_FMC_ACTIVE_CLK_CSR_CLK_DISTRIB_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 4, 28)
#define WB_FMC_ACTIVE_CLK_CSR_CLK_DISTRIB_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 4, 28)
/* definitions for register: Dummy */
/* definitions for field: Reserved in reg: Dummy */
#define WB_FMC_ACTIVE_CLK_CSR_DUMMY_RESERVED_MASK WBGEN2_GEN_MASK(0, 32)
#define WB_FMC_ACTIVE_CLK_CSR_DUMMY_RESERVED_SHIFT 0
#define WB_FMC_ACTIVE_CLK_CSR_DUMMY_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WB_FMC_ACTIVE_CLK_CSR_DUMMY_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* [0x0]: REG Clock distribution control register */
#define WB_FMC_ACTIVE_CLK_CSR_REG_CLK_DISTRIB 0x00000000
/* [0x4]: REG Dummy */
#define WB_FMC_ACTIVE_CLK_CSR_REG_DUMMY 0x00000004
#endif
hdl/modules/dbe_wishbone/wb_fmc_active_clk/wbgen/wb_fmc_active_clk_regs.vhd 0 → 100644
View file @ d01c6e95
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for FMC Active Clock registers
---------------------------------------------------------------------------------------
-- File : wb_fmc_active_clk_regs.vhd
-- Author : auto-generated by wbgen2 from wb_fmc_active_clk_regs.wb
-- Created : Mon Apr 18 10:20:28 2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmc_active_clk_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wb_fmc_active_clk_csr_wbgen2_pkg.all;
entity wb_fmc_active_clk_csr is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(0 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
regs_i : in t_wb_fmc_active_clk_csr_in_registers;
regs_o : out t_wb_fmc_active_clk_csr_out_registers
);
end wb_fmc_active_clk_csr;
architecture syn of wb_fmc_active_clk_csr is
signal wb_fmc_active_clk_csr_clk_distrib_si571_oe_int : std_logic ;
signal wb_fmc_active_clk_csr_clk_distrib_pll_function_int : std_logic ;
signal wb_fmc_active_clk_csr_clk_distrib_clk_sel_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(0 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
wb_fmc_active_clk_csr_clk_distrib_si571_oe_int <= '0';
wb_fmc_active_clk_csr_clk_distrib_pll_function_int <= '0';
wb_fmc_active_clk_csr_clk_distrib_clk_sel_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(0) is
when '0' =>
if (wb_we_i = '1') then
wb_fmc_active_clk_csr_clk_distrib_si571_oe_int <= wrdata_reg(0);
wb_fmc_active_clk_csr_clk_distrib_pll_function_int <= wrdata_reg(1);
wb_fmc_active_clk_csr_clk_distrib_clk_sel_int <= wrdata_reg(3);
end if;
rddata_reg(0) <= wb_fmc_active_clk_csr_clk_distrib_si571_oe_int;
rddata_reg(1) <= wb_fmc_active_clk_csr_clk_distrib_pll_function_int;
rddata_reg(2) <= regs_i.clk_distrib_pll_status_i;
rddata_reg(3) <= wb_fmc_active_clk_csr_clk_distrib_clk_sel_int;
rddata_reg(31 downto 4) <= regs_i.clk_distrib_reserved_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when '1' =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.dummy_reserved_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- Si 571 Output Enable
regs_o.clk_distrib_si571_oe_o <= wb_fmc_active_clk_csr_clk_distrib_si571_oe_int;
-- AD9510 PLL function
regs_o.clk_distrib_pll_function_o <= wb_fmc_active_clk_csr_clk_distrib_pll_function_int;
-- AD9510 PLL Status
-- Reference Clock Selection
regs_o.clk_distrib_clk_sel_o <= wb_fmc_active_clk_csr_clk_distrib_clk_sel_int;
-- Reserved
-- Reserved
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
hdl/modules/dbe_wishbone/wb_fmc_adc_common/Manifest.py 0 → 100644
View file @ d01c6e95
files = [ "wbgen/wb_fmc_adc_common_regs_pkg.vhd",
"wbgen/wb_fmc_adc_common_regs.vhd"
];
hdl/modules/dbe_wishbone/wb_fmc_adc_common/wbgen/build_wb.sh 0 → 100755
View file @ d01c6e95
#!/bin/bash
wbgen2 -V wb_fmc_adc_common_regs.vhd -H record -p wb_fmc_adc_common_regs_pkg.vhd -K ../../../../sim/regs/wb_fmc_adc_common_regs.vh -s defines -C wb_fmc_adc_common_regs.h -f html -D doc/fmc_adc_common_regs_wb.html wb_fmc_adc_common_regs.wb
hdl/modules/dbe_wishbone/wb_trigger/Manifest.py 0 → 100644
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files = [
"trigger_pkg.vhd",
"trigger_resolver.vhd",
"wb_trigger.vhd",
"xwb_trigger.vhd"
];
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files = [
"wb_trigger_iface.vhd",
"xwb_trigger_iface.vhd",
"wbgen/wb_trigger_iface_regs.vhd",
"wbgen/wb_trigger_iface_regs_pkg.vhd"];
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#!/bin/bash
wbgen2 -V wb_trigger_iface_regs.vhd -H record -p wb_trigger_iface_regs_pkg.vhd -K ../../../../sim/regs/wb_trigger_iface_regs.vh -s defines -C wb_trigger_iface_regs.h -f html -D doc/wb_trigger_iface_regs_wb.html wb_trigger_iface.wb
hdl/modules/dbe_wishbone/wb_trigger_mux/Manifest.py 0 → 100644
View file @ d01c6e95
files = [
"wb_trigger_mux.vhd",
"xwb_trigger_mux.vhd",
"wbgen/wb_trigger_mux_regs.vhd",
"wbgen/wb_trigger_mux_regs_pkg.vhd"];
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#!/bin/bash
wbgen2 -V wb_trigger_mux_regs.vhd -H record -p wb_trigger_mux_regs_pkg.vhd -K ../../../../sim/regs/wb_trigger_mux_regs.vh -s defines -C wb_trigger_mux_regs.h -f html -D doc/wb_trigger_mux_regs_wb.html wb_trigger_mux.wb
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hdl/modules/fmc_adc_common/fmc_adc_clk.vhd
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