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Beam Positoning Monitor - Gateware
Commit b130cef4 authored by Lucas Russo's avatar Lucas Russo
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README: update sim/syn/project instructions 

The README was very outdated and the
simulations, synthesis and project organization
ahve chenged since then.
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README
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==============================================================================
# Sirius Beam Position Monitor FPGA firmware
Repository containing the Beam Position Monitor FPGA firmware and
software.
==============================================================================
Folder Hierarchy organization:
## Project Folder Organization
*
|
......@@ -48,134 +43,71 @@ Folder Hierarchy organization:
| |
| |-- top:
| Top design modules.
|
|-- sw:
| | Software related to interfacing the BPM carrier board with a PC
| | via PCIe.
| |
| |-- drivers:
| | Linux Kernel code for device drivers
| |
| |-- include:
| | Header files for device structures and definitions
| |
| |-- lib:
| Utilities and API functions exported by the drivers
|
|-- embedded-sw (based on the original project by Alessandrio Rubini
| | and others <http://www.ohwr.org/projects/wrpc-sw>):
| |
| | Embedded software that runs inside the LM32 softcore processor.
| |
| |-- arch:
| | Architecture specific code, like linker scripts and boot code.
| |
| |-- boards:
| | Board specific parameters and initialization.
| |
| |-- dev:
| | Device specific code, such as UART, GPIO and DMA interfaces
| |
| |-- include:
| | | General headers, mostly API device headers.
| | |
| | |-- hw:
| | | Device specific registers and structures. This definitions
| | | are included by the more general headers located inside
| | | the "include" top directory.
| | |
| | |-- memmgr:
| | Memory pool for "dynamic" allocated memory.
| |
| |-- lib:
| | Utilities and general functions, such as the memmgr subsystem
| | and a printf-like function.
| |
| |-- tests:
| | Folder dedicated to software testing.
| |
| |-- tools:
| | General tools for generating RAM loadable file by the firmware
| | FPGA.
==============================================================================
Cloning this repository:
## Cloning Instructions
This repository makes use of git submodules, located at 'hdl/ip_cores' folder:
hdl/ip_cores/general-cores
hdl/ip_cores/etherbone-core
hdl/ip_cores/dsp-cores
hdl/ip_cores/infra-cores
To clone the whole repository use the following command:
$ git clone --recursive git://github.com/lerwys/bpm-sw.git (read only)
or
$ git clone --recursive git@github.com:lerwys/bpm-sw.git (read+write)
For older versions of Git (<1.6.5), use the following:
git clone --recursive git://github.com/lnls-dig/bpm-gw.git (read only)
$ git clone git://github.com/lerwys/bpm-sw.git
or
$ git clone git@github.com:lerwys/bpm-sw.git
$ git submodule init
$ git submodule update
To update each submodule within this project use:
$ git submodule foreach git rebase origin master
==============================================================================
git clone --recursive git@github.com:lnls-dig/bpm-gw.git (read+write)
Simulation instructions:
For older versions of Git (<1.6.5), use the following:
Go to a testbench directory. It must have a top manifest file:
cd /hdl/testbench/path_to_testbench
git clone git://github.com/lnls-dig/bpm-gw.git
Run the following commands. You must have hdlmake2 command available
in your PATH environment variable.
or
Create the (ISim) simualation makefile
git clone git@github.com:lnls-dig/bpm-gw.git
$ hdlmake2 --make-isim
git submodule init
git submodule update
Compile the project
To update each submodule within this project use:
$ make
git submodule foreach git rebase origin master
Create the simulation executable ELF file
## Simulation Instructions
$ make fuse TOP_MODULE=<top_level_testbench_module_without_the_extension>
Go to a testbench directory. It must have a top manifest file:
Execute the simulation with GUI and aditional commands
cd hdl/testbench/path_to_testbench
$ ./isim_proj -view wave.wcfg -tclbatch isim_cmd -gui
Run the following commands. You must have hdlmake command available
in your PATH environment variable.
==============================================================================
Create the simualation makefile
Synthesis instructions:
hdlmake
Go to a syn directory. It must have a top manifest file:
cd /hdl/top/path_to_top_design
Compile the project
Run the following commands. You must have hdlmake2 command available
in your PATH environment variable.
make
Create the synthesis makefile and an ISE project
Execute the simulation with GUI and aditional commands
$ hdlmake2 --make-ise --ise-proj
vsim -do run.do &
Compile the source files locally
## Synthesis Instructions
$ make local
Go to a syn directory. It must have a synthesis manifest file:
Load the generated .bit file with iMPACT or other tool
cd hdl/syn/path_to_syn_design
$ impact
Run the following commands. You must have hdlmake command available
in your PATH environment variable.
==============================================================================
./build_synthesis_local.sh
Known Issues:
## Known Issues
wb_fmc150/sim/: This folder containts behavioral simulation models
for memories (ROMs). However, the xilinx initialization file (.mif)
......
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