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Beam Positoning Monitor - Gateware
Commit 741e251e authored by Lucas Russo's avatar Lucas Russo
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update initial design 2

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COPYING
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GNU LESSER GENERAL PUBLIC LICENSE
Version 3, 29 June 2007
Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>
Everyone is permitted to copy and distribute verbatim copies
of this license document, but changing it is not allowed.
This version of the GNU Lesser General Public License incorporates
the terms and conditions of version 3 of the GNU General Public
License, supplemented by the additional permissions listed below.
0. Additional Definitions.
As used herein, "this License" refers to version 3 of the GNU Lesser
General Public License, and the "GNU GPL" refers to version 3 of the GNU
General Public License.
"The Library" refers to a covered work governed by this License,
other than an Application or a Combined Work as defined below.
An "Application" is any work that makes use of an interface provided
by the Library, but which is not otherwise based on the Library.
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A "Combined Work" is a work produced by combining or linking an
Application with the Library. The particular version of the Library
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5. Combined Libraries.
You may place library facilities that are a work based on the
Library side by side in a single library together with other library
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choice, if you do both of the following:
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b) Give prominent notice with the combined library that part of it
is a work based on the Library, and explaining where to find the
accompanying uncombined form of the same work.
6. Revised Versions of the GNU Lesser General Public License.
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of the GNU Lesser General Public License from time to time. Such new
versions will be similar in spirit to the present version, but may
differ in detail to address new problems or concerns.
Each version is given a distinguishing version number. If the
Library as you received it specifies that a certain numbered version
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\ No newline at end of file
README
View file @ 741e251e
==========================================================
Repository containing the Beam Position Monitor FPGA firmware and
software.
==========================================================
Folder Hierarchy organization:
TODO
==========================================================
hdl/README
View file @ 741e251e
Folder containing all the BPM FPGA firmware and related tests
==========================================================
Folder containing all o the BPM FPGA firmware, testbenches
and related test software
==========================================================
hdl/modules/custom_wishbone/wb_fmc150/Manifest.py
View file @ 741e251e
......@@ -3,5 +3,4 @@ modules = { "local" : [
"fmc150",
"netlist" ] };
files = ["wb_fmc150.vhd", "xwb_fmc150.vhd", "xfmc150_regs_pkg.vhd", "wb_fmc150_port.vhd",
"xwb_fmc150.vhd" ];
files = ["wb_fmc150.vhd", "xwb_fmc150.vhd", "xfmc150_regs_pkg.vhd", "wb_fmc150_port.vhd" ];
hdl/modules/custom_wishbone/wb_fmc150/doc/xfmc150_regs_wb.html
View file @ 741e251e
......@@ -703,23 +703,6 @@ fmc150_flgs_out_spi_busy_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc150_flgs_out_pll_status_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc150_flgs_out_adc_clk_locked_i
......@@ -728,23 +711,6 @@ fmc150_flgs_out_adc_clk_locked_i
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc150_flgs_out_fmc_prst_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
</table>
<h3><a name="sect_3_0">3. Register description</a></h3>
......@@ -2816,14 +2782,14 @@ FLGS_OUT
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
FMC_PRST
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
ADC_CLK_LOCKED
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
PLL_STATUS
ADC_CLK_LOCKED
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
SPI_BUSY
......@@ -2836,17 +2802,9 @@ SPI_BUSY
</b>[<i>read-only</i>]: SPI Busy
<br>read 1: spi busy.<br> read 0: spi idle
<li><b>
PLL_STATUS
</b>[<i>read-only</i>]: CDCE72010 PLL Status
<br>read 1: PLL locked.<br> read 0: PLL not locked
<li><b>
ADC_CLK_LOCKED
</b>[<i>read-only</i>]: FPGA ADC clock locked
<br>read 1: FPGA ADC PLL locked.<br> read 0: FPGA ADC PLL not locked
<li><b>
FMC_PRST
</b>[<i>read-only</i>]: FMC present
<br>read 1: FMC present.<br> read 0: FMC not present
</ul>
......
hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_adc_if.vhd
View file @ 741e251e
......@@ -10,6 +10,9 @@ use work.adc_pkg.all;
entity fmc150_adc_if is
generic (
g_sim : boolean := false
);
port
(
clk_200MHz_i : in std_logic;
......@@ -47,18 +50,27 @@ architecture rtl of fmc150_adc_if is
signal s_adc_chb_sdr : std_logic_vector(13 downto 0);
begin
-- ADC data strobe (channel A and B) with adjustable delay
cmp_adc_str: strobe_lvds
port map
(
clk_ctrl_i => clk_100MHz_i,
strobe_p_i => str_p_i,
strobe_n_i => str_n_i,
strobe_o => s_adc_str_dly,
ctrl_delay_update_i => delay_update_i,
ctrl_delay_value_i => str_cntvalue_i,
ctrl_delay_value_o => str_cntvalue_o
);
-- Synthesis Only!
gen_adc_clk : if (g_sim = false) generate
-- ADC data strobe (channel A and B) with adjustable delay
cmp_adc_str: strobe_lvds
port map
(
clk_ctrl_i => clk_100MHz_i,
strobe_p_i => str_p_i,
strobe_n_i => str_n_i,
strobe_o => s_adc_str_dly,
ctrl_delay_update_i => delay_update_i,
ctrl_delay_value_i => str_cntvalue_i,
ctrl_delay_value_o => str_cntvalue_o
);
end generate;
-- Simulation Only!
gen_adc_clk_sim : if (g_sim = true) generate
s_adc_str_dly <= str_p_i and str_n_i;
end generate;
-- s_adc_str_dly is a regional clock driven by BUFR.
-- Must go through a BUFG before other components (BPM DDC)
......@@ -109,4 +121,4 @@ begin
ctrl_delay_value_i => chb_cntvalue_i
);
end rtl;
\ No newline at end of file
end rtl;
hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_pkg.vhd
View file @ 741e251e
......@@ -70,6 +70,9 @@ package fmc150_pkg is
end component;
component fmc150_adc_if is
generic (
g_sim : boolean := false
);
port
(
clk_200MHz_i : in std_logic;
......@@ -386,4 +389,4 @@ package fmc150_pkg is
);
end component;
end fmc150_pkg;
\ No newline at end of file
end fmc150_pkg;
hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_testbench.vhd
View file @ 741e251e
......@@ -8,8 +8,10 @@ use unisim.vcomponents.all;
library work;
use work.fmc150_pkg.all;
entity fmc150_testbench is
generic(
g_sim : boolean := false
);
port
(
rst : in std_logic;
......@@ -28,10 +30,10 @@ port
dac_frame_p : out std_logic;
dac_frame_n : out std_logic;
txenable : out std_logic;
clk_to_fpga_p : in std_logic;
clk_to_fpga_n : in std_logic;
ext_trigger_p : in std_logic;
ext_trigger_n : in std_logic;
--clk_to_fpga_p : in std_logic;
--clk_to_fpga_n : in std_logic;
--ext_trigger_p : in std_logic;
--ext_trigger_n : in std_logic;
spi_sclk : out std_logic;
spi_sdata : out std_logic;
rd_n_wr : in std_logic;
......@@ -113,116 +115,140 @@ architecture rtl of fmc150_testbench is
signal dac_din_d : std_logic_vector(15 downto 0);
signal adc_str_fbin, adc_str_out, adc_str_2x_out, adc_str_fbout : std_logic;
-- simulation only
signal toggle_ff_q : std_logic := '0';
begin
-- I/O delay control
cmp_idelayctrl : idelayctrl
port map
(
rst => rst,
refclk => clk_200MHz,
rdy => open
);
-- Synthesis Only
gen_clk : if (g_sim = false) generate
-- I/O delay control
cmp_idelayctrl : idelayctrl
port map
(
rst => rst,
refclk => clk_200MHz,
rdy => open
);
-- ADC Clock PLL
cmp_mmcm_adc : MMCM_ADV
generic map
(
BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
CLOCK_HOLD => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
--CLKFBOUT_MULT_F => 16.000,
CLKFBOUT_MULT_F => 8.000,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
--CLKOUT0_DIVIDE_F => 16.000,
CLKOUT0_DIVIDE_F => 8.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
--CLKOUT1_DIVIDE => 8,
CLKOUT1_DIVIDE => 4,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_USE_FINE_PS => FALSE,
-- 61.44 MHZ input clock
--CLKIN1_PERIOD => 16.276,
-- 122.88 MHZ input clock
CLKIN1_PERIOD => 8.138,
REF_JITTER1 => 0.010
)
port map
(
-- Output clocks
CLKFBOUT => adc_str_fbout,
CLKFBOUTB => open,
CLKOUT0 => adc_str_out,
CLKOUT0B => open,
CLKOUT1 => adc_str_2x_out,
CLKOUT1B => open,
CLKOUT2 => open,
CLKOUT2B => open,
CLKOUT3 => open,
CLKOUT3B => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKOUT6 => open,
-- Input clock control
CLKFBIN => adc_str_fbin,
CLKIN1 => adc_str,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => mmcm_adc_locked,
CLKINSTOPPED => open,
CLKFBSTOPPED => open,
PWRDWN => '0',
RST => rst
);
-- ADC Clock PLL
cmp_mmcm_adc : MMCM_ADV
generic map
(
BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
CLOCK_HOLD => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
--CLKFBOUT_MULT_F => 16.000,
CLKFBOUT_MULT_F => 8.000,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
--CLKOUT0_DIVIDE_F => 16.000,
CLKOUT0_DIVIDE_F => 8.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
--CLKOUT1_DIVIDE => 8,
CLKOUT1_DIVIDE => 4,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_USE_FINE_PS => FALSE,
-- 61.44 MHZ input clock
--CLKIN1_PERIOD => 16.276,
-- 122.88 MHZ input clock
CLKIN1_PERIOD => 8.138,
REF_JITTER1 => 0.010
)
port map
(
-- Output clocks
CLKFBOUT => adc_str_fbout,
CLKFBOUTB => open,
CLKOUT0 => adc_str_out,
CLKOUT0B => open,
CLKOUT1 => adc_str_2x_out,
CLKOUT1B => open,
CLKOUT2 => open,
CLKOUT2B => open,
CLKOUT3 => open,
CLKOUT3B => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKOUT6 => open,
-- Input clock control
CLKFBIN => adc_str_fbin,
CLKIN1 => adc_str,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => mmcm_adc_locked,
CLKINSTOPPED => open,
CLKFBSTOPPED => open,
PWRDWN => '0',
RST => rst
);
-- Global clock buffers for "cmp_mmcm_adc" instance
cmp_clkf_bufg : BUFG
port map
(
O => adc_str_fbin,
I => adc_str_fbout
);
cmp_adc_str_out_bufg : BUFG
port map
(
O => clk_adc,
I => adc_str_out
);
cmp_adc_str_2x_out_bufg : BUFG
port map
(
O => clk_adc_2x,
I => adc_str_2x_out
);
end generate;
-- Global clock buffers for "cmp_mmcm_adc" instance
cmp_clkf_bufg : BUFG
port map
(
O => adc_str_fbin,
I => adc_str_fbout
);
-- Double clock circuit. only for SIMULATION!
-- See Xilinx "six easy pieces" paper from Peter Alfke
gen_clk_sim : if (g_sim = true) generate
cmp_adc_str_out_bufg : BUFG
port map
(
O => clk_adc,
I => adc_str_out
);
cmp_adc_str_2x_out_bufg : BUFG
port map
(
O => clk_adc_2x,
I => adc_str_2x_out
);
clk_adc <= adc_str;
clk_adc_2x <= adc_str xor not toggle_ff_q;
p_gen_clk2x_sim : process(clk_adc_2x)
begin
if rising_edge(clk_adc_2x) then
toggle_ff_q <= not toggle_ff_q;
end if;
end process;
end generate;
clk_adc_o <= clk_adc;--adc_str;
-- ADC Interface
cmp_adc_if : fmc150_adc_if
generic map(
g_sim => g_sim
)
port map
(
clk_200MHz_i => clk_200MHz,
......@@ -331,4 +357,4 @@ begin
prsnt_m2c_l => prsnt_m2c_l
);
end rtl;
\ No newline at end of file
end rtl;
hdl/modules/custom_wishbone/wb_fmc150/output deleted 100644 → 0
View file @ b985100a
This diff is collapsed.
hdl/modules/custom_wishbone/wb_fmc150/xfmc150.wb
View file @ 741e251e
......@@ -21,7 +21,7 @@ peripheral {
--prefix = "start";
-- Pulse to start
type = MONOSTABLE;
clock = "clk_100Mhz";
clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -38,7 +38,7 @@ peripheral {
write 0: read from SPI";
prefix = "spi_rw";
type = BIT;
--clock = "";
clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -49,7 +49,7 @@ peripheral {
write 0: internal clock for ADC";
prefix = "ext_clk";
type = BIT;
--clock = "";
clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -66,7 +66,7 @@ peripheral {
--prefix = "addr";
type = SLV;
size = 16;
--clock = "";
clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -83,7 +83,7 @@ peripheral {
--prefix = "data";
type = SLV;
size = 32;
--clock = "";
clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -100,7 +100,7 @@ peripheral {
write 0: no effect";
prefix = "cdce72010";
type = BIT;
--clock = "";
clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -111,7 +111,7 @@ peripheral {
write 0: no effect";
prefix = "ads62p49";
type = BIT;
--clock = "";
clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -122,7 +122,7 @@ peripheral {
write 0: no effect";
prefix = "dac3283";
type = BIT;
--clock = "";
clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -133,7 +133,7 @@ peripheral {
write 0: no effect";
prefix = "amc7823";
type = BIT;
--clock = "";
clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -151,7 +151,7 @@ peripheral {
type = SLV;
size = 5;
align = 8;
--clock = "";
clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -163,7 +163,7 @@ peripheral {
type = SLV;
size = 5;
align = 8;
--clock = "";
clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -175,11 +175,18 @@ peripheral {
type = SLV;
size = 5;
align = 8;
--clock = "";
clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-- The following registers are within the clk_100Mhz_i domain.
-- Therefore, in order to read it from the bus, we need
-- to synchronize them to clk_wb_i (wishbone control clock) domain.
-- Note that clk_wb_i must be connected to the same clock as clk_sys_i.
-- It is just a diferent name to the same port, to avoid naming
-- conflicts as generated by wbgen2.
-- Data Out
reg {
......@@ -192,7 +199,8 @@ peripheral {
--prefix = "data";
type = SLV;
size = 32;
--clock = "";
--clock = "clk_100Mhz";
clock = "clk_wb_i";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
......@@ -209,21 +217,23 @@ peripheral {
read 0: spi idle";
prefix = "spi_busy";
type = BIT;
--clock = "";
--clock = "clk_100Mhz";
clock = "clk_wb_i";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "CDCE72010 PLL Status";
description = "read 1: PLL locked.\
read 0: PLL not locked";
prefix = "pll_status";
type = BIT;
--clock = "";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
--field {
-- name = "CDCE72010 PLL Status";
-- description = "read 1: PLL locked.\
-- read 0: PLL not locked";
-- prefix = "pll_status";
-- type = BIT;
-- --clock = "clk_100Mhz";
-- clock = "clk_wb_i";
-- access_bus = READ_ONLY;
-- access_dev = WRITE_ONLY;
--};
field {
name = "FPGA ADC clock locked";
......@@ -231,21 +241,23 @@ peripheral {
read 0: FPGA ADC PLL not locked";
prefix = "adc_clk_locked";
type = BIT;
--clock = "";
--clock = "clk_100Mhz";
clock = "clk_wb_i";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "FMC present";
description = "read 1: FMC present.\
read 0: FMC not present";
prefix = "fmc_prst";
type = BIT;
--clock = "";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
--field {
-- name = "FMC present";
-- description = "read 1: FMC present.\
-- read 0: FMC not present";
-- prefix = "fmc_prst";
-- type = BIT;
-- --clock = "clk_100Mhz";
-- clock = "clk_wb_i";
-- access_bus = READ_ONLY;
-- access_dev = WRITE_ONLY;
--};
};
};
......
hdl/modules/custom_wishbone/wb_fmc150/xfmc150_regs_pkg.vhd
View file @ 741e251e
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : xfmc150_regs_pkg.vhd
-- Author : auto-generated by wbgen2 from xfmc150.wb
-- Created : Tue Oct 2 09:38:47 2012
-- Created : Wed Oct 3 10:01:05 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE xfmc150.wb
......@@ -22,17 +22,13 @@ package fmc150_wbgen2_pkg is
type t_fmc150_in_registers is record
data_out_i : std_logic_vector(31 downto 0);
flgs_out_spi_busy_i : std_logic;
flgs_out_pll_status_i : std_logic;
flgs_out_adc_clk_locked_i : std_logic;
flgs_out_fmc_prst_i : std_logic;
end record;
constant c_fmc150_in_registers_init_value: t_fmc150_in_registers := (
data_out_i => (others => '0'),
flgs_out_spi_busy_i => '0',
flgs_out_pll_status_i => '0',
flgs_out_adc_clk_locked_i => '0',
flgs_out_fmc_prst_i => '0'
flgs_out_adc_clk_locked_i => '0'
);
-- Output registers (WB slave -> user design)
......@@ -97,9 +93,7 @@ variable tmp: t_fmc150_in_registers;
begin
tmp.data_out_i := f_x_to_zero(left.data_out_i) or f_x_to_zero(right.data_out_i);
tmp.flgs_out_spi_busy_i := f_x_to_zero(left.flgs_out_spi_busy_i) or f_x_to_zero(right.flgs_out_spi_busy_i);
tmp.flgs_out_pll_status_i := f_x_to_zero(left.flgs_out_pll_status_i) or f_x_to_zero(right.flgs_out_pll_status_i);
tmp.flgs_out_adc_clk_locked_i := f_x_to_zero(left.flgs_out_adc_clk_locked_i) or f_x_to_zero(right.flgs_out_adc_clk_locked_i);
tmp.flgs_out_fmc_prst_i := f_x_to_zero(left.flgs_out_fmc_prst_i) or f_x_to_zero(right.flgs_out_fmc_prst_i);
return tmp;
end function;
end package body;
hdl/modules/custom_wishbone/wb_fmc150/xfmc150_regs_regs.h
View file @ 741e251e
......@@ -3,7 +3,7 @@
* File : xfmc150_regs_regs.h
* Author : auto-generated by wbgen2 from xfmc150.wb
* Created : Tue Oct 2 09:38:47 2012
* Created : Wed Oct 3 10:01:05 2012
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE xfmc150.wb
......@@ -86,14 +86,8 @@
/* definitions for field: SPI Busy in reg: Flags out from Chips on FMC150 */
#define FMC150_FLGS_OUT_SPI_BUSY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: CDCE72010 PLL Status in reg: Flags out from Chips on FMC150 */
#define FMC150_FLGS_OUT_PLL_STATUS WBGEN2_GEN_MASK(1, 1)
/* definitions for field: FPGA ADC clock locked in reg: Flags out from Chips on FMC150 */
#define FMC150_FLGS_OUT_ADC_CLK_LOCKED WBGEN2_GEN_MASK(2, 1)
/* definitions for field: FMC present in reg: Flags out from Chips on FMC150 */
#define FMC150_FLGS_OUT_FMC_PRST WBGEN2_GEN_MASK(3, 1)
#define FMC150_FLGS_OUT_ADC_CLK_LOCKED WBGEN2_GEN_MASK(1, 1)
PACKED struct FMC150_WB {
/* [0x0]: REG Input Flags for Pulsing Registers */
......
hdl/modules/custom_wishbone/wb_fmc150/xwb_fmc150.vhd
View file @ 741e251e
......@@ -3,6 +3,11 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Custom Wishbone Modules
use work.custom_wishbone_pkg.all;
-- Wishbone Stream Interface
use work.wb_stream_pkg.all;
entity xwb_fmc150 is
......@@ -10,7 +15,8 @@ generic
(
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_packet_size : natural := 32
g_packet_size : natural := 32;
g_sim : boolean := false
);
port
(
......@@ -23,8 +29,8 @@ port
-- Wishbone signals
-----------------------------
wb_slv_i : t_wishbone_slave_in;
wb_slv_o : t_wishbone_slave_out;
wb_slv_i : in t_wishbone_slave_in;
wb_slv_o : out t_wishbone_slave_out;
-----------------------------
-- External ports
......@@ -47,10 +53,10 @@ port
txenable_o : out std_logic;
--Clock/Trigger connection to FMC150
clk_to_fpga_p_i : in std_logic;
clk_to_fpga_n_i : in std_logic;
ext_trigger_p_i : in std_logic;
ext_trigger_n_i : in std_logic;
--clk_to_fpga_p_i : in std_logic;
--clk_to_fpga_n_i : in std_logic;
--ext_trigger_p_i : in std_logic;
--ext_trigger_n_i : in std_logic;
-- Control signals from/to FMC150
--Serial Peripheral Interface (SPI)
......@@ -95,7 +101,10 @@ architecture rtl of xwb_fmc150 is
component wb_fmc150
generic
(
g_packet_size : natural := 32
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_packet_size : natural := 32;
g_sim : boolean := false
);
port
(
......@@ -141,10 +150,10 @@ architecture rtl of xwb_fmc150 is
txenable_o : out std_logic;
--Clock/Trigger connection to FMC150
clk_to_fpga_p_i : in std_logic;
clk_to_fpga_n_i : in std_logic;
ext_trigger_p_i : in std_logic;
ext_trigger_n_i : in std_logic;
--clk_to_fpga_p_i : in std_logic;
--clk_to_fpga_n_i : in std_logic;
--ext_trigger_p_i : in std_logic;
--ext_trigger_n_i : in std_logic;
-- Control signals from/to FMC150
--Serial Peripheral Interface (SPI)
......@@ -197,9 +206,12 @@ begin
cmp_wb_fmc150 : wb_fmc150
generic map
(
g_packet_size => g_packet_size
);
port
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity,
g_packet_size => g_packet_size,
g_sim => g_sim
)
port map
(
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
......@@ -210,17 +222,17 @@ begin
-- Wishbone signals
-----------------------------
wb_adr_i => wb_slave_i.adr,
wb_dat_i => wb_slave_i.dat,
wb_dat_o => wb_slave_o.dat,
wb_sel_i => wb_slave_i.sel,
wb_we_i => wb_slave_i.we,
wb_cyc_i => wb_slave_i.cyc,
wb_stb_i => wb_slave_i.stb,
wb_ack_o => wb_slave_o.ack,
wb_err_o => wb_slave_o.err,
wb_rty_o => wb_slave_o.rty,
wb_stall_o => wb_slave_o.stall,
wb_adr_i => wb_slv_i.adr,
wb_dat_i => wb_slv_i.dat,
wb_dat_o => wb_slv_o.dat,
wb_sel_i => wb_slv_i.sel,
wb_we_i => wb_slv_i.we,
wb_cyc_i => wb_slv_i.cyc,
wb_stb_i => wb_slv_i.stb,
wb_ack_o => wb_slv_o.ack,
wb_err_o => wb_slv_o.err,
wb_rty_o => wb_slv_o.rty,
wb_stall_o => wb_slv_o.stall,
-----------------------------
-- External ports
......@@ -243,10 +255,10 @@ begin
txenable_o => txenable_o,
--Clock/Trigger connection to FMC150
clk_to_fpga_p_i => clk_to_fpga_p_i,
clk_to_fpga_n_i => clk_to_fpga_n_i,
ext_trigger_p_i => ext_trigger_p_i,
ext_trigger_n_i => ext_trigger_n_i,
--clk_to_fpga_p_i => clk_to_fpga_p_i,
--clk_to_fpga_n_i => clk_to_fpga_n_i,
--ext_trigger_p_i => ext_trigger_p_i,
--ext_trigger_n_i => ext_trigger_n_i,
-- Control signals from/to FMC150
--Serial Peripheral Interface (SPI)
......@@ -254,17 +266,17 @@ begin
spi_sdata_o => spi_sdata_o, -- Shared SPI data line
-- ADC specific signals
adc_n_en_o => adc_n_en_o -- SPI chip select
adc_sdo_i => adc_sdo_i -- SPI data out
adc_reset_o => adc_reset_o -- SPI reset
adc_n_en_o => adc_n_en_o, -- SPI chip select
adc_sdo_i => adc_sdo_i, -- SPI data out
adc_reset_o => adc_reset_o, -- SPI reset
-- CDCE specific signals
cdce_n_en_o => cdce_n_en_o -- SPI chip select
cdce_sdo_i => cdce_sdo_i -- SPI data out
cdce_n_reset_o => cdce_n_reset_o
cdce_n_pd_o => cdce_n_pd_o
cdce_ref_en_o => cdce_ref_en_o
cdce_pll_status_i => cdce_pll_status_i
cdce_n_en_o => cdce_n_en_o, -- SPI chip select
cdce_sdo_i => cdce_sdo_i, -- SPI data out
cdce_n_reset_o => cdce_n_reset_o,
cdce_n_pd_o => cdce_n_pd_o,
cdce_ref_en_o => cdce_ref_en_o,
cdce_pll_status_i => cdce_pll_status_i,
-- DAC specific signals
dac_n_en_o => dac_n_en_o, -- SPI chip select
......@@ -293,6 +305,6 @@ begin
wbs_rty_i => wbs_source_i.rty
);
wb_slave_o.int <= '0';
wb_slv_o.int <= '0';
end rtl;
hdl/modules/custom_wishbone/wb_stream/wb_stream_pkg.vhd
View file @ 741e251e
......@@ -18,10 +18,10 @@ package wb_stream_pkg is
subtype t_wbs_byte_select is
std_logic_vector((c_wbs_data_width/8)-1 downto 0);
constant c_WRF_DATA : unsigned(c_wbs_address_width-1 downto 0) := to_unsigned(0, c_wbs_address_width);
constant c_WRF_OOB : unsigned(c_wbs_address_width-1 downto 0) := to_unsigned(1, c_wbs_address_width);
constant c_WRF_STATUS : unsigned(c_wbs_address_width-1 downto 0) := to_unsigned(2, c_wbs_address_width);
constant c_WRF_USER : unsigned(c_wbs_address_width-1 downto 0) := to_unsigned(3, c_wbs_address_width);
constant c_WBS_DATA : unsigned(c_wbs_address_width-1 downto 0) := to_unsigned(0, c_wbs_address_width);
constant c_WBS_OOB : unsigned(c_wbs_address_width-1 downto 0) := to_unsigned(1, c_wbs_address_width);
constant c_WBS_STATUS : unsigned(c_wbs_address_width-1 downto 0) := to_unsigned(2, c_wbs_address_width);
constant c_WBS_USER : unsigned(c_wbs_address_width-1 downto 0) := to_unsigned(3, c_wbs_address_width);
--constant c_WRF_OOB_TYPE_RX : std_logic_vector(3 downto 0) := "0000";
--constant c_WRF_OOB_TYPE_TX : std_logic_vector(3 downto 0) := "0001";
......@@ -79,13 +79,13 @@ package wb_stream_pkg is
constant cc_dummy_wbs_sel : std_logic_vector(c_wbs_data_width/8-1 downto 0) :=
(others => 'X');
constant c_dummy_src_in : t_wbs_source_in :=
constant cc_dummy_src_in : t_wbs_source_in :=
('0', '0', '0', '0');
constant c_dummy_snk_in : t_wbs_sink_in :=
constant cc_dummy_snk_in : t_wbs_sink_in :=
(cc_dummy_wbs_addr, cc_dummy_wbs_dat, '0', '0', '0', cc_dummy_wbs_sel);
-- Components
component xwb_stream_source
component xwb_stream_source
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
......@@ -130,9 +130,7 @@ package wb_stream_pkg is
end wb_stream_pkg;
package body wb_stream_pkg is
function f_marshall_wbs_status(stat : t_wbs_status_reg)
return std_logic_vector
is
......
hdl/modules/custom_wishbone/wb_stream/xwb_stream_sink.vhd
View file @ 741e251e
......@@ -66,9 +66,9 @@ entity xwb_stream_sink is
dreq_i : in std_logic
);
end xwb_fabric_sink;
end xwb_stream_sink;
architecture rtl of xwb_fabric_sink is
architecture rtl of xwb_stream_sink is
constant c_logic_width : integer := 4;
constant c_fifo_width : integer := c_wbs_data_width + c_wbs_address_width + 4;
......@@ -138,7 +138,7 @@ begin -- rtl
we <= '1' when fin(c_logic_range) /= "0000" and full = '0' else '0';
rd <= q_valid and dreq_i and not post_sof;
U_FIFO : generic_shiftreg_fifo
cmp_fifo : generic_shiftreg_fifo
generic map (
g_data_width => c_fifo_width,
g_size => c_fifo_depth
......@@ -173,7 +173,7 @@ begin -- rtl
sof_o <= post_sof and rd_d0;
dvalid_o <= post_dvalid and rd_d0;
error_o <= '1' when rd_d0 = '1' and (post_addr = std_logic_vector(c_WRF_STATUS)) and (f_unmarshall_wrf_status(post_data).error = '1') else '0';
error_o <= '1' when rd_d0 = '1' and (post_addr = std_logic_vector(c_WBS_STATUS)) and (f_unmarshall_wbs_status(post_data).error = '1') else '0';
eof_o <= fout_reg(c_logic_start+2) and rd_d0;
bytesel_o <= fout_reg(c_logic_start+1);
data_o <= post_data;
......@@ -239,7 +239,7 @@ architecture wrapper of wb_stream_sink is
begin -- wrapper
U_Wrapped_Sink : xwb_stream_sink
cmp_stream_sink_wrapper : xwb_stream_sink
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
......
hdl/modules/custom_wishbone/wb_stream/xwb_stream_source.vhd
View file @ 741e251e
......@@ -28,12 +28,12 @@ entity xwb_stream_source is
dreq_o : out std_logic
);
end xwb_fabric_source;
end xwb_stream_source;
architecture rtl of xwb_fabric_source is
architecture rtl of xwb_stream_source is
constant c_logic_width : integer := 4;
constant c_fifo_width : integer := c_wbs_data_width + c_wbs_address_width + 4;
constant c_fifo_width : integer := c_wbs_data_width + c_wbs_address_width + c_logic_width;
constant c_fifo_depth : integer := 32;
constant c_logic_start : integer := c_wbs_data_width + c_wbs_address_width;
......@@ -57,7 +57,7 @@ architecture rtl of xwb_fabric_source is
signal post_dvalid, post_eof, post_bytesel, post_sof : std_logic;
signal err_status : t_wrf_status_reg;
signal err_status : t_wbs_status_reg;
signal cyc_int : std_logic;
begin -- rtl
......@@ -70,13 +70,13 @@ begin -- rtl
we <= sof_i or eof_i or error_i or dvalid_i;
pre_dvalid <= dvalid_i or error_i;
pre_data <= data_i when (error_i = '0') else f_marshall_wrf_status(err_status);
pre_addr <= addr_i when (error_i = '0') else std_logic_vector(c_WRF_STATUS);
pre_data <= data_i when (error_i = '0') else f_marshall_wbs_status(err_status);
pre_addr <= addr_i when (error_i = '0') else std_logic_vector(c_WBS_STATUS);
pre_eof <= error_i or eof_i;
fin <= sof_i & pre_eof & bytesel_i & pre_dvalid & pre_addr & pre_data;
U_FIFO : generic_shiftreg_fifo
cmp_fifo : generic_shiftreg_fifo
generic map (
g_data_width => c_fifo_width,
g_size => c_fifo_depth
......@@ -158,8 +158,8 @@ entity wb_stream_source is
end wb_stream_source;
architecture wrapper of wb_fabric_source is
component xwb_fabric_source
architecture wrapper of wb_stream_source is
component xwb_stream_source
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
......@@ -180,7 +180,7 @@ architecture wrapper of wb_fabric_source is
begin -- wrapper
U_Wrapped_Source : xwb_fabric_source
cmp_stream_source_wrapper : xwb_stream_source
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
......@@ -193,7 +193,8 @@ begin -- wrapper
eof_i => eof_i,
error_i => error_i,
bytesel_i => bytesel_i,
dreq_o => dreq_o);
dreq_o => dreq_o
);
src_cyc_o <= src_out.cyc;
src_stb_o <= src_out.stb;
......
hdl/sim/regs/xfmc150_regs_regs.vh
View file @ 741e251e
......@@ -26,9 +26,5 @@
`define ADDR_FMC150_FLGS_OUT 5'h1c
`define FMC150_FLGS_OUT_SPI_BUSY_OFFSET 0
`define FMC150_FLGS_OUT_SPI_BUSY 32'h00000001
`define FMC150_FLGS_OUT_PLL_STATUS_OFFSET 1
`define FMC150_FLGS_OUT_PLL_STATUS 32'h00000002
`define FMC150_FLGS_OUT_ADC_CLK_LOCKED_OFFSET 2
`define FMC150_FLGS_OUT_ADC_CLK_LOCKED 32'h00000004
`define FMC150_FLGS_OUT_FMC_PRST_OFFSET 3
`define FMC150_FLGS_OUT_FMC_PRST 32'h00000008
`define FMC150_FLGS_OUT_ADC_CLK_LOCKED_OFFSET 1
`define FMC150_FLGS_OUT_ADC_CLK_LOCKED 32'h00000002
hdl/testbench/wishbone/wb_fmc150_test/Makefile
View file @ 741e251e
......@@ -343,6 +343,7 @@ work/wb_fmc150_tb/.wb_fmc150_tb_vhd: wb_fmc150_tb.vhd work/wb_fmc150_tb/.wb_fmc1
work/wb_fmc150_tb/.wb_fmc150_tb: \
work/wishbone_pkg/.wishbone_pkg_vhd \
work/xfmc150_regs_pkg/.xfmc150_regs_pkg_vhd \
work/wb_stream_pkg/.wb_stream_pkg_vhd \
work/custom_wishbone_pkg/.custom_wishbone_pkg_vhd
......@@ -352,7 +353,8 @@ work/custom_wishbone_pkg/.custom_wishbone_pkg_vhd: ../../../modules/custom_wishb
work/custom_wishbone_pkg/.custom_wishbone_pkg: \
work/wishbone_pkg/.wishbone_pkg_vhd
work/wishbone_pkg/.wishbone_pkg_vhd \
work/wb_stream_pkg/.wb_stream_pkg_vhd
work/custom_common_pkg/.custom_common_pkg_vhd: ../../../modules/custom_common/custom_common_pkg.vhd work/custom_common_pkg/.custom_common_pkg
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
......@@ -392,7 +394,10 @@ work/wb_fmc150/.wb_fmc150_vhd: ../../../modules/custom_wishbone/wb_fmc150/wb_fmc
work/wb_fmc150/.wb_fmc150: \
work/wb_stream_pkg/.wb_stream_pkg_vhd
work/wishbone_pkg/.wishbone_pkg_vhd \
work/xfmc150_regs_pkg/.xfmc150_regs_pkg_vhd \
work/wb_stream_pkg/.wb_stream_pkg_vhd \
work/custom_wishbone_pkg/.custom_wishbone_pkg_vhd
work/xwb_fmc150/.xwb_fmc150_vhd: ../../../modules/custom_wishbone/wb_fmc150/xwb_fmc150.vhd work/xwb_fmc150/.xwb_fmc150
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
......@@ -400,7 +405,9 @@ work/xwb_fmc150/.xwb_fmc150_vhd: ../../../modules/custom_wishbone/wb_fmc150/xwb_
work/xwb_fmc150/.xwb_fmc150: \
work/wb_stream_pkg/.wb_stream_pkg_vhd
work/wishbone_pkg/.wishbone_pkg_vhd \
work/wb_stream_pkg/.wb_stream_pkg_vhd \
work/custom_wishbone_pkg/.custom_wishbone_pkg_vhd
work/xfmc150_regs_pkg/.xfmc150_regs_pkg_vhd: ../../../modules/custom_wishbone/wb_fmc150/xfmc150_regs_pkg.vhd work/xfmc150_regs_pkg/.xfmc150_regs_pkg
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
......
hdl/testbench/wishbone/wb_fmc150_test/fuse.xmsgs deleted 100644 → 0
View file @ b985100a
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"../../../modules/custom_wishbone/custom_wishbone_pkg.vhd" Line 198: &lt;<arg fmt="%s" index="1">c_wbs_address_width</arg>&gt; is not declared.
</msg>
<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"../../../modules/custom_wishbone/custom_wishbone_pkg.vhd" Line 199: &lt;<arg fmt="%s" index="1">c_wbs_data_width</arg>&gt; is not declared.
</msg>
<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"../../../modules/custom_wishbone/custom_wishbone_pkg.vhd" Line 203: &lt;<arg fmt="%s" index="1">c_wbs_data_width</arg>&gt; is not declared.
</msg>
<msg type="error" file="HDLCompiler" num="806" delta="unknown" >"../../../modules/custom_wishbone/custom_wishbone_pkg.vhd" Line 212: Syntax error near &quot;<arg fmt="%s" index="1">entity</arg>&quot;.
</msg>
<msg type="error" file="HDLCompiler" num="854" delta="unknown" >"../../../modules/custom_wishbone/custom_wishbone_pkg.vhd" Line 7: Unit &lt;<arg fmt="%s" index="1">custom_wishbone_pkg</arg>&gt; ignored due to previous errors.
</msg>
</messages>
hdl/testbench/wishbone/wb_fmc150_test/wave.wcfg 0 → 100644
View file @ 741e251e
This diff is collapsed.
hdl/testbench/wishbone/wb_fmc150_test/wb_fmc150_tb.vhd
View file @ 741e251e
......@@ -3,9 +3,14 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Custom Wishbone Modules
use work.custom_wishbone_pkg.all;
-- Wishbone Stream Interface
use work.wb_stream_pkg.all;
-- Register Bank
use work.fmc150_wbgen2_pkg.all;
entity wb_fmc150_tb is
end wb_fmc150_tb;
......@@ -16,6 +21,8 @@ architecture sim of wb_fmc150_tb is
constant c_100mhz_clk_period : time := 10.00 ns;
-- 200.00 MHz clock
constant c_200mhz_clk_period : time := 5.00 ns;
-- 61.44 MHz clock
constant c_61_44mhz_clk_period : time := 16.00 ns;
constant c_sim_time : time := 10000.00 ns;
signal g_end_simulation : boolean := false; -- Set to true to halt the simulation
......@@ -30,12 +37,15 @@ architecture sim of wb_fmc150_tb is
signal wb_slv_in : t_wishbone_slave_in := cc_dummy_slave_in;
signal wb_slv_out : t_wishbone_slave_out;
signal wbs_src_in : t_wbs_source_in := c_dummy_src_in;
signal wbs_src_in : t_wbs_source_in := cc_dummy_src_in;
signal wbs_src_out : t_wbs_source_out;
-- Dummy signals
constant cc_dummy_bit : std_logic := '0';
constant cc_dummy_slv : std_logic_vector := '0';
-- Simulation signals
signal s_adc_clk_ab_p : std_logic := '0';
signal s_adc_clk_ab_n : std_logic := '0';
-- Generate dummy (0) values
function f_zeros(size : integer)
......@@ -67,6 +77,19 @@ begin -- sim
end loop;
wait; -- simulation stops here
end process;
p_61_44mhz_clk_gen : process
begin
while g_end_simulation = false loop
wait for c_61_44mhz_clk_period/2;
s_adc_clk_ab_p <= not s_adc_clk_ab_p;
s_adc_clk_ab_n <= not s_adc_clk_ab_n;
wait for c_61_44mhz_clk_period/2;
s_adc_clk_ab_p <= not s_adc_clk_ab_p;
s_adc_clk_ab_n <= not s_adc_clk_ab_n;
end loop;
wait; -- simulation stops here
end process;
p_main_simulation : process
begin
......@@ -81,12 +104,13 @@ begin -- sim
end process;
cmp_dut : xwb_fmc150
--generic map
--(
generic map
(
--g_interface_mode => PIPELINED,
--g_address_granularity => WORD,
--g_packet_size => 32
--);
g_sim => true
)
port map
(
rst_n_i => rst_n_i,
......@@ -105,8 +129,8 @@ begin -- sim
-- External ports
-----------------------------
--Clock/Data connection to ADC on FMC150 (ADS62P49)
adc_clk_ab_p_i => '0',
adc_clk_ab_n_i => '0',
adc_clk_ab_p_i => s_adc_clk_ab_p,
adc_clk_ab_n_i => s_adc_clk_ab_n,
adc_cha_p_i => f_zeros(7),
adc_cha_n_i => f_zeros(7),
adc_chb_p_i => f_zeros(7),
......@@ -122,10 +146,10 @@ begin -- sim
txenable_o => open,
--Clock/Trigger connection to FMC150
clk_to_fpga_p_i => '0',
clk_to_fpga_n_i => '0',
ext_trigger_p_i => '0',
ext_trigger_n_i => '0',
--clk_to_fpga_p_i => cc_dummy_bit,
--clk_to_fpga_n_i => cc_dummy_bit,
--ext_trigger_p_i => cc_dummy_bit,
--ext_trigger_n_i => cc_dummy_bit,
-- Control signals from/to FMC150
--Serial Peripheral Interface (SPI)
......@@ -134,29 +158,29 @@ begin -- sim
-- ADC specific signals
adc_n_en_o => open, -- SPI chip select
adc_sdo_i => '0', -- SPI data out
adc_sdo_i => cc_dummy_bit, -- SPI data out
adc_reset_o => open, -- SPI reset
-- CDCE specific signals
cdce_n_en_o => open, -- SPI chip select
cdce_sdo_i =>'0', -- SPI data out
cdce_sdo_i => cc_dummy_bit, -- SPI data out
cdce_n_reset_o => open,
cdce_n_pd_o => open,
cdce_ref_en_o => open,
cdce_pll_status_i => '0',
cdce_pll_status_i => cc_dummy_bit,
-- DAC specific signals
dac_n_en_o => open, -- SPI chip select
dac_sdo_i => '0', -- SPI data out
dac_sdo_i => cc_dummy_bit, -- SPI data out
-- Monitoring specific signals
mon_n_en_o => open, -- SPI chip select
mon_sdo_i => '0', -- SPI data out
mon_sdo_i => cc_dummy_bit, -- SPI data out
mon_n_reset_o => open,
mon_n_int_i => '0',
mon_n_int_i => cc_dummy_bit,
--FMC Present status
prsnt_m2c_l_i => '0',
prsnt_m2c_l_i => cc_dummy_bit,
-- Wishbone Streaming Interface Source
wbs_source_i => wbs_src_in,
......
hdl/testbench/wishbone/wb_fmc150_test/xilinxsim.ini deleted 100644 → 0
View file @ b985100a
-- Default lib mapping for Simulator
std=$XILINX/vhdl/hdp/lin64/std
ieee=$XILINX/vhdl/hdp/lin64/ieee
ieee_proposed=$XILINX/vhdl/hdp/lin64/ieee_proposed
vl=$XILINX/vhdl/hdp/lin64/vl
synopsys=$XILINX/vhdl/hdp/lin64/synopsys
simprim=$XILINX/vhdl/hdp/lin64/simprim
unisim=$XILINX/vhdl/hdp/lin64/unisim
unimacro=$XILINX/vhdl/hdp/lin64/unimacro
aim=$XILINX/vhdl/hdp/lin64/aim
cpld=$XILINX/vhdl/hdp/lin64/cpld
pls=$XILINX/vhdl/hdp/lin64/pls
xilinxcorelib=$XILINX/vhdl/hdp/lin64/xilinxcorelib
aim_ver=$XILINX/verilog/hdp/lin64/aim_ver
cpld_ver=$XILINX/verilog/hdp/lin64/cpld_ver
simprims_ver=$XILINX/verilog/hdp/lin64/simprims_ver
unisims_ver=$XILINX/verilog/hdp/lin64/unisims_ver
uni9000_ver=$XILINX/verilog/hdp/lin64/uni9000_ver
unimacro_ver=$XILINX/verilog/hdp/lin64/unimacro_ver
xilinxcorelib_ver=$XILINX/verilog/hdp/lin64/xilinxcorelib_ver
secureip=$XILINX/verilog/hdp/lin64/xip/secureip
work=work
fifo_generator_v6_1=fifo_generator_v6_1
sw/README
View file @ 741e251e
==========================================================
Folder containing all of the Beam Position Monitor software.
==========================================================
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