Commit 741e251e authored by Lucas Russo's avatar Lucas Russo

update initial design 2

parent b985100a
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\ No newline at end of file
==========================================================
Repository containing the Beam Position Monitor FPGA firmware and
software.
==========================================================
Folder Hierarchy organization:
TODO
==========================================================
Folder containing all the BPM FPGA firmware and related tests
==========================================================
Folder containing all o the BPM FPGA firmware, testbenches
and related test software
==========================================================
......@@ -3,6 +3,7 @@ use ieee.std_logic_1164.all;
library work;
use work.wishbone_pkg.all;
use work.wb_stream_pkg.all;
package custom_wishbone_pkg is
......@@ -12,98 +13,98 @@ package custom_wishbone_pkg is
component wb_dma_interface
generic(
g_ovf_counter_width : natural := 10
);
port(
-- Asynchronous Reset signal
arst_n_i : in std_logic;
-- Write Domain Clock
dma_clk_i : in std_logic;
--dma_valid_o : out std_logic;
--dma_data_o : out std_logic_vector(C_NBITS_DATA_INPUT-1 downto 0);
--dma_be_o : out std_logic_vector(C_NBITS_DATA_INPUT/8 - 1 downto 0);
--dma_last_o : out std_logic;
--dma_ready_i : in std_logic;
g_ovf_counter_width : natural := 10
);
port(
-- Asynchronous Reset signal
arst_n_i : in std_logic;
-- Write Domain Clock
dma_clk_i : in std_logic;
--dma_valid_o : out std_logic;
--dma_data_o : out std_logic_vector(C_NBITS_DATA_INPUT-1 downto 0);
--dma_be_o : out std_logic_vector(C_NBITS_DATA_INPUT/8 - 1 downto 0);
--dma_last_o : out std_logic;
--dma_ready_i : in std_logic;
-- Slave Data Flow port
--dma_dflow_slave_i : in t_wishbone_dflow_slave_in;
--dma_dflow_slave_o : out t_wishbone_dflow_slave_out;
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_adr_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
--dma_dflow_slave_i : in t_wishbone_dflow_slave_in;
--dma_dflow_slave_o : out t_wishbone_dflow_slave_out;
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_adr_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Slave Data Input Port
--data_slave_i : in t_wishbone_slave_in;
--data_slave_o : out t_wishbone_slave_out;
data_clk_i : in std_logic;
data_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
data_valid_i : in std_logic;
data_ready_o : out std_logic;
--data_slave_i : in t_wishbone_slave_in;
--data_slave_o : out t_wishbone_slave_out;
data_clk_i : in std_logic;
data_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
data_valid_i : in std_logic;
data_ready_o : out std_logic;
-- Slave control port. use wbgen2 tool or not if it is simple.
--control_slave_i : in t_wishbone_slave_in;
--control_slave_o : out t_wishbone_slave_out;
capture_ctl_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
dma_complete_o : out std_logic;
dma_ovf_o : out std_logic
--control_slave_i : in t_wishbone_slave_in;
--control_slave_o : out t_wishbone_slave_out;
capture_ctl_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
dma_complete_o : out std_logic;
dma_ovf_o : out std_logic
-- Debug Signals
--dma_debug_clk_o : out std_logic;
--dma_debug_data_o : out std_logic_vector(255 downto 0);
--dma_debug_trigger_o : out std_logic_vector(15 downto 0)
--dma_debug_clk_o : out std_logic;
--dma_debug_data_o : out std_logic_vector(255 downto 0);
--dma_debug_trigger_o : out std_logic_vector(15 downto 0)
);
end component;
component xwb_dma_interface
generic(
-- Three 32-bit data input. LSB bits are valid.
--C_NBITS_VALID_INPUT : natural := 128;
--C_NBITS_DATA_INPUT : natural := 128;
--C_OVF_COUNTER_SIZE : natural := 10
g_ovf_counter_width : natural := 10
--C_NBITS_VALID_INPUT : natural := 128;
--C_NBITS_DATA_INPUT : natural := 128;
--C_OVF_COUNTER_SIZE : natural := 10
g_ovf_counter_width : natural := 10
);
port(
-- Asynchronous Reset signal
arst_n_i : in std_logic;
-- Write Domain Clock
dma_clk_i : in std_logic;
--dma_valid_o : out std_logic;
--dma_data_o : out std_logic_vector(C_NBITS_DATA_INPUT-1 downto 0);
--dma_be_o : out std_logic_vector(C_NBITS_DATA_INPUT/8 - 1 downto 0);
--dma_last_o : out std_logic;
--dma_ready_i : in std_logic;
arst_n_i : in std_logic;
-- Write Domain Clock
dma_clk_i : in std_logic;
--dma_valid_o : out std_logic;
--dma_data_o : out std_logic_vector(C_NBITS_DATA_INPUT-1 downto 0);
--dma_be_o : out std_logic_vector(C_NBITS_DATA_INPUT/8 - 1 downto 0);
--dma_last_o : out std_logic;
--dma_ready_i : in std_logic;
-- Slave Data Flow port
dma_slave_i : in t_wishbone_slave_in;
dma_slave_o : out t_wishbone_slave_out;
dma_slave_i : in t_wishbone_slave_in;
dma_slave_o : out t_wishbone_slave_out;
-- Slave Data Input Port
--data_slave_i : in t_wishbone_slave_in;
--data_slave_o : out t_wishbone_slave_out;
data_clk_i : in std_logic;
data_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
data_valid_i : in std_logic;
data_ready_o : out std_logic;
--data_slave_i : in t_wishbone_slave_in;
--data_slave_o : out t_wishbone_slave_out;
data_clk_i : in std_logic;
data_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
data_valid_i : in std_logic;
data_ready_o : out std_logic;
-- Slave control port. use wbgen2 tool or not if it is simple.
--control_slave_i : in t_wishbone_slave_in;
--control_slave_o : out t_wishbone_slave_out;
capture_ctl_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
dma_complete_o : out std_logic;
dma_ovf_o : out std_logic
--control_slave_i : in t_wishbone_slave_in;
--control_slave_o : out t_wishbone_slave_out;
capture_ctl_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
dma_complete_o : out std_logic;
dma_ovf_o : out std_logic
-- Debug Signals
--dma_debug_clk_o : out std_logic;
--dma_debug_data_o : out std_logic_vector(255 downto 0);
--dma_debug_trigger_o : out std_logic_vector(15 downto 0)
--dma_debug_clk_o : out std_logic;
--dma_debug_data_o : out std_logic_vector(255 downto 0);
--dma_debug_trigger_o : out std_logic_vector(15 downto 0)
);
end component;
......@@ -112,109 +113,111 @@ package custom_wishbone_pkg is
(
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_packet_size : natural := 32
g_packet_size : natural := 32;
g_sim : boolean := false
);
port
(
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
clk_100Mhz_i : in std_logic;
clk_200Mhz_i : in std_logic;
-----------------------------
-- Wishbone signals
-----------------------------
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := (others => '0');
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0) := (others => '0');
wb_we_i : in std_logic := '0';
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
clk_100Mhz_i : in std_logic;
clk_200Mhz_i : in std_logic;
-----------------------------
-- Wishbone signals
-----------------------------
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := (others => '0');
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0) := (others => '0');
wb_we_i : in std_logic := '0';
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
-----------------------------
-- External ports
-----------------------------
--Clock/Data connection to ADC on FMC150 (ADS62P49)
adc_clk_ab_p_i : in std_logic;
adc_clk_ab_n_i : in std_logic;
adc_cha_p_i : in std_logic_vector(6 downto 0);
adc_cha_n_i : in std_logic_vector(6 downto 0);
adc_chb_p_i : in std_logic_vector(6 downto 0);
adc_chb_n_i : in std_logic_vector(6 downto 0);
adc_clk_ab_p_i : in std_logic;
adc_clk_ab_n_i : in std_logic;
adc_cha_p_i : in std_logic_vector(6 downto 0);
adc_cha_n_i : in std_logic_vector(6 downto 0);
adc_chb_p_i : in std_logic_vector(6 downto 0);
adc_chb_n_i : in std_logic_vector(6 downto 0);
--Clock/Data connection to DAC on FMC150 (DAC3283)
dac_dclk_p_o : out std_logic;
dac_dclk_n_o : out std_logic;
dac_data_p_o : out std_logic_vector(7 downto 0);
dac_data_n_o : out std_logic_vector(7 downto 0);
dac_frame_p_o : out std_logic;
dac_frame_n_o : out std_logic;
txenable_o : out std_logic;
--Clock/Trigger connection to FMC150
clk_to_fpga_p_i : in std_logic;
clk_to_fpga_n_i : in std_logic;
ext_trigger_p_i : in std_logic;
ext_trigger_n_i : in std_logic;
-- Control signals from/to FMC150
--Serial Peripheral Interface (SPI)
spi_sclk_o : out std_logic; -- Shared SPI clock line
spi_sdata_o : out std_logic; -- Shared SPI data line
-- ADC specific signals
adc_n_en_o : out std_logic; -- SPI chip select
adc_sdo_i : in std_logic; -- SPI data out
adc_reset_o : out std_logic; -- SPI reset
-- CDCE specific signals
cdce_n_en_o : out std_logic; -- SPI chip select
cdce_sdo_i : in std_logic; -- SPI data out
cdce_n_reset_o : out std_logic;
cdce_n_pd_o : out std_logic;
cdce_ref_en_o : out std_logic;
cdce_pll_status_i : in std_logic;
-- DAC specific signals
dac_n_en_o : out std_logic; -- SPI chip select
dac_sdo_i : in std_logic; -- SPI data out
-- Monitoring specific signals
mon_n_en_o : out std_logic; -- SPI chip select
mon_sdo_i : in std_logic; -- SPI data out
mon_n_reset_o : out std_logic;
mon_n_int_i : in std_logic;
dac_dclk_p_o : out std_logic;
dac_dclk_n_o : out std_logic;
dac_data_p_o : out std_logic_vector(7 downto 0);
dac_data_n_o : out std_logic_vector(7 downto 0);
dac_frame_p_o : out std_logic;
dac_frame_n_o : out std_logic;
txenable_o : out std_logic;
--Clock/Trigger connection to FMC150
--clk_to_fpga_p : in std_logic;
--clk_to_fpga_n : in std_logic;
--ext_trigger_p : in std_logic;
--ext_trigger_n : in std_logic;
-- Control signals from/to FMC150
--Serial Peripheral Interface (SPI)
spi_sclk_o : out std_logic; -- Shared SPI clock line
spi_sdata_o : out std_logic; -- Shared SPI data line
--FMC Present status
prsnt_m2c_l_i : in std_logic;
-- Wishbone Streaming Interface Source
wbs_adr_o : out std_logic_vector(c_wbs_address_width-1 downto 0);
wbs_dat_o : out std_logic_vector(c_wbs_data_width-1 downto 0);
wbs_cyc_o : out std_logic;
wbs_stb_o : out std_logic;
wbs_we_o : out std_logic;
wbs_sel_o : out std_logic_vector((c_wbs_data_width/8)-1 downto 0);
-- ADC specific signals
adc_n_en_o : out std_logic; -- SPI chip select
adc_sdo_i : in std_logic; -- SPI data out
adc_reset_o : out std_logic; -- SPI reset
-- CDCE specific signals
cdce_n_en_o : out std_logic; -- SPI chip select
cdce_sdo_i : in std_logic; -- SPI data out
cdce_n_reset_o : out std_logic;
cdce_n_pd_o : out std_logic;
cdce_ref_en_o : out std_logic;
cdce_pll_status_i : in std_logic;
-- DAC specific signals
dac_n_en_o : out std_logic; -- SPI chip select
dac_sdo_i : in std_logic; -- SPI data out
-- Monitoring specific signals
mon_n_en_o : out std_logic; -- SPI chip select
mon_sdo_i : in std_logic; -- SPI data out
mon_n_reset_o : out std_logic;
mon_n_int_i : in std_logic;
--FMC Present status
prsnt_m2c_l_i : in std_logic;
-- Wishbone Streaming Interface Source
wbs_adr_o : out std_logic_vector(c_wbs_address_width-1 downto 0);
wbs_dat_o : out std_logic_vector(c_wbs_data_width-1 downto 0);
wbs_cyc_o : out std_logic;
wbs_stb_o : out std_logic;
wbs_we_o : out std_logic;
wbs_sel_o : out std_logic_vector((c_wbs_data_width/8)-1 downto 0);
wbs_ack_i : in std_logic;
wbs_stall_i : in std_logic;
wbs_err_i : in std_logic;
wbs_rty_i : in std_logic
wbs_ack_i : in std_logic;
wbs_stall_i : in std_logic;
wbs_err_i : in std_logic;
wbs_rty_i : in std_logic
);
end component;
entity xwb_fmc150 is
component xwb_fmc150
generic
(
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_packet_size : natural := 32
g_packet_size : natural := 32;
g_sim : boolean := false
);
port
(
......@@ -227,8 +230,8 @@ package custom_wishbone_pkg is
-- Wishbone signals
-----------------------------
wb_slv_i : t_wishbone_slave_in;
wb_slv_o : t_wishbone_slave_out;
wb_slv_i : in t_wishbone_slave_in;
wb_slv_o : out t_wishbone_slave_out;
-----------------------------
-- External ports
......@@ -251,10 +254,10 @@ package custom_wishbone_pkg is
txenable_o : out std_logic;
--Clock/Trigger connection to FMC150
clk_to_fpga_p_i : in std_logic;
clk_to_fpga_n_i : in std_logic;
ext_trigger_p_i : in std_logic;
ext_trigger_n_i : in std_logic;
--clk_to_fpga_p : in std_logic;
--clk_to_fpga_n : in std_logic;
--ext_trigger_p : in std_logic;
--ext_trigger_n : in std_logic;
-- Control signals from/to FMC150
--Serial Peripheral Interface (SPI)
......@@ -291,7 +294,6 @@ package custom_wishbone_pkg is
wbs_source_i : in t_wbs_source_in;
wbs_source_o : out t_wbs_source_out
);
end component;
end custom_wishbone_pkg;
......@@ -3,5 +3,4 @@ modules = { "local" : [
"fmc150",
"netlist" ] };
files = ["wb_fmc150.vhd", "xwb_fmc150.vhd", "xfmc150_regs_pkg.vhd", "wb_fmc150_port.vhd",
"xwb_fmc150.vhd" ];
files = ["wb_fmc150.vhd", "xwb_fmc150.vhd", "xfmc150_regs_pkg.vhd", "wb_fmc150_port.vhd" ];
......@@ -703,23 +703,6 @@ fmc150_flgs_out_spi_busy_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc150_flgs_out_pll_status_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc150_flgs_out_adc_clk_locked_i
......@@ -728,23 +711,6 @@ fmc150_flgs_out_adc_clk_locked_i
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc150_flgs_out_fmc_prst_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
</table>
<h3><a name="sect_3_0">3. Register description</a></h3>
......@@ -2816,14 +2782,14 @@ FLGS_OUT
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
FMC_PRST
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
ADC_CLK_LOCKED
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
PLL_STATUS
ADC_CLK_LOCKED
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
SPI_BUSY
......@@ -2836,17 +2802,9 @@ SPI_BUSY
</b>[<i>read-only</i>]: SPI Busy
<br>read 1: spi busy.<br> read 0: spi idle
<li><b>
PLL_STATUS
</b>[<i>read-only</i>]: CDCE72010 PLL Status
<br>read 1: PLL locked.<br> read 0: PLL not locked
<li><b>
ADC_CLK_LOCKED
</b>[<i>read-only</i>]: FPGA ADC clock locked
<br>read 1: FPGA ADC PLL locked.<br> read 0: FPGA ADC PLL not locked
<li><b>
FMC_PRST
</b>[<i>read-only</i>]: FMC present
<br>read 1: FMC present.<br> read 0: FMC not present
</ul>
......
......@@ -10,6 +10,9 @@ use work.adc_pkg.all;
entity fmc150_adc_if is
generic (
g_sim : boolean := false
);
port
(
clk_200MHz_i : in std_logic;
......@@ -47,18 +50,27 @@ architecture rtl of fmc150_adc_if is
signal s_adc_chb_sdr : std_logic_vector(13 downto 0);
begin
-- ADC data strobe (channel A and B) with adjustable delay
cmp_adc_str: strobe_lvds
port map
(
clk_ctrl_i => clk_100MHz_i,
strobe_p_i => str_p_i,
strobe_n_i => str_n_i,
strobe_o => s_adc_str_dly,
ctrl_delay_update_i => delay_update_i,
ctrl_delay_value_i => str_cntvalue_i,
ctrl_delay_value_o => str_cntvalue_o
);
-- Synthesis Only!
gen_adc_clk : if (g_sim = false) generate
-- ADC data strobe (channel A and B) with adjustable delay
cmp_adc_str: strobe_lvds
port map
(
clk_ctrl_i => clk_100MHz_i,
strobe_p_i => str_p_i,
strobe_n_i => str_n_i,
strobe_o => s_adc_str_dly,
ctrl_delay_update_i => delay_update_i,
ctrl_delay_value_i => str_cntvalue_i,
ctrl_delay_value_o => str_cntvalue_o
);
end generate;
-- Simulation Only!
gen_adc_clk_sim : if (g_sim = true) generate
s_adc_str_dly <= str_p_i and str_n_i;
end generate;
-- s_adc_str_dly is a regional clock driven by BUFR.
-- Must go through a BUFG before other components (BPM DDC)
......@@ -109,4 +121,4 @@ begin
ctrl_delay_value_i => chb_cntvalue_i
);
end rtl;
\ No newline at end of file
end rtl;
......@@ -70,6 +70,9 @@ package fmc150_pkg is
end component;
component fmc150_adc_if is
generic (
g_sim : boolean := false
);
port
(
clk_200MHz_i : in std_logic;
......@@ -386,4 +389,4 @@ package fmc150_pkg is
);
end component;
end fmc150_pkg;
\ No newline at end of file
end fmc150_pkg;
......@@ -8,8 +8,10 @@ use unisim.vcomponents.all;
library work;
use work.fmc150_pkg.all;
entity fmc150_testbench is
generic(
g_sim : boolean := false
);
port
(
rst : in std_logic;
......@@ -28,10 +30,10 @@ port
dac_frame_p : out std_logic;
dac_frame_n : out std_logic;
txenable : out std_logic;
clk_to_fpga_p : in std_logic;
clk_to_fpga_n : in std_logic;
ext_trigger_p : in std_logic;
ext_trigger_n : in std_logic;
--clk_to_fpga_p : in std_logic;
--clk_to_fpga_n : in std_logic;
--ext_trigger_p : in std_logic;
--ext_trigger_n : in std_logic;
spi_sclk : out std_logic;
spi_sdata : out std_logic;
rd_n_wr : in std_logic;
......@@ -113,116 +115,140 @@ architecture rtl of fmc150_testbench is
signal dac_din_d : std_logic_vector(15 downto 0);
signal adc_str_fbin, adc_str_out, adc_str_2x_out, adc_str_fbout : std_logic;
-- simulation only
signal toggle_ff_q : std_logic := '0';
begin
-- I/O delay control
cmp_idelayctrl : idelayctrl
port map
(
rst => rst,
refclk => clk_200MHz,
rdy => open
);
-- Synthesis Only
gen_clk : if (g_sim = false) generate
-- I/O delay control
cmp_idelayctrl : idelayctrl
port map
(
rst => rst,
refclk => clk_200MHz,
rdy => open
);
-- ADC Clock PLL
cmp_mmcm_adc : MMCM_ADV
generic map
(
BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
CLOCK_HOLD => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
--CLKFBOUT_MULT_F => 16.000,
CLKFBOUT_MULT_F => 8.000,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
--CLKOUT0_DIVIDE_F => 16.000,
CLKOUT0_DIVIDE_F => 8.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
--CLKOUT1_DIVIDE => 8,
CLKOUT1_DIVIDE => 4,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_USE_FINE_PS => FALSE,
-- 61.44 MHZ input clock
--CLKIN1_PERIOD => 16.276,
-- 122.88 MHZ input clock
CLKIN1_PERIOD => 8.138,
REF_JITTER1 => 0.010
)
port map
(
-- Output clocks
CLKFBOUT => adc_str_fbout,
CLKFBOUTB => open,
CLKOUT0 => adc_str_out,
CLKOUT0B => open,
CLKOUT1 => adc_str_2x_out,
CLKOUT1B => open,
CLKOUT2 => open,
CLKOUT2B => open,
CLKOUT3 => open,
CLKOUT3B => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKOUT6 => open,
-- Input clock control
CLKFBIN => adc_str_fbin,
CLKIN1 => adc_str,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => mmcm_adc_locked,
CLKINSTOPPED => open,
CLKFBSTOPPED => open,
PWRDWN => '0',
RST => rst
);
-- ADC Clock PLL
cmp_mmcm_adc : MMCM_ADV
generic map
(
BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
CLOCK_HOLD => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
--CLKFBOUT_MULT_F => 16.000,
CLKFBOUT_MULT_F => 8.000,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
--CLKOUT0_DIVIDE_F => 16.000,
CLKOUT0_DIVIDE_F => 8.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
--CLKOUT1_DIVIDE => 8,
CLKOUT1_DIVIDE => 4,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_USE_FINE_PS => FALSE,
-- 61.44 MHZ input clock
--CLKIN1_PERIOD => 16.276,
-- 122.88 MHZ input clock
CLKIN1_PERIOD => 8.138,
REF_JITTER1 => 0.010
)
port map
(
-- Output clocks
CLKFBOUT => adc_str_fbout,
CLKFBOUTB => open,
CLKOUT0 => adc_str_out,
CLKOUT0B => open,
CLKOUT1 => adc_str_2x_out,
CLKOUT1B => open,
CLKOUT2 => open,
CLKOUT2B => open,
CLKOUT3 => open,
CLKOUT3B => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKOUT6 => open,
-- Input clock control
CLKFBIN => adc_str_fbin,
CLKIN1 => adc_str,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => mmcm_adc_locked,
CLKINSTOPPED => open,
CLKFBSTOPPED => open,
PWRDWN => '0',
RST => rst
);
-- Global clock buffers for "cmp_mmcm_adc" instance
cmp_clkf_bufg : BUFG
port map
(
O => adc_str_fbin,
I => adc_str_fbout
);
cmp_adc_str_out_bufg : BUFG
port map
(
O => clk_adc,
I => adc_str_out
);
cmp_adc_str_2x_out_bufg : BUFG
port map
(
O => clk_adc_2x,
I => adc_str_2x_out
);
end generate;
-- Global clock buffers for "cmp_mmcm_adc" instance
cmp_clkf_bufg : BUFG
port map
(
O => adc_str_fbin,
I => adc_str_fbout
);
-- Double clock circuit. only for SIMULATION!
-- See Xilinx "six easy pieces" paper from Peter Alfke
gen_clk_sim : if (g_sim = true) generate
cmp_adc_str_out_bufg : BUFG
port map
(
O => clk_adc,
I => adc_str_out
);
cmp_adc_str_2x_out_bufg : BUFG
port map
(
O => clk_adc_2x,
I => adc_str_2x_out
);
clk_adc <= adc_str;
clk_adc_2x <= adc_str xor not toggle_ff_q;
p_gen_clk2x_sim : process(clk_adc_2x)
begin
if rising_edge(clk_adc_2x) then
toggle_ff_q <= not toggle_ff_q;
end if;
end process;
end generate;
clk_adc_o <= clk_adc;--adc_str;
-- ADC Interface
cmp_adc_if : fmc150_adc_if
generic map(
g_sim => g_sim
)
port map
(
clk_200MHz_i => clk_200MHz,
......@@ -331,4 +357,4 @@ begin
prsnt_m2c_l => prsnt_m2c_l
);
end rtl;
\ No newline at end of file
end rtl;
INFO: Simulation tool: isim
[hdlmake2 0.02714]: LoadTopManifest
[hdlmake2 0.02719]: Looking for manifest in /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150
[hdlmake2 0.02726]: *** found manifest for module /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150
[hdlmake2 0.02797]: Parsing manifest file: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/Manifest.py
[hdlmake2 0.02837]: Looking for manifest in /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/adc
[hdlmake2 0.02840]: *** found manifest for module /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/adc
[hdlmake2 0.02846]: Looking for manifest in /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150
[hdlmake2 0.02849]: *** found manifest for module /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150
[hdlmake2 0.02854]: Looking for manifest in /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/netlist
[hdlmake2 0.02857]: *** found manifest for module /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/netlist
[hdlmake2 0.02869]: SFF> /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/wb_fmc150.vhd
[hdlmake2 0.03113]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/wb_fmc150.vhd provides []
[hdlmake2 0.03114]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/wb_fmc150.vhd requires [('work', 'wb_stream_pkg')]
[hdlmake2 0.03118]: SFF> /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/xwb_fmc150.vhd
[hdlmake2 0.03256]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/xwb_fmc150.vhd provides []
[hdlmake2 0.03257]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/xwb_fmc150.vhd requires [('work', 'wb_fmc150_pkg'), ('work', 'wb_stream_pkg')]
[hdlmake2 0.03260]: SFF> /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/xfmc150_regs_pkg.vhd
[hdlmake2 0.03313]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/xfmc150_regs_pkg.vhd provides [('work', 'fmc150_wbgen2_pkg')]
[hdlmake2 0.03314]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/xfmc150_regs_pkg.vhd requires []
[hdlmake2 0.03317]: SFF> /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/wb_fmc150_port.vhd
[hdlmake2 0.03490]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/wb_fmc150_port.vhd provides []
[hdlmake2 0.03491]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/wb_fmc150_port.vhd requires [('work', 'fmc150_wbgen2_pkg')]
[hdlmake2 0.03494]: SFF> /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/xwb_fmc150.vhd
[hdlmake2 0.03632]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/xwb_fmc150.vhd provides []
[hdlmake2 0.03633]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/xwb_fmc150.vhd requires [('work', 'wb_fmc150_pkg'), ('work', 'wb_stream_pkg')]
[hdlmake2 0.03702]: Parsing manifest file: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/adc/Manifest.py
[hdlmake2 0.03767]: SFF> /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/adc/adc_channel_lvds_ddr.vhd
[hdlmake2 0.03815]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/adc/adc_channel_lvds_ddr.vhd provides []
[hdlmake2 0.03816]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/adc/adc_channel_lvds_ddr.vhd requires [('unisim', 'vcomponents')]
[hdlmake2 0.03819]: SFF> /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/adc/adc_pkg.vhd
[hdlmake2 0.03845]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/adc/adc_pkg.vhd provides [('work', 'adc_pkg')]
[hdlmake2 0.03846]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/adc/adc_pkg.vhd requires []
[hdlmake2 0.03849]: SFF> /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/adc/strobe_lvds.vhd
[hdlmake2 0.03895]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/adc/strobe_lvds.vhd provides []
[hdlmake2 0.03896]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/adc/strobe_lvds.vhd requires [('unisim', 'vcomponents')]
[hdlmake2 0.03970]: Parsing manifest file: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/Manifest.py
[hdlmake2 0.04035]: SFF> /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/ads62p49_ctrl.vhd
[hdlmake2 0.04232]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/ads62p49_ctrl.vhd provides []
[hdlmake2 0.04233]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/ads62p49_ctrl.vhd requires []
[hdlmake2 0.04236]: SFF> /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/amc7823_ctrl.vhd
[hdlmake2 0.04434]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/amc7823_ctrl.vhd provides []
[hdlmake2 0.04435]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/amc7823_ctrl.vhd requires []
[hdlmake2 0.04438]: SFF> /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/cdce72010_ctrl.vhd
[hdlmake2 0.04652]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/cdce72010_ctrl.vhd provides []
[hdlmake2 0.04653]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/cdce72010_ctrl.vhd requires []
[hdlmake2 0.04656]: SFF> /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/dac3283_ctrl.vhd
[hdlmake2 0.04847]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/dac3283_ctrl.vhd provides []
[hdlmake2 0.04848]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/dac3283_ctrl.vhd requires []
[hdlmake2 0.04851]: SFF> /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_adc_if.vhd
[hdlmake2 0.04904]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_adc_if.vhd provides []
[hdlmake2 0.04906]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_adc_if.vhd requires [('work', 'adc_pkg'), ('unisim', 'vcomponents')]
[hdlmake2 0.04909]: SFF> /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_dac_if.vhd
[hdlmake2 0.05006]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_dac_if.vhd provides []
[hdlmake2 0.05007]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_dac_if.vhd requires [('unisim', 'vcomponents')]
[hdlmake2 0.05010]: SFF> /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_pkg.vhd
[hdlmake2 0.05178]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_pkg.vhd provides [('work', 'fmc150_pkg')]
[hdlmake2 0.05179]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_pkg.vhd requires []
[hdlmake2 0.05182]: SFF> /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_spi_ctrl.vhd
[hdlmake2 0.05361]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_spi_ctrl.vhd provides []
[hdlmake2 0.05362]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_spi_ctrl.vhd requires [('unisim', 'vcomponents')]
[hdlmake2 0.05366]: SFF> /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_stellar_cmd.vhd
[hdlmake2 0.05472]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_stellar_cmd.vhd provides []
[hdlmake2 0.05473]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_stellar_cmd.vhd requires []
[hdlmake2 0.05477]: SFF> /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_testbench.vhd
[hdlmake2 0.05620]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_testbench.vhd provides []
[hdlmake2 0.05621]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_testbench.vhd requires [('unisim', 'vcomponents'), ('work', 'fmc150_pkg')]
[hdlmake2 0.05625]: SFF> /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/pulse2pulse.vhd
[hdlmake2 0.05690]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/pulse2pulse.vhd provides []
[hdlmake2 0.05693]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/pulse2pulse.vhd requires []
[hdlmake2 0.05763]: Parsing manifest file: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/netlist/Manifest.py
[hdlmake2 0.05817]: SFF> /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/netlist/ads62p49_init_mem.ngc
[hdlmake2 0.05820]: SFF> /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/netlist/amc7823_init_mem.ngc
[hdlmake2 0.05823]: SFF> /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/netlist/cdce72010_init_mem_ext.ngc
[hdlmake2 0.05827]: SFF> /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/netlist/cdce72010_init_mem_int.ngc
[hdlmake2 0.05830]: SFF> /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/netlist/dac3283_init_mem.ngc
INFO: Generating ISE Simulation (ISim) makefile for simulation.
[hdlmake2 0.06846]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/wb_fmc150.vhd
ERROR: Missing dependency in file /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/wb_fmc150.vhd: work.wb_stream_pkg
[hdlmake2 0.06851]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/xwb_fmc150.vhd
ERROR: Missing dependency in file /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/xwb_fmc150.vhd: work.wb_fmc150_pkg
ERROR: Missing dependency in file /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/xwb_fmc150.vhd: work.wb_stream_pkg
[hdlmake2 0.06857]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/xfmc150_regs_pkg.vhd
[hdlmake2 0.06857]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/wb_fmc150_port.vhd
[hdlmake2 0.06859]: --> /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/xfmc150_regs_pkg.vhd
[hdlmake2 0.06860]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/adc/adc_channel_lvds_ddr.vhd
ERROR: Missing dependency in file /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/adc/adc_channel_lvds_ddr.vhd: unisim.vcomponents
[hdlmake2 0.06864]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/adc/adc_pkg.vhd
[hdlmake2 0.06864]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/adc/strobe_lvds.vhd
ERROR: Missing dependency in file /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/adc/strobe_lvds.vhd: unisim.vcomponents
[hdlmake2 0.06868]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/ads62p49_ctrl.vhd
[hdlmake2 0.06869]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/amc7823_ctrl.vhd
[hdlmake2 0.06869]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/cdce72010_ctrl.vhd
[hdlmake2 0.06870]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/dac3283_ctrl.vhd
[hdlmake2 0.06871]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_adc_if.vhd
[hdlmake2 0.06873]: --> /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/adc/adc_pkg.vhd
ERROR: Missing dependency in file /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_adc_if.vhd: unisim.vcomponents
[hdlmake2 0.06876]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_dac_if.vhd
ERROR: Missing dependency in file /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_dac_if.vhd: unisim.vcomponents
[hdlmake2 0.06879]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_pkg.vhd
[hdlmake2 0.06880]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_spi_ctrl.vhd
ERROR: Missing dependency in file /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_spi_ctrl.vhd: unisim.vcomponents
[hdlmake2 0.06884]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_stellar_cmd.vhd
[hdlmake2 0.06884]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_testbench.vhd
ERROR: Missing dependency in file /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_testbench.vhd: unisim.vcomponents
[hdlmake2 0.06892]: --> /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_pkg.vhd
[hdlmake2 0.06893]: /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/pulse2pulse.vhd
[hdlmake2 0.06930]: 0 /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/wb_fmc150.vhdTrue
[hdlmake2 0.06931]: 0 /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/xwb_fmc150.vhdTrue
[hdlmake2 0.06931]: 0 /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/xfmc150_regs_pkg.vhdTrue
[hdlmake2 0.06932]: 0 /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/wb_fmc150_port.vhdTrue
[hdlmake2 0.06932]: 0 /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/adc/adc_channel_lvds_ddr.vhdTrue
[hdlmake2 0.06933]: 0 /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/adc/adc_pkg.vhdTrue
[hdlmake2 0.06933]: 0 /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/adc/strobe_lvds.vhdTrue
[hdlmake2 0.06934]: 0 /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/ads62p49_ctrl.vhdTrue
[hdlmake2 0.06934]: 0 /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/amc7823_ctrl.vhdTrue
[hdlmake2 0.06935]: 0 /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/cdce72010_ctrl.vhdTrue
[hdlmake2 0.06935]: 0 /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/dac3283_ctrl.vhdTrue
[hdlmake2 0.06936]: 0 /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_adc_if.vhdTrue
[hdlmake2 0.06936]: 0 /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_dac_if.vhdTrue
[hdlmake2 0.06936]: 0 /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_pkg.vhdTrue
[hdlmake2 0.06937]: 0 /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_spi_ctrl.vhdTrue
[hdlmake2 0.06937]: 0 /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_stellar_cmd.vhdTrue
[hdlmake2 0.06938]: 0 /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_testbench.vhdTrue
[hdlmake2 0.06938]: 0 /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/pulse2pulse.vhdTrue
[hdlmake2 0.06939]: 0 /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/netlist/ads62p49_init_mem.ngcTrue
[hdlmake2 0.06939]: 0 /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/netlist/amc7823_init_mem.ngcTrue
[hdlmake2 0.06940]: 0 /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/netlist/cdce72010_init_mem_ext.ngcTrue
[hdlmake2 0.06940]: 0 /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/netlist/cdce72010_init_mem_int.ngcTrue
[hdlmake2 0.06941]: 0 /home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/netlist/dac3283_init_mem.ngcTrue
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
--use work.wb_fmc150_pkg.all;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Custom Wishbone Modules
use work.custom_wishbone_pkg.all;
-- Wishbone Stream Interface
use work.wb_stream_pkg.all;
-- Register Bank
use work.fmc150_wbgen2_pkg.all;
-- FIX. Synchorinze the assynchronous clock at deassertion1
-- FIX. Sel byte select in wb_source_out
-- FIX. Test SOF and EOF in wb_source_out at the same sycle. Should work.
entity wb_fmc150 is
generic
(
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_packet_size : natural := 32
g_packet_size : natural := 32;
g_sim : boolean := false
);
port
(
......@@ -57,10 +69,10 @@ port
txenable_o : out std_logic;
--Clock/Trigger connection to FMC150
clk_to_fpga_p_i : in std_logic;
clk_to_fpga_n_i : in std_logic;
ext_trigger_p_i : in std_logic;
ext_trigger_n_i : in std_logic;
--clk_to_fpga_p_i : in std_logic;
--clk_to_fpga_n_i : in std_logic;
--ext_trigger_p_i : in std_logic;
--ext_trigger_n_i : in std_logic;
-- Control signals from/to FMC150
--Serial Peripheral Interface (SPI)
......@@ -111,6 +123,9 @@ end wb_fmc150;
architecture rtl of wb_fmc150 is
-- Constants
constant c_counter_size : natural := f_ceil_log2(g_packet_size);
-----------------------------------------------------------------------------------------------
-- IP / user logic interface signals
-----------------------------------------------------------------------------------------------
......@@ -123,14 +138,15 @@ architecture rtl of wb_fmc150 is
signal wbs_stream_in : t_wbs_source_in;
-- FMC 150 testbench signals
signal cdce_pll_status : std_logic;
--signal cdce_pll_status : std_logic;
signal s_mmcm_adc_locked : std_logic;
signal s_adc_dout : std_logic;
signal s_adc_dout : std_logic_vector(31 downto 0);
signal s_clk_adc : std_logic;
signal s_fmc150_rst : std_logic;
-- Streaming control signals
signal s_wbs_packet_counter : unsigned;
signal s_wbs_packet_counter : unsigned(c_counter_size-1 downto 0);
signal s_addr : std_logic_vector(c_wbs_address_width-1 downto 0);
signal s_data : std_logic_vector(c_wbs_data_width-1 downto 0);
signal s_dvalid : std_logic;
......@@ -146,57 +162,181 @@ architecture rtl of wb_fmc150 is
signal resized_addr : std_logic_vector(c_wishbone_address_width-1 downto 0);
-- Components
-- Bank Register / Wishbone Interface
component wb_fmc150_port
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
clk_100Mhz_i : in std_logic;
clk_wb_i : in std_logic;
regs_i : in t_fmc150_in_registers;
regs_o : out t_fmc150_out_registers
);
end component;
-- Top FMC150 component
component fmc150_testbench
generic(
g_sim : boolean := false
);
port
(
rst : in std_logic;
clk_100Mhz : in std_logic;
clk_200Mhz : in std_logic;
adc_clk_ab_p : in std_logic;
adc_clk_ab_n : in std_logic;
adc_cha_p : in std_logic_vector(6 downto 0);
adc_cha_n : in std_logic_vector(6 downto 0);
adc_chb_p : in std_logic_vector(6 downto 0);
adc_chb_n : in std_logic_vector(6 downto 0);
dac_dclk_p : out std_logic;
dac_dclk_n : out std_logic;
dac_data_p : out std_logic_vector(7 downto 0);
dac_data_n : out std_logic_vector(7 downto 0);
dac_frame_p : out std_logic;
dac_frame_n : out std_logic;
txenable : out std_logic;
--clk_to_fpga_p : in std_logic;
--clk_to_fpga_n : in std_logic;
--ext_trigger_p : in std_logic;
--ext_trigger_n : in std_logic;
spi_sclk : out std_logic;
spi_sdata : out std_logic;
rd_n_wr : in std_logic;
addr : in std_logic_vector(15 downto 0);
idata : in std_logic_vector(31 downto 0);
odata : out std_logic_vector(31 downto 0);
busy : out std_logic;
cdce72010_valid : in std_logic;
ads62p49_valid : in std_logic;
dac3283_valid : in std_logic;
amc7823_valid : in std_logic;
external_clock : in std_logic;
adc_n_en : out std_logic;
adc_sdo : in std_logic;
adc_reset : out std_logic;
cdce_n_en : out std_logic;
cdce_sdo : in std_logic;
cdce_n_reset : out std_logic;
cdce_n_pd : out std_logic;
ref_en : out std_logic;
pll_status : in std_logic;
dac_n_en : out std_logic;
dac_sdo : in std_logic;
mon_n_en : out std_logic;
mon_sdo : in std_logic;
mon_n_reset : out std_logic;
mon_n_int : in std_logic;
prsnt_m2c_l : in std_logic;
adc_delay_update_i : in std_logic;
adc_str_cntvaluein_i : in std_logic_vector(4 downto 0);
adc_cha_cntvaluein_i : in std_logic_vector(4 downto 0);
adc_chb_cntvaluein_i : in std_logic_vector(4 downto 0);
adc_str_cntvalueout_o : out std_logic_vector(4 downto 0);
adc_dout_o : out std_logic_vector(31 downto 0);
clk_adc_o : out std_logic;
mmcm_adc_locked_o : out std_logic
);
end component;
-- Generate bit with probability of '1' equals to 'prob'
procedure gen_valid(prob : real; variable seed1, seed2 : inout positive;
signal result : out std_logic)
is
variable rand: real; -- Random real-number value in range 0 to 1.0
begin
uniform(seed1, seed2, rand); -- generate random number
--int_rand := integer(trunc(rand*4096.0)); -- rescale to 0..4096, find integer part
--stim := std_logic_vector(to_unsigned(int_rand, stim'LENGTH)); -- convert to std_logic_vector
if (rand > prob) then
result <= '1';
else
result <= '0';
end if;
end procedure;
-- Generate std_logic_vector
procedure gen_data(size : positive; variable seed1, seed2 : inout positive;
signal result : out std_logic_vector)
is
variable rand : real; -- Random real-number value in range 0 to 1.0
variable int_rand : integer; -- Random integer value in range 0..2^c_wbs_data_width
variable stim : std_logic_vector(c_wbs_data_width-1 downto 0); -- Random c_wbs_data_width-1 bit stimulus
begin
uniform(seed1, seed2, rand); -- generate random number
int_rand := integer(trunc(rand*real(2**16))); -- rescale to 0..2^c_wbs_data_width, find integer part
stim := std_logic_vector(to_unsigned(int_rand, stim'length)); -- convert to std_logic_vector
result <= stim(size-1 downto 0);
end procedure;
begin
-----------------------------------------------------------------------------------------------
-- BUS / IP interface
-----------------------------------------------------------------------------------------------
cmp_fmc150_testbench: fmc150_testbench
generic map(
g_sim => g_sim
)
port map
(
rst => rst,
clk_100Mhz => clk_100Mhz,
clk_200Mhz => clk_200Mhz,
rst => s_fmc150_rst,
clk_100Mhz => clk_100Mhz_i,
clk_200Mhz => clk_200Mhz_i,
adc_clk_ab_p => adc_clk_ab_p,
adc_clk_ab_n => adc_clk_ab_n,
adc_cha_p => adc_cha_p,
adc_cha_n => adc_cha_n,
adc_chb_p => adc_chb_p,
adc_chb_n => adc_chb_n,
dac_dclk_p => dac_dclk_p,
dac_dclk_n => dac_dclk_n,
dac_data_p => dac_data_p,
dac_data_n => dac_data_n,
dac_frame_p => dac_frame_p,
dac_frame_n => dac_frame_n,
txenable => txenable,
clk_to_fpga_p => clk_to_fpga_p,
clk_to_fpga_n => clk_to_fpga_n,
ext_trigger_p => ext_trigger_p,
ext_trigger_n => ext_trigger_n,
spi_sclk => spi_sclk,
spi_sdata => spi_sdata,
adc_n_en => adc_n_en,
adc_sdo => adc_sdo,
adc_reset => adc_reset,
cdce_n_en => cdce_n_en,
cdce_sdo => cdce_sdo,
cdce_n_reset => cdce_n_reset,
cdce_n_pd => cdce_n_pd,
ref_en => cdce_ref_en,
dac_n_en => dac_n_en,
dac_sdo => dac_sdo,
mon_n_en => mon_n_en,
mon_sdo => mon_sdo,
mon_n_reset => mon_n_reset,
mon_n_int => mon_n_int,
adc_clk_ab_p => adc_clk_ab_p_i,
adc_clk_ab_n => adc_clk_ab_n_i,
adc_cha_p => adc_cha_p_i,
adc_cha_n => adc_cha_n_i,
adc_chb_p => adc_chb_p_i,
adc_chb_n => adc_chb_n_i,
dac_dclk_p => dac_dclk_p_o,
dac_dclk_n => dac_dclk_n_o,
dac_data_p => dac_data_p_o,
dac_data_n => dac_data_n_o,
dac_frame_p => dac_frame_p_o,
dac_frame_n => dac_frame_n_o,
txenable => txenable_o,
--clk_to_fpga_p => clk_to_fpga_p_i,
--clk_to_fpga_n => clk_to_fpga_n_i,
--ext_trigger_p => ext_trigger_p_i,
--ext_trigger_n => ext_trigger_n_i,
spi_sclk => spi_sclk_o,
spi_sdata => spi_sdata_o,
adc_n_en => adc_n_en_o,
adc_sdo => adc_sdo_i,
adc_reset => adc_reset_o,
cdce_n_en => cdce_n_en_o,
cdce_sdo => cdce_sdo_i,
cdce_n_reset => cdce_n_reset_o,
cdce_n_pd => cdce_n_pd_o,
ref_en => cdce_ref_en_o,
dac_n_en => dac_n_en_o,
dac_sdo => dac_sdo_i,
mon_n_en => mon_n_en_o,
mon_sdo => mon_sdo_i,
mon_n_reset => mon_n_reset_o,
mon_n_int => mon_n_int_i,
pll_status => cdce_pll_status,--regs_out.flgs_out_pll_status_i,
pll_status => cdce_pll_status_i, --cdce_pll_status,--regs_out.flgs_out_pll_status_i,
mmcm_adc_locked_o => s_mmcm_adc_locked,--regs_out.flgs_out_adc_clk_locked_i,
odata => regs_out.data_out_i,--s_odata,
busy => regs_out.flgs_out_spi_busy_i,--s_busy,
prsnt_m2c_l => regs_out.flgs_out_fmc_prst_i,--prsnt_m2c_l,
prsnt_m2c_l => prsnt_m2c_l_i,--regs_out.flgs_out_fmc_prst_i,--prsnt_m2c_l,
rd_n_wr => regs_in.flgs_in_spi_rw_o, --s_registers(FLAGS_IN_0)(FLAGS_IN_0_SPI_RW),
addr => regs_in.addr_o, --s_registers(ADDR)(15 downto 0),
......@@ -216,7 +356,9 @@ begin
clk_adc_o => s_clk_adc
);
regs_out.flgs_out_pll_status_i <= cdce_pll_status;
s_fmc150_rst <= not rst_n_i;
--regs_out.flgs_out_pll_status_i <= cdce_pll_status;
regs_out.flgs_out_adc_clk_locked_i <= s_mmcm_adc_locked;
-- Pipelined <--> Classic cycles / Word <--> Byte address granularity
......@@ -228,7 +370,8 @@ begin
g_master_granularity => WORD,
g_slave_use_struct => false,
g_slave_mode => g_interface_mode,
g_slave_granularity => g_address_granularity)
g_slave_granularity => g_address_granularity
)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
......@@ -263,14 +406,16 @@ begin
wb_we_i => wb_in.we,
wb_ack_o => wb_out.ack,
wb_stall_o => wb_out.stall,
clk_100Mhz => clk_100_i,
clk_100Mhz_i => clk_100Mhz_i,
clk_wb_i => clk_sys_i,
regs_i => regs_out,
regs_o => regs_in
);
-- This stream source is in ADC clock domain
cmp_wb_source_if : xwb_stream_source
port map(
clk_i => clk_sys_i,
clk_i => s_clk_adc,
rst_n_i => rst_n_i,
-- Wishbone Fabric Interface I/O
......@@ -284,20 +429,60 @@ begin
sof_i => s_sof,
eof_i => s_eof,
error_i => s_error,
bytesel_i => s_bytesel,
-- For now, just pick the LSB bit of s_bytesel
bytesel_i => s_bytesel(0),
dreq_o => s_dreq
);
s_addr <= (others => '0');
s_data <= s_adc_dout;
s_dvalid <= cdce_pll_status and s_mmcm_adc_locked;
s_addr <= (others => '0');
-- Simulation / Syntesis Only consructs. Is there a better way to do it?
gen_stream_data : if (g_sim = false) generate
s_data <= s_adc_dout(c_wbs_data_width-1 downto 0);
end generate;
gen_stream_data_sim : if (g_sim = true) generate
p_gen_data_sim : process--(s_clk_adc, rst_n_i)
variable seed1, seed2: positive; -- Seed values for random generator
begin
seed1 := 432566;
seed2 := 211;
s_data <= (others => '0');
-- Wait until the next valid clock edge
wait until rst_n_i = '1' and rising_edge(s_clk_adc);
l_generate_data: loop
gen_data(c_wbs_data_width, seed1, seed2, s_data);
wait until rising_edge(s_clk_adc);
end loop;
end process;
end generate;
gen_stream_valid : if (g_sim = false) generate
s_dvalid <= cdce_pll_status_i and s_mmcm_adc_locked;
end generate;
gen_stream_valid_sim : if (g_sim = true) generate
p_gen_valid_sim : process--(s_clk_adc, rst_n_i)
variable seed1, seed2: positive; -- Seed values for random generator
begin
seed1 := 67632;
seed2 := 3234;
s_dvalid <= '0';
-- Wait until the next valid clock edge
wait until rst_n_i = '1' and rising_edge(s_clk_adc);
l_generate_valid: loop
gen_valid(0.5, seed1, seed2, s_dvalid);
wait until rising_edge(s_clk_adc);
end loop;
end process;
end generate;
p_gen_sof_eof : process(s_clk_adc, rst_n_i)
begin
if rst_n_i = '0' then
s_sof <= '0';
s_eof <= '0';
s_wbs_packet_counter <= 0;
s_wbs_packet_counter <= (others => '0');
elsif rising_edge(s_clk_adc) then
-- Defaults assignments
s_sof <= '0';
......@@ -306,20 +491,20 @@ begin
-- Finish current transaction
if(s_wbs_packet_counter = g_packet_size) then
s_eof <= '1';
s_wbs_packet_counter <= 0;
elsif (s_wbs_packet_counter = 0) then
s_wbs_packet_counter <= (others => '0');
elsif (s_wbs_packet_counter = to_unsigned(0, c_counter_size)) then
s_sof <= '1';
end if;
-- Increment counter if data is valid
if s_dvalid then
if s_dvalid = '1' then
s_wbs_packet_counter <= s_wbs_packet_counter + 1;
end if;
end if;
end process;
s_error <= '0';
bytesel_i <= (others => '1');
s_bytesel <= (others => '1');
wbs_adr_o <= wbs_stream_out.adr;
wbs_dat_o <= wbs_stream_out.dat;
......@@ -327,7 +512,9 @@ begin
wbs_stb_o <= wbs_stream_out.cyc;
wbs_we_o <= wbs_stream_out.we;
wbs_sel_o <= wbs_stream_out.sel;
wb_err_o <= '0';
wb_rty_o <= '0';
wbs_stream_in.ack <= wbs_ack_i;
wbs_stream_in.stall <= wbs_stall_i;
wbs_stream_in.err <= wbs_err_i;
......
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wb_fmc150_port.vhd
-- Author : auto-generated by wbgen2 from xfmc150.wb
-- Created : Tue Oct 2 09:38:47 2012
-- Created : Wed Oct 3 10:01:05 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE xfmc150.wb
......@@ -30,7 +30,8 @@ entity wb_fmc150_port is
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
clk_100Mhz : in std_logic;
clk_100Mhz_i : in std_logic;
clk_wb_i : in std_logic;
regs_i : in t_fmc150_in_registers;
regs_o : out t_fmc150_out_registers
);
......@@ -44,16 +45,64 @@ signal fmc150_flgs_pulse_sync0 : std_logic ;
signal fmc150_flgs_pulse_sync1 : std_logic ;
signal fmc150_flgs_pulse_sync2 : std_logic ;
signal fmc150_flgs_in_spi_rw_int : std_logic ;
signal fmc150_flgs_in_spi_rw_sync0 : std_logic ;
signal fmc150_flgs_in_spi_rw_sync1 : std_logic ;
signal fmc150_flgs_in_ext_clk_int : std_logic ;
signal fmc150_flgs_in_ext_clk_sync0 : std_logic ;
signal fmc150_flgs_in_ext_clk_sync1 : std_logic ;
signal fmc150_addr_int : std_logic_vector(15 downto 0);
signal fmc150_addr_swb : std_logic ;
signal fmc150_addr_swb_delay : std_logic ;
signal fmc150_addr_swb_s0 : std_logic ;
signal fmc150_addr_swb_s1 : std_logic ;
signal fmc150_addr_swb_s2 : std_logic ;
signal fmc150_data_in_int : std_logic_vector(31 downto 0);
signal fmc150_data_in_swb : std_logic ;
signal fmc150_data_in_swb_delay : std_logic ;
signal fmc150_data_in_swb_s0 : std_logic ;
signal fmc150_data_in_swb_s1 : std_logic ;
signal fmc150_data_in_swb_s2 : std_logic ;
signal fmc150_cs_cdce72010_int : std_logic ;
signal fmc150_cs_cdce72010_sync0 : std_logic ;
signal fmc150_cs_cdce72010_sync1 : std_logic ;
signal fmc150_cs_ads62p49_int : std_logic ;
signal fmc150_cs_ads62p49_sync0 : std_logic ;
signal fmc150_cs_ads62p49_sync1 : std_logic ;
signal fmc150_cs_dac3283_int : std_logic ;
signal fmc150_cs_dac3283_sync0 : std_logic ;
signal fmc150_cs_dac3283_sync1 : std_logic ;
signal fmc150_cs_amc7823_int : std_logic ;
signal fmc150_cs_amc7823_sync0 : std_logic ;
signal fmc150_cs_amc7823_sync1 : std_logic ;
signal fmc150_adc_dly_str_int : std_logic_vector(4 downto 0);
signal fmc150_adc_dly_str_swb : std_logic ;
signal fmc150_adc_dly_str_swb_delay : std_logic ;
signal fmc150_adc_dly_str_swb_s0 : std_logic ;
signal fmc150_adc_dly_str_swb_s1 : std_logic ;
signal fmc150_adc_dly_str_swb_s2 : std_logic ;
signal fmc150_adc_dly_cha_int : std_logic_vector(4 downto 0);
signal fmc150_adc_dly_cha_swb : std_logic ;
signal fmc150_adc_dly_cha_swb_delay : std_logic ;
signal fmc150_adc_dly_cha_swb_s0 : std_logic ;
signal fmc150_adc_dly_cha_swb_s1 : std_logic ;
signal fmc150_adc_dly_cha_swb_s2 : std_logic ;
signal fmc150_adc_dly_chb_int : std_logic_vector(4 downto 0);
signal fmc150_adc_dly_chb_swb : std_logic ;
signal fmc150_adc_dly_chb_swb_delay : std_logic ;
signal fmc150_adc_dly_chb_swb_s0 : std_logic ;
signal fmc150_adc_dly_chb_swb_s1 : std_logic ;
signal fmc150_adc_dly_chb_swb_s2 : std_logic ;
signal fmc150_data_out_int : std_logic_vector(31 downto 0);
signal fmc150_data_out_lwb : std_logic ;
signal fmc150_data_out_lwb_delay : std_logic ;
signal fmc150_data_out_lwb_in_progress : std_logic ;
signal fmc150_data_out_lwb_s0 : std_logic ;
signal fmc150_data_out_lwb_s1 : std_logic ;
signal fmc150_data_out_lwb_s2 : std_logic ;
signal fmc150_flgs_out_spi_busy_sync0 : std_logic ;
signal fmc150_flgs_out_spi_busy_sync1 : std_logic ;
signal fmc150_flgs_out_adc_clk_locked_sync0 : std_logic ;
signal fmc150_flgs_out_adc_clk_locked_sync1 : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
......@@ -86,14 +135,27 @@ begin
fmc150_flgs_in_spi_rw_int <= '0';
fmc150_flgs_in_ext_clk_int <= '0';
fmc150_addr_int <= "0000000000000000";
fmc150_addr_swb <= '0';
fmc150_addr_swb_delay <= '0';
fmc150_data_in_int <= "00000000000000000000000000000000";
fmc150_data_in_swb <= '0';
fmc150_data_in_swb_delay <= '0';
fmc150_cs_cdce72010_int <= '0';
fmc150_cs_ads62p49_int <= '0';
fmc150_cs_dac3283_int <= '0';
fmc150_cs_amc7823_int <= '0';
fmc150_adc_dly_str_int <= "00000";
fmc150_adc_dly_str_swb <= '0';
fmc150_adc_dly_str_swb_delay <= '0';
fmc150_adc_dly_cha_int <= "00000";
fmc150_adc_dly_cha_swb <= '0';
fmc150_adc_dly_cha_swb_delay <= '0';
fmc150_adc_dly_chb_int <= "00000";
fmc150_adc_dly_chb_swb <= '0';
fmc150_adc_dly_chb_swb_delay <= '0';
fmc150_data_out_lwb <= '0';
fmc150_data_out_lwb_delay <= '0';
fmc150_data_out_lwb_in_progress <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
......@@ -104,6 +166,22 @@ begin
else
fmc150_flgs_pulse_int <= fmc150_flgs_pulse_int_delay;
fmc150_flgs_pulse_int_delay <= '0';
fmc150_addr_swb <= fmc150_addr_swb_delay;
fmc150_addr_swb_delay <= '0';
fmc150_data_in_swb <= fmc150_data_in_swb_delay;
fmc150_data_in_swb_delay <= '0';
fmc150_adc_dly_str_swb <= fmc150_adc_dly_str_swb_delay;
fmc150_adc_dly_str_swb_delay <= '0';
fmc150_adc_dly_cha_swb <= fmc150_adc_dly_cha_swb_delay;
fmc150_adc_dly_cha_swb_delay <= '0';
fmc150_adc_dly_chb_swb <= fmc150_adc_dly_chb_swb_delay;
fmc150_adc_dly_chb_swb_delay <= '0';
fmc150_data_out_lwb <= fmc150_data_out_lwb_delay;
fmc150_data_out_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (fmc150_data_out_lwb_in_progress = '1')) then
rddata_reg(31 downto 0) <= fmc150_data_out_int;
fmc150_data_out_lwb_in_progress <= '0';
end if;
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
......@@ -184,11 +262,13 @@ begin
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "010" =>
if (wb_we_i = '1') then
fmc150_addr_int <= wrdata_reg(15 downto 0);
fmc150_addr_swb <= '1';
fmc150_addr_swb_delay <= '1';
end if;
rddata_reg(15 downto 0) <= fmc150_addr_int;
rddata_reg(16) <= 'X';
......@@ -207,14 +287,16 @@ begin
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "011" =>
if (wb_we_i = '1') then
fmc150_data_in_int <= wrdata_reg(31 downto 0);
fmc150_data_in_swb <= '1';
fmc150_data_in_swb_delay <= '1';
end if;
rddata_reg(31 downto 0) <= fmc150_data_in_int;
ack_sreg(0) <= '1';
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "100" =>
if (wb_we_i = '1') then
......@@ -255,13 +337,19 @@ begin
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "101" =>
if (wb_we_i = '1') then
fmc150_adc_dly_str_int <= wrdata_reg(4 downto 0);
fmc150_adc_dly_str_swb <= '1';
fmc150_adc_dly_str_swb_delay <= '1';
fmc150_adc_dly_cha_int <= wrdata_reg(12 downto 8);
fmc150_adc_dly_cha_swb <= '1';
fmc150_adc_dly_cha_swb_delay <= '1';
fmc150_adc_dly_chb_int <= wrdata_reg(20 downto 16);
fmc150_adc_dly_chb_swb <= '1';
fmc150_adc_dly_chb_swb_delay <= '1';
end if;
rddata_reg(4 downto 0) <= fmc150_adc_dly_str_int;
rddata_reg(12 downto 8) <= fmc150_adc_dly_cha_int;
......@@ -283,21 +371,25 @@ begin
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.data_out_i;
ack_sreg(0) <= '1';
if (wb_we_i = '0') then
fmc150_data_out_lwb <= '1';
fmc150_data_out_lwb_delay <= '1';
fmc150_data_out_lwb_in_progress <= '1';
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= regs_i.flgs_out_spi_busy_i;
rddata_reg(1) <= regs_i.flgs_out_pll_status_i;
rddata_reg(2) <= regs_i.flgs_out_adc_clk_locked_i;
rddata_reg(3) <= regs_i.flgs_out_fmc_prst_i;
rddata_reg(0) <= fmc150_flgs_out_spi_busy_sync1;
rddata_reg(1) <= fmc150_flgs_out_adc_clk_locked_sync1;
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
......@@ -342,14 +434,14 @@ begin
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- Update ADC delay
process (clk_100Mhz, rst_n_i)
process (clk_100Mhz_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.flgs_pulse_o <= '0';
fmc150_flgs_pulse_sync0 <= '0';
fmc150_flgs_pulse_sync1 <= '0';
fmc150_flgs_pulse_sync2 <= '0';
elsif rising_edge(clk_100Mhz) then
elsif rising_edge(clk_100Mhz_i) then
fmc150_flgs_pulse_sync0 <= fmc150_flgs_pulse_int;
fmc150_flgs_pulse_sync1 <= fmc150_flgs_pulse_sync0;
fmc150_flgs_pulse_sync2 <= fmc150_flgs_pulse_sync1;
......@@ -359,32 +451,249 @@ begin
-- SPI Read/Write flag
regs_o.flgs_in_spi_rw_o <= fmc150_flgs_in_spi_rw_int;
-- synchronizer chain for field : SPI Read/Write flag (type RW/RO, clk_sys_i <-> clk_100Mhz_i)
process (clk_100Mhz_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.flgs_in_spi_rw_o <= '0';
fmc150_flgs_in_spi_rw_sync0 <= '0';
fmc150_flgs_in_spi_rw_sync1 <= '0';
elsif rising_edge(clk_100Mhz_i) then
fmc150_flgs_in_spi_rw_sync0 <= fmc150_flgs_in_spi_rw_int;
fmc150_flgs_in_spi_rw_sync1 <= fmc150_flgs_in_spi_rw_sync0;
regs_o.flgs_in_spi_rw_o <= fmc150_flgs_in_spi_rw_sync1;
end if;
end process;
-- External Clock for ADC
regs_o.flgs_in_ext_clk_o <= fmc150_flgs_in_ext_clk_int;
-- synchronizer chain for field : External Clock for ADC (type RW/RO, clk_sys_i <-> clk_100Mhz_i)
process (clk_100Mhz_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.flgs_in_ext_clk_o <= '0';
fmc150_flgs_in_ext_clk_sync0 <= '0';
fmc150_flgs_in_ext_clk_sync1 <= '0';
elsif rising_edge(clk_100Mhz_i) then
fmc150_flgs_in_ext_clk_sync0 <= fmc150_flgs_in_ext_clk_int;
fmc150_flgs_in_ext_clk_sync1 <= fmc150_flgs_in_ext_clk_sync0;
regs_o.flgs_in_ext_clk_o <= fmc150_flgs_in_ext_clk_sync1;
end if;
end process;
-- SPI address
regs_o.addr_o <= fmc150_addr_int;
-- asynchronous std_logic_vector register : SPI address (type RW/RO, clk_100Mhz_i <-> clk_sys_i)
process (clk_100Mhz_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc150_addr_swb_s0 <= '0';
fmc150_addr_swb_s1 <= '0';
fmc150_addr_swb_s2 <= '0';
regs_o.addr_o <= "0000000000000000";
elsif rising_edge(clk_100Mhz_i) then
fmc150_addr_swb_s0 <= fmc150_addr_swb;
fmc150_addr_swb_s1 <= fmc150_addr_swb_s0;
fmc150_addr_swb_s2 <= fmc150_addr_swb_s1;
if ((fmc150_addr_swb_s2 = '0') and (fmc150_addr_swb_s1 = '1')) then
regs_o.addr_o <= fmc150_addr_int;
end if;
end if;
end process;
-- Data In for FMC150
regs_o.data_in_o <= fmc150_data_in_int;
-- asynchronous std_logic_vector register : Data In for FMC150 (type RW/RO, clk_100Mhz_i <-> clk_sys_i)
process (clk_100Mhz_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc150_data_in_swb_s0 <= '0';
fmc150_data_in_swb_s1 <= '0';
fmc150_data_in_swb_s2 <= '0';
regs_o.data_in_o <= "00000000000000000000000000000000";
elsif rising_edge(clk_100Mhz_i) then
fmc150_data_in_swb_s0 <= fmc150_data_in_swb;
fmc150_data_in_swb_s1 <= fmc150_data_in_swb_s0;
fmc150_data_in_swb_s2 <= fmc150_data_in_swb_s1;
if ((fmc150_data_in_swb_s2 = '0') and (fmc150_data_in_swb_s1 = '1')) then
regs_o.data_in_o <= fmc150_data_in_int;
end if;
end if;
end process;
-- Chipselect for cdce72010
regs_o.cs_cdce72010_o <= fmc150_cs_cdce72010_int;
-- synchronizer chain for field : Chipselect for cdce72010 (type RW/RO, clk_sys_i <-> clk_100Mhz_i)
process (clk_100Mhz_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.cs_cdce72010_o <= '0';
fmc150_cs_cdce72010_sync0 <= '0';
fmc150_cs_cdce72010_sync1 <= '0';
elsif rising_edge(clk_100Mhz_i) then
fmc150_cs_cdce72010_sync0 <= fmc150_cs_cdce72010_int;
fmc150_cs_cdce72010_sync1 <= fmc150_cs_cdce72010_sync0;
regs_o.cs_cdce72010_o <= fmc150_cs_cdce72010_sync1;
end if;
end process;
-- Chipselect for ads62p49
regs_o.cs_ads62p49_o <= fmc150_cs_ads62p49_int;
-- synchronizer chain for field : Chipselect for ads62p49 (type RW/RO, clk_sys_i <-> clk_100Mhz_i)
process (clk_100Mhz_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.cs_ads62p49_o <= '0';
fmc150_cs_ads62p49_sync0 <= '0';
fmc150_cs_ads62p49_sync1 <= '0';
elsif rising_edge(clk_100Mhz_i) then
fmc150_cs_ads62p49_sync0 <= fmc150_cs_ads62p49_int;
fmc150_cs_ads62p49_sync1 <= fmc150_cs_ads62p49_sync0;
regs_o.cs_ads62p49_o <= fmc150_cs_ads62p49_sync1;
end if;
end process;
-- Chipselect for dac3283
regs_o.cs_dac3283_o <= fmc150_cs_dac3283_int;
-- synchronizer chain for field : Chipselect for dac3283 (type RW/RO, clk_sys_i <-> clk_100Mhz_i)
process (clk_100Mhz_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.cs_dac3283_o <= '0';
fmc150_cs_dac3283_sync0 <= '0';
fmc150_cs_dac3283_sync1 <= '0';
elsif rising_edge(clk_100Mhz_i) then
fmc150_cs_dac3283_sync0 <= fmc150_cs_dac3283_int;
fmc150_cs_dac3283_sync1 <= fmc150_cs_dac3283_sync0;
regs_o.cs_dac3283_o <= fmc150_cs_dac3283_sync1;
end if;
end process;
-- Chipselect for amc7823
regs_o.cs_amc7823_o <= fmc150_cs_amc7823_int;
-- synchronizer chain for field : Chipselect for amc7823 (type RW/RO, clk_sys_i <-> clk_100Mhz_i)
process (clk_100Mhz_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.cs_amc7823_o <= '0';
fmc150_cs_amc7823_sync0 <= '0';
fmc150_cs_amc7823_sync1 <= '0';
elsif rising_edge(clk_100Mhz_i) then
fmc150_cs_amc7823_sync0 <= fmc150_cs_amc7823_int;
fmc150_cs_amc7823_sync1 <= fmc150_cs_amc7823_sync0;
regs_o.cs_amc7823_o <= fmc150_cs_amc7823_sync1;
end if;
end process;
-- ADC Strobe delay
regs_o.adc_dly_str_o <= fmc150_adc_dly_str_int;
-- asynchronous std_logic_vector register : ADC Strobe delay (type RW/RO, clk_100Mhz_i <-> clk_sys_i)
process (clk_100Mhz_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc150_adc_dly_str_swb_s0 <= '0';
fmc150_adc_dly_str_swb_s1 <= '0';
fmc150_adc_dly_str_swb_s2 <= '0';
regs_o.adc_dly_str_o <= "00000";
elsif rising_edge(clk_100Mhz_i) then
fmc150_adc_dly_str_swb_s0 <= fmc150_adc_dly_str_swb;
fmc150_adc_dly_str_swb_s1 <= fmc150_adc_dly_str_swb_s0;
fmc150_adc_dly_str_swb_s2 <= fmc150_adc_dly_str_swb_s1;
if ((fmc150_adc_dly_str_swb_s2 = '0') and (fmc150_adc_dly_str_swb_s1 = '1')) then
regs_o.adc_dly_str_o <= fmc150_adc_dly_str_int;
end if;
end if;
end process;
-- ADC Channel A delay
regs_o.adc_dly_cha_o <= fmc150_adc_dly_cha_int;
-- asynchronous std_logic_vector register : ADC Channel A delay (type RW/RO, clk_100Mhz_i <-> clk_sys_i)
process (clk_100Mhz_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc150_adc_dly_cha_swb_s0 <= '0';
fmc150_adc_dly_cha_swb_s1 <= '0';
fmc150_adc_dly_cha_swb_s2 <= '0';
regs_o.adc_dly_cha_o <= "00000";
elsif rising_edge(clk_100Mhz_i) then
fmc150_adc_dly_cha_swb_s0 <= fmc150_adc_dly_cha_swb;
fmc150_adc_dly_cha_swb_s1 <= fmc150_adc_dly_cha_swb_s0;
fmc150_adc_dly_cha_swb_s2 <= fmc150_adc_dly_cha_swb_s1;
if ((fmc150_adc_dly_cha_swb_s2 = '0') and (fmc150_adc_dly_cha_swb_s1 = '1')) then
regs_o.adc_dly_cha_o <= fmc150_adc_dly_cha_int;
end if;
end if;
end process;
-- ADC Strobe delay
regs_o.adc_dly_chb_o <= fmc150_adc_dly_chb_int;
-- asynchronous std_logic_vector register : ADC Strobe delay (type RW/RO, clk_100Mhz_i <-> clk_sys_i)
process (clk_100Mhz_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc150_adc_dly_chb_swb_s0 <= '0';
fmc150_adc_dly_chb_swb_s1 <= '0';
fmc150_adc_dly_chb_swb_s2 <= '0';
regs_o.adc_dly_chb_o <= "00000";
elsif rising_edge(clk_100Mhz_i) then
fmc150_adc_dly_chb_swb_s0 <= fmc150_adc_dly_chb_swb;
fmc150_adc_dly_chb_swb_s1 <= fmc150_adc_dly_chb_swb_s0;
fmc150_adc_dly_chb_swb_s2 <= fmc150_adc_dly_chb_swb_s1;
if ((fmc150_adc_dly_chb_swb_s2 = '0') and (fmc150_adc_dly_chb_swb_s1 = '1')) then
regs_o.adc_dly_chb_o <= fmc150_adc_dly_chb_int;
end if;
end if;
end process;
-- Data out from FMC150
-- asynchronous std_logic_vector register : Data out from FMC150 (type RO/WO, clk_wb_i <-> clk_sys_i)
process (clk_wb_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc150_data_out_lwb_s0 <= '0';
fmc150_data_out_lwb_s1 <= '0';
fmc150_data_out_lwb_s2 <= '0';
fmc150_data_out_int <= "00000000000000000000000000000000";
elsif rising_edge(clk_wb_i) then
fmc150_data_out_lwb_s0 <= fmc150_data_out_lwb;
fmc150_data_out_lwb_s1 <= fmc150_data_out_lwb_s0;
fmc150_data_out_lwb_s2 <= fmc150_data_out_lwb_s1;
if ((fmc150_data_out_lwb_s1 = '1') and (fmc150_data_out_lwb_s2 = '0')) then
fmc150_data_out_int <= regs_i.data_out_i;
end if;
end if;
end process;
-- SPI Busy
-- CDCE72010 PLL Status
-- synchronizer chain for field : SPI Busy (type RO/WO, clk_wb_i -> clk_sys_i)
process (clk_wb_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc150_flgs_out_spi_busy_sync0 <= '0';
fmc150_flgs_out_spi_busy_sync1 <= '0';
elsif rising_edge(clk_wb_i) then
fmc150_flgs_out_spi_busy_sync0 <= regs_i.flgs_out_spi_busy_i;
fmc150_flgs_out_spi_busy_sync1 <= fmc150_flgs_out_spi_busy_sync0;
end if;
end process;
-- FPGA ADC clock locked
-- FMC present
-- synchronizer chain for field : FPGA ADC clock locked (type RO/WO, clk_wb_i -> clk_sys_i)
process (clk_wb_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc150_flgs_out_adc_clk_locked_sync0 <= '0';
fmc150_flgs_out_adc_clk_locked_sync1 <= '0';
elsif rising_edge(clk_wb_i) then
fmc150_flgs_out_adc_clk_locked_sync0 <= regs_i.flgs_out_adc_clk_locked_i;
fmc150_flgs_out_adc_clk_locked_sync1 <= fmc150_flgs_out_adc_clk_locked_sync0;
end if;
end process;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
......
......@@ -21,7 +21,7 @@ peripheral {
--prefix = "start";
-- Pulse to start
type = MONOSTABLE;
clock = "clk_100Mhz";
clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -38,7 +38,7 @@ peripheral {
write 0: read from SPI";
prefix = "spi_rw";
type = BIT;
--clock = "";
clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -49,7 +49,7 @@ peripheral {
write 0: internal clock for ADC";
prefix = "ext_clk";
type = BIT;
--clock = "";
clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -66,7 +66,7 @@ peripheral {
--prefix = "addr";
type = SLV;
size = 16;
--clock = "";
clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -83,7 +83,7 @@ peripheral {
--prefix = "data";
type = SLV;
size = 32;
--clock = "";
clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -100,7 +100,7 @@ peripheral {
write 0: no effect";
prefix = "cdce72010";
type = BIT;
--clock = "";
clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -111,7 +111,7 @@ peripheral {
write 0: no effect";
prefix = "ads62p49";
type = BIT;
--clock = "";
clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -122,7 +122,7 @@ peripheral {
write 0: no effect";
prefix = "dac3283";
type = BIT;
--clock = "";
clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -133,7 +133,7 @@ peripheral {
write 0: no effect";
prefix = "amc7823";
type = BIT;
--clock = "";
clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -151,7 +151,7 @@ peripheral {
type = SLV;
size = 5;
align = 8;
--clock = "";
clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -163,7 +163,7 @@ peripheral {
type = SLV;
size = 5;
align = 8;
--clock = "";
clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -175,11 +175,18 @@ peripheral {
type = SLV;
size = 5;
align = 8;
--clock = "";
clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-- The following registers are within the clk_100Mhz_i domain.
-- Therefore, in order to read it from the bus, we need
-- to synchronize them to clk_wb_i (wishbone control clock) domain.
-- Note that clk_wb_i must be connected to the same clock as clk_sys_i.
-- It is just a diferent name to the same port, to avoid naming
-- conflicts as generated by wbgen2.
-- Data Out
reg {
......@@ -192,7 +199,8 @@ peripheral {
--prefix = "data";
type = SLV;
size = 32;
--clock = "";
--clock = "clk_100Mhz";
clock = "clk_wb_i";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
......@@ -209,21 +217,23 @@ peripheral {
read 0: spi idle";
prefix = "spi_busy";
type = BIT;
--clock = "";
--clock = "clk_100Mhz";
clock = "clk_wb_i";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "CDCE72010 PLL Status";
description = "read 1: PLL locked.\
read 0: PLL not locked";
prefix = "pll_status";
type = BIT;
--clock = "";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
--field {
-- name = "CDCE72010 PLL Status";
-- description = "read 1: PLL locked.\
-- read 0: PLL not locked";
-- prefix = "pll_status";
-- type = BIT;
-- --clock = "clk_100Mhz";
-- clock = "clk_wb_i";
-- access_bus = READ_ONLY;
-- access_dev = WRITE_ONLY;
--};
field {
name = "FPGA ADC clock locked";
......@@ -231,21 +241,23 @@ peripheral {
read 0: FPGA ADC PLL not locked";
prefix = "adc_clk_locked";
type = BIT;
--clock = "";
--clock = "clk_100Mhz";
clock = "clk_wb_i";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "FMC present";
description = "read 1: FMC present.\
read 0: FMC not present";
prefix = "fmc_prst";
type = BIT;
--clock = "";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
--field {
-- name = "FMC present";
-- description = "read 1: FMC present.\
-- read 0: FMC not present";
-- prefix = "fmc_prst";
-- type = BIT;
-- --clock = "clk_100Mhz";
-- clock = "clk_wb_i";
-- access_bus = READ_ONLY;
-- access_dev = WRITE_ONLY;
--};
};
};
......
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : xfmc150_regs_pkg.vhd
-- Author : auto-generated by wbgen2 from xfmc150.wb
-- Created : Tue Oct 2 09:38:47 2012
-- Created : Wed Oct 3 10:01:05 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE xfmc150.wb
......@@ -22,17 +22,13 @@ package fmc150_wbgen2_pkg is
type t_fmc150_in_registers is record
data_out_i : std_logic_vector(31 downto 0);
flgs_out_spi_busy_i : std_logic;
flgs_out_pll_status_i : std_logic;
flgs_out_adc_clk_locked_i : std_logic;
flgs_out_fmc_prst_i : std_logic;
end record;
constant c_fmc150_in_registers_init_value: t_fmc150_in_registers := (
data_out_i => (others => '0'),
flgs_out_spi_busy_i => '0',
flgs_out_pll_status_i => '0',
flgs_out_adc_clk_locked_i => '0',
flgs_out_fmc_prst_i => '0'
flgs_out_adc_clk_locked_i => '0'
);
-- Output registers (WB slave -> user design)
......@@ -97,9 +93,7 @@ variable tmp: t_fmc150_in_registers;
begin
tmp.data_out_i := f_x_to_zero(left.data_out_i) or f_x_to_zero(right.data_out_i);
tmp.flgs_out_spi_busy_i := f_x_to_zero(left.flgs_out_spi_busy_i) or f_x_to_zero(right.flgs_out_spi_busy_i);
tmp.flgs_out_pll_status_i := f_x_to_zero(left.flgs_out_pll_status_i) or f_x_to_zero(right.flgs_out_pll_status_i);
tmp.flgs_out_adc_clk_locked_i := f_x_to_zero(left.flgs_out_adc_clk_locked_i) or f_x_to_zero(right.flgs_out_adc_clk_locked_i);
tmp.flgs_out_fmc_prst_i := f_x_to_zero(left.flgs_out_fmc_prst_i) or f_x_to_zero(right.flgs_out_fmc_prst_i);
return tmp;
end function;
end package body;
......@@ -3,7 +3,7 @@
* File : xfmc150_regs_regs.h
* Author : auto-generated by wbgen2 from xfmc150.wb
* Created : Tue Oct 2 09:38:47 2012
* Created : Wed Oct 3 10:01:05 2012
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE xfmc150.wb
......@@ -86,14 +86,8 @@
/* definitions for field: SPI Busy in reg: Flags out from Chips on FMC150 */
#define FMC150_FLGS_OUT_SPI_BUSY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: CDCE72010 PLL Status in reg: Flags out from Chips on FMC150 */
#define FMC150_FLGS_OUT_PLL_STATUS WBGEN2_GEN_MASK(1, 1)
/* definitions for field: FPGA ADC clock locked in reg: Flags out from Chips on FMC150 */
#define FMC150_FLGS_OUT_ADC_CLK_LOCKED WBGEN2_GEN_MASK(2, 1)
/* definitions for field: FMC present in reg: Flags out from Chips on FMC150 */
#define FMC150_FLGS_OUT_FMC_PRST WBGEN2_GEN_MASK(3, 1)
#define FMC150_FLGS_OUT_ADC_CLK_LOCKED WBGEN2_GEN_MASK(1, 1)
PACKED struct FMC150_WB {
/* [0x0]: REG Input Flags for Pulsing Registers */
......
......@@ -3,6 +3,11 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Custom Wishbone Modules
use work.custom_wishbone_pkg.all;
-- Wishbone Stream Interface
use work.wb_stream_pkg.all;
entity xwb_fmc150 is
......@@ -10,7 +15,8 @@ generic
(
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_packet_size : natural := 32
g_packet_size : natural := 32;
g_sim : boolean := false
);
port
(
......@@ -23,8 +29,8 @@ port
-- Wishbone signals
-----------------------------
wb_slv_i : t_wishbone_slave_in;
wb_slv_o : t_wishbone_slave_out;
wb_slv_i : in t_wishbone_slave_in;
wb_slv_o : out t_wishbone_slave_out;
-----------------------------
-- External ports
......@@ -47,10 +53,10 @@ port
txenable_o : out std_logic;
--Clock/Trigger connection to FMC150
clk_to_fpga_p_i : in std_logic;
clk_to_fpga_n_i : in std_logic;
ext_trigger_p_i : in std_logic;
ext_trigger_n_i : in std_logic;
--clk_to_fpga_p_i : in std_logic;
--clk_to_fpga_n_i : in std_logic;
--ext_trigger_p_i : in std_logic;
--ext_trigger_n_i : in std_logic;
-- Control signals from/to FMC150
--Serial Peripheral Interface (SPI)
......@@ -95,7 +101,10 @@ architecture rtl of xwb_fmc150 is
component wb_fmc150
generic
(
g_packet_size : natural := 32
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_packet_size : natural := 32;
g_sim : boolean := false
);
port
(
......@@ -141,10 +150,10 @@ architecture rtl of xwb_fmc150 is
txenable_o : out std_logic;
--Clock/Trigger connection to FMC150
clk_to_fpga_p_i : in std_logic;
clk_to_fpga_n_i : in std_logic;
ext_trigger_p_i : in std_logic;
ext_trigger_n_i : in std_logic;
--clk_to_fpga_p_i : in std_logic;
--clk_to_fpga_n_i : in std_logic;
--ext_trigger_p_i : in std_logic;
--ext_trigger_n_i : in std_logic;
-- Control signals from/to FMC150
--Serial Peripheral Interface (SPI)
......@@ -197,9 +206,12 @@ begin
cmp_wb_fmc150 : wb_fmc150
generic map
(
g_packet_size => g_packet_size
);
port
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity,
g_packet_size => g_packet_size,
g_sim => g_sim
)
port map
(
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
......@@ -210,17 +222,17 @@ begin
-- Wishbone signals
-----------------------------
wb_adr_i => wb_slave_i.adr,
wb_dat_i => wb_slave_i.dat,
wb_dat_o => wb_slave_o.dat,
wb_sel_i => wb_slave_i.sel,
wb_we_i => wb_slave_i.we,
wb_cyc_i => wb_slave_i.cyc,
wb_stb_i => wb_slave_i.stb,
wb_ack_o => wb_slave_o.ack,
wb_err_o => wb_slave_o.err,
wb_rty_o => wb_slave_o.rty,
wb_stall_o => wb_slave_o.stall,
wb_adr_i => wb_slv_i.adr,
wb_dat_i => wb_slv_i.dat,
wb_dat_o => wb_slv_o.dat,
wb_sel_i => wb_slv_i.sel,
wb_we_i => wb_slv_i.we,
wb_cyc_i => wb_slv_i.cyc,
wb_stb_i => wb_slv_i.stb,
wb_ack_o => wb_slv_o.ack,
wb_err_o => wb_slv_o.err,
wb_rty_o => wb_slv_o.rty,
wb_stall_o => wb_slv_o.stall,
-----------------------------
-- External ports
......@@ -243,10 +255,10 @@ begin
txenable_o => txenable_o,
--Clock/Trigger connection to FMC150
clk_to_fpga_p_i => clk_to_fpga_p_i,
clk_to_fpga_n_i => clk_to_fpga_n_i,
ext_trigger_p_i => ext_trigger_p_i,
ext_trigger_n_i => ext_trigger_n_i,
--clk_to_fpga_p_i => clk_to_fpga_p_i,
--clk_to_fpga_n_i => clk_to_fpga_n_i,
--ext_trigger_p_i => ext_trigger_p_i,
--ext_trigger_n_i => ext_trigger_n_i,
-- Control signals from/to FMC150
--Serial Peripheral Interface (SPI)
......@@ -254,17 +266,17 @@ begin
spi_sdata_o => spi_sdata_o, -- Shared SPI data line
-- ADC specific signals
adc_n_en_o => adc_n_en_o -- SPI chip select
adc_sdo_i => adc_sdo_i -- SPI data out
adc_reset_o => adc_reset_o -- SPI reset
adc_n_en_o => adc_n_en_o, -- SPI chip select
adc_sdo_i => adc_sdo_i, -- SPI data out
adc_reset_o => adc_reset_o, -- SPI reset
-- CDCE specific signals
cdce_n_en_o => cdce_n_en_o -- SPI chip select
cdce_sdo_i => cdce_sdo_i -- SPI data out
cdce_n_reset_o => cdce_n_reset_o
cdce_n_pd_o => cdce_n_pd_o
cdce_ref_en_o => cdce_ref_en_o
cdce_pll_status_i => cdce_pll_status_i
cdce_n_en_o => cdce_n_en_o, -- SPI chip select
cdce_sdo_i => cdce_sdo_i, -- SPI data out
cdce_n_reset_o => cdce_n_reset_o,
cdce_n_pd_o => cdce_n_pd_o,
cdce_ref_en_o => cdce_ref_en_o,
cdce_pll_status_i => cdce_pll_status_i,
-- DAC specific signals
dac_n_en_o => dac_n_en_o, -- SPI chip select
......@@ -293,6 +305,6 @@ begin
wbs_rty_i => wbs_source_i.rty
);
wb_slave_o.int <= '0';
wb_slv_o.int <= '0';
end rtl;
......@@ -18,10 +18,10 @@ package wb_stream_pkg is
subtype t_wbs_byte_select is
std_logic_vector((c_wbs_data_width/8)-1 downto 0);
constant c_WRF_DATA : unsigned(c_wbs_address_width-1 downto 0) := to_unsigned(0, c_wbs_address_width);
constant c_WRF_OOB : unsigned(c_wbs_address_width-1 downto 0) := to_unsigned(1, c_wbs_address_width);
constant c_WRF_STATUS : unsigned(c_wbs_address_width-1 downto 0) := to_unsigned(2, c_wbs_address_width);
constant c_WRF_USER : unsigned(c_wbs_address_width-1 downto 0) := to_unsigned(3, c_wbs_address_width);
constant c_WBS_DATA : unsigned(c_wbs_address_width-1 downto 0) := to_unsigned(0, c_wbs_address_width);
constant c_WBS_OOB : unsigned(c_wbs_address_width-1 downto 0) := to_unsigned(1, c_wbs_address_width);
constant c_WBS_STATUS : unsigned(c_wbs_address_width-1 downto 0) := to_unsigned(2, c_wbs_address_width);
constant c_WBS_USER : unsigned(c_wbs_address_width-1 downto 0) := to_unsigned(3, c_wbs_address_width);
--constant c_WRF_OOB_TYPE_RX : std_logic_vector(3 downto 0) := "0000";
--constant c_WRF_OOB_TYPE_TX : std_logic_vector(3 downto 0) := "0001";
......@@ -79,13 +79,13 @@ package wb_stream_pkg is
constant cc_dummy_wbs_sel : std_logic_vector(c_wbs_data_width/8-1 downto 0) :=
(others => 'X');
constant c_dummy_src_in : t_wbs_source_in :=
constant cc_dummy_src_in : t_wbs_source_in :=
('0', '0', '0', '0');
constant c_dummy_snk_in : t_wbs_sink_in :=
constant cc_dummy_snk_in : t_wbs_sink_in :=
(cc_dummy_wbs_addr, cc_dummy_wbs_dat, '0', '0', '0', cc_dummy_wbs_sel);
-- Components
component xwb_stream_source
component xwb_stream_source
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
......@@ -130,9 +130,7 @@ package wb_stream_pkg is
end wb_stream_pkg;
package body wb_stream_pkg is
function f_marshall_wbs_status(stat : t_wbs_status_reg)
return std_logic_vector
is
......
......@@ -66,9 +66,9 @@ entity xwb_stream_sink is
dreq_i : in std_logic
);
end xwb_fabric_sink;
end xwb_stream_sink;
architecture rtl of xwb_fabric_sink is
architecture rtl of xwb_stream_sink is
constant c_logic_width : integer := 4;
constant c_fifo_width : integer := c_wbs_data_width + c_wbs_address_width + 4;
......@@ -138,7 +138,7 @@ begin -- rtl
we <= '1' when fin(c_logic_range) /= "0000" and full = '0' else '0';
rd <= q_valid and dreq_i and not post_sof;
U_FIFO : generic_shiftreg_fifo
cmp_fifo : generic_shiftreg_fifo
generic map (
g_data_width => c_fifo_width,
g_size => c_fifo_depth
......@@ -173,7 +173,7 @@ begin -- rtl
sof_o <= post_sof and rd_d0;
dvalid_o <= post_dvalid and rd_d0;
error_o <= '1' when rd_d0 = '1' and (post_addr = std_logic_vector(c_WRF_STATUS)) and (f_unmarshall_wrf_status(post_data).error = '1') else '0';
error_o <= '1' when rd_d0 = '1' and (post_addr = std_logic_vector(c_WBS_STATUS)) and (f_unmarshall_wbs_status(post_data).error = '1') else '0';
eof_o <= fout_reg(c_logic_start+2) and rd_d0;
bytesel_o <= fout_reg(c_logic_start+1);
data_o <= post_data;
......@@ -239,7 +239,7 @@ architecture wrapper of wb_stream_sink is
begin -- wrapper
U_Wrapped_Sink : xwb_stream_sink
cmp_stream_sink_wrapper : xwb_stream_sink
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
......
......@@ -28,12 +28,12 @@ entity xwb_stream_source is
dreq_o : out std_logic
);
end xwb_fabric_source;
end xwb_stream_source;
architecture rtl of xwb_fabric_source is
architecture rtl of xwb_stream_source is
constant c_logic_width : integer := 4;
constant c_fifo_width : integer := c_wbs_data_width + c_wbs_address_width + 4;
constant c_fifo_width : integer := c_wbs_data_width + c_wbs_address_width + c_logic_width;
constant c_fifo_depth : integer := 32;
constant c_logic_start : integer := c_wbs_data_width + c_wbs_address_width;
......@@ -57,7 +57,7 @@ architecture rtl of xwb_fabric_source is
signal post_dvalid, post_eof, post_bytesel, post_sof : std_logic;
signal err_status : t_wrf_status_reg;
signal err_status : t_wbs_status_reg;
signal cyc_int : std_logic;
begin -- rtl
......@@ -70,13 +70,13 @@ begin -- rtl
we <= sof_i or eof_i or error_i or dvalid_i;
pre_dvalid <= dvalid_i or error_i;
pre_data <= data_i when (error_i = '0') else f_marshall_wrf_status(err_status);
pre_addr <= addr_i when (error_i = '0') else std_logic_vector(c_WRF_STATUS);
pre_data <= data_i when (error_i = '0') else f_marshall_wbs_status(err_status);
pre_addr <= addr_i when (error_i = '0') else std_logic_vector(c_WBS_STATUS);
pre_eof <= error_i or eof_i;
fin <= sof_i & pre_eof & bytesel_i & pre_dvalid & pre_addr & pre_data;
U_FIFO : generic_shiftreg_fifo
cmp_fifo : generic_shiftreg_fifo
generic map (
g_data_width => c_fifo_width,
g_size => c_fifo_depth
......@@ -158,8 +158,8 @@ entity wb_stream_source is
end wb_stream_source;
architecture wrapper of wb_fabric_source is
component xwb_fabric_source
architecture wrapper of wb_stream_source is
component xwb_stream_source
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
......@@ -180,7 +180,7 @@ architecture wrapper of wb_fabric_source is
begin -- wrapper
U_Wrapped_Source : xwb_fabric_source
cmp_stream_source_wrapper : xwb_stream_source
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
......@@ -193,7 +193,8 @@ begin -- wrapper
eof_i => eof_i,
error_i => error_i,
bytesel_i => bytesel_i,
dreq_o => dreq_o);
dreq_o => dreq_o
);
src_cyc_o <= src_out.cyc;
src_stb_o <= src_out.stb;
......
......@@ -26,9 +26,5 @@
`define ADDR_FMC150_FLGS_OUT 5'h1c
`define FMC150_FLGS_OUT_SPI_BUSY_OFFSET 0
`define FMC150_FLGS_OUT_SPI_BUSY 32'h00000001
`define FMC150_FLGS_OUT_PLL_STATUS_OFFSET 1
`define FMC150_FLGS_OUT_PLL_STATUS 32'h00000002
`define FMC150_FLGS_OUT_ADC_CLK_LOCKED_OFFSET 2
`define FMC150_FLGS_OUT_ADC_CLK_LOCKED 32'h00000004
`define FMC150_FLGS_OUT_FMC_PRST_OFFSET 3
`define FMC150_FLGS_OUT_FMC_PRST 32'h00000008
`define FMC150_FLGS_OUT_ADC_CLK_LOCKED_OFFSET 1
`define FMC150_FLGS_OUT_ADC_CLK_LOCKED 32'h00000002
......@@ -343,6 +343,7 @@ work/wb_fmc150_tb/.wb_fmc150_tb_vhd: wb_fmc150_tb.vhd work/wb_fmc150_tb/.wb_fmc1
work/wb_fmc150_tb/.wb_fmc150_tb: \
work/wishbone_pkg/.wishbone_pkg_vhd \
work/xfmc150_regs_pkg/.xfmc150_regs_pkg_vhd \
work/wb_stream_pkg/.wb_stream_pkg_vhd \
work/custom_wishbone_pkg/.custom_wishbone_pkg_vhd
......@@ -352,7 +353,8 @@ work/custom_wishbone_pkg/.custom_wishbone_pkg_vhd: ../../../modules/custom_wishb
work/custom_wishbone_pkg/.custom_wishbone_pkg: \
work/wishbone_pkg/.wishbone_pkg_vhd
work/wishbone_pkg/.wishbone_pkg_vhd \
work/wb_stream_pkg/.wb_stream_pkg_vhd
work/custom_common_pkg/.custom_common_pkg_vhd: ../../../modules/custom_common/custom_common_pkg.vhd work/custom_common_pkg/.custom_common_pkg
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
......@@ -392,7 +394,10 @@ work/wb_fmc150/.wb_fmc150_vhd: ../../../modules/custom_wishbone/wb_fmc150/wb_fmc
work/wb_fmc150/.wb_fmc150: \
work/wb_stream_pkg/.wb_stream_pkg_vhd
work/wishbone_pkg/.wishbone_pkg_vhd \
work/xfmc150_regs_pkg/.xfmc150_regs_pkg_vhd \
work/wb_stream_pkg/.wb_stream_pkg_vhd \
work/custom_wishbone_pkg/.custom_wishbone_pkg_vhd
work/xwb_fmc150/.xwb_fmc150_vhd: ../../../modules/custom_wishbone/wb_fmc150/xwb_fmc150.vhd work/xwb_fmc150/.xwb_fmc150
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
......@@ -400,7 +405,9 @@ work/xwb_fmc150/.xwb_fmc150_vhd: ../../../modules/custom_wishbone/wb_fmc150/xwb_
work/xwb_fmc150/.xwb_fmc150: \
work/wb_stream_pkg/.wb_stream_pkg_vhd
work/wishbone_pkg/.wishbone_pkg_vhd \
work/wb_stream_pkg/.wb_stream_pkg_vhd \
work/custom_wishbone_pkg/.custom_wishbone_pkg_vhd
work/xfmc150_regs_pkg/.xfmc150_regs_pkg_vhd: ../../../modules/custom_wishbone/wb_fmc150/xfmc150_regs_pkg.vhd work/xfmc150_regs_pkg/.xfmc150_regs_pkg
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
......
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"../../../modules/custom_wishbone/custom_wishbone_pkg.vhd" Line 198: &lt;<arg fmt="%s" index="1">c_wbs_address_width</arg>&gt; is not declared.
</msg>
<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"../../../modules/custom_wishbone/custom_wishbone_pkg.vhd" Line 199: &lt;<arg fmt="%s" index="1">c_wbs_data_width</arg>&gt; is not declared.
</msg>
<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"../../../modules/custom_wishbone/custom_wishbone_pkg.vhd" Line 203: &lt;<arg fmt="%s" index="1">c_wbs_data_width</arg>&gt; is not declared.
</msg>
<msg type="error" file="HDLCompiler" num="806" delta="unknown" >"../../../modules/custom_wishbone/custom_wishbone_pkg.vhd" Line 212: Syntax error near &quot;<arg fmt="%s" index="1">entity</arg>&quot;.
</msg>
<msg type="error" file="HDLCompiler" num="854" delta="unknown" >"../../../modules/custom_wishbone/custom_wishbone_pkg.vhd" Line 7: Unit &lt;<arg fmt="%s" index="1">custom_wishbone_pkg</arg>&gt; ignored due to previous errors.
</msg>
</messages>
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="./isim.wdb" id="1" type="auto">
<top_modules>
<top_module name="adc_pkg" />
<top_module name="attributes" />
<top_module name="custom_wishbone_pkg" />
<top_module name="fmc150_pkg" />
<top_module name="fmc150_wbgen2_pkg" />
<top_module name="genram_pkg" />
<top_module name="math_real" />
<top_module name="numeric_std" />
<top_module name="std_logic_1164" />
<top_module name="std_logic_arith" />
<top_module name="std_logic_misc" />
<top_module name="std_logic_unsigned" />
<top_module name="textio" />
<top_module name="vcomponents" />
<top_module name="vital_primitives" />
<top_module name="vital_timing" />
<top_module name="vpkg" />
<top_module name="wb_fmc150_tb" />
<top_module name="wb_stream_pkg" />
<top_module name="wishbone_pkg" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="97" />
<wvobject fp_name="/wb_fmc150_tb/clk_100mhz" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk_100mhz</obj_property>
<obj_property name="ObjectShortName">clk_100mhz</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/clk_200mhz" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk_200mhz</obj_property>
<obj_property name="ObjectShortName">clk_200mhz</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/clk_sys" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk_sys</obj_property>
<obj_property name="ObjectShortName">clk_sys</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/rst_n_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst_n_i</obj_property>
<obj_property name="ObjectShortName">rst_n_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/wb_slv_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wb_slv_in</obj_property>
<obj_property name="ObjectShortName">wb_slv_in</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/wb_slv_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wb_slv_out</obj_property>
<obj_property name="ObjectShortName">wb_slv_out</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/wbs_src_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wbs_src_in</obj_property>
<obj_property name="ObjectShortName">wbs_src_in</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/wbs_src_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wbs_src_out</obj_property>
<obj_property name="ObjectShortName">wbs_src_out</obj_property>
</wvobject>
<wvobject fp_name="divider71" type="divider">
<obj_property name="label">fmc150</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="BkColor">128 128 255</obj_property>
<obj_property name="TextColor">230 230 230</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/rst_n_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst_n_i</obj_property>
<obj_property name="ObjectShortName">rst_n_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/clk_sys_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk_sys_i</obj_property>
<obj_property name="ObjectShortName">clk_sys_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/clk_100mhz_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk_100mhz_i</obj_property>
<obj_property name="ObjectShortName">clk_100mhz_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/clk_200mhz_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk_200mhz_i</obj_property>
<obj_property name="ObjectShortName">clk_200mhz_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/wb_adr_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wb_adr_i[31:0]</obj_property>
<obj_property name="ObjectShortName">wb_adr_i[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/wb_dat_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wb_dat_i[31:0]</obj_property>
<obj_property name="ObjectShortName">wb_dat_i[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/wb_dat_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wb_dat_o[31:0]</obj_property>
<obj_property name="ObjectShortName">wb_dat_o[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/wb_sel_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wb_sel_i[3:0]</obj_property>
<obj_property name="ObjectShortName">wb_sel_i[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/wb_we_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wb_we_i</obj_property>
<obj_property name="ObjectShortName">wb_we_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/wb_cyc_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wb_cyc_i</obj_property>
<obj_property name="ObjectShortName">wb_cyc_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/wb_stb_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wb_stb_i</obj_property>
<obj_property name="ObjectShortName">wb_stb_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/wb_ack_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wb_ack_o</obj_property>
<obj_property name="ObjectShortName">wb_ack_o</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/wb_err_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wb_err_o</obj_property>
<obj_property name="ObjectShortName">wb_err_o</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/wb_rty_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wb_rty_o</obj_property>
<obj_property name="ObjectShortName">wb_rty_o</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/wb_stall_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wb_stall_o</obj_property>
<obj_property name="ObjectShortName">wb_stall_o</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/adc_clk_ab_p_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">adc_clk_ab_p_i</obj_property>
<obj_property name="ObjectShortName">adc_clk_ab_p_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/adc_clk_ab_n_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">adc_clk_ab_n_i</obj_property>
<obj_property name="ObjectShortName">adc_clk_ab_n_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/adc_cha_p_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">adc_cha_p_i[6:0]</obj_property>
<obj_property name="ObjectShortName">adc_cha_p_i[6:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/adc_cha_n_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">adc_cha_n_i[6:0]</obj_property>
<obj_property name="ObjectShortName">adc_cha_n_i[6:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/adc_chb_p_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">adc_chb_p_i[6:0]</obj_property>
<obj_property name="ObjectShortName">adc_chb_p_i[6:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/adc_chb_n_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">adc_chb_n_i[6:0]</obj_property>
<obj_property name="ObjectShortName">adc_chb_n_i[6:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/dac_dclk_p_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">dac_dclk_p_o</obj_property>
<obj_property name="ObjectShortName">dac_dclk_p_o</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/dac_dclk_n_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">dac_dclk_n_o</obj_property>
<obj_property name="ObjectShortName">dac_dclk_n_o</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/dac_data_p_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dac_data_p_o[7:0]</obj_property>
<obj_property name="ObjectShortName">dac_data_p_o[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/dac_data_n_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dac_data_n_o[7:0]</obj_property>
<obj_property name="ObjectShortName">dac_data_n_o[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/dac_frame_p_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">dac_frame_p_o</obj_property>
<obj_property name="ObjectShortName">dac_frame_p_o</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/dac_frame_n_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">dac_frame_n_o</obj_property>
<obj_property name="ObjectShortName">dac_frame_n_o</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/txenable_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">txenable_o</obj_property>
<obj_property name="ObjectShortName">txenable_o</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/spi_sclk_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">spi_sclk_o</obj_property>
<obj_property name="ObjectShortName">spi_sclk_o</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/spi_sdata_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">spi_sdata_o</obj_property>
<obj_property name="ObjectShortName">spi_sdata_o</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/adc_n_en_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">adc_n_en_o</obj_property>
<obj_property name="ObjectShortName">adc_n_en_o</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/adc_sdo_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">adc_sdo_i</obj_property>
<obj_property name="ObjectShortName">adc_sdo_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/adc_reset_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">adc_reset_o</obj_property>
<obj_property name="ObjectShortName">adc_reset_o</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/cdce_n_en_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">cdce_n_en_o</obj_property>
<obj_property name="ObjectShortName">cdce_n_en_o</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/cdce_sdo_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">cdce_sdo_i</obj_property>
<obj_property name="ObjectShortName">cdce_sdo_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/cdce_n_reset_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">cdce_n_reset_o</obj_property>
<obj_property name="ObjectShortName">cdce_n_reset_o</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/cdce_n_pd_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">cdce_n_pd_o</obj_property>
<obj_property name="ObjectShortName">cdce_n_pd_o</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/cdce_ref_en_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">cdce_ref_en_o</obj_property>
<obj_property name="ObjectShortName">cdce_ref_en_o</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/cdce_pll_status_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">cdce_pll_status_i</obj_property>
<obj_property name="ObjectShortName">cdce_pll_status_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/dac_n_en_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">dac_n_en_o</obj_property>
<obj_property name="ObjectShortName">dac_n_en_o</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/dac_sdo_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">dac_sdo_i</obj_property>
<obj_property name="ObjectShortName">dac_sdo_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/mon_n_en_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">mon_n_en_o</obj_property>
<obj_property name="ObjectShortName">mon_n_en_o</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/mon_sdo_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">mon_sdo_i</obj_property>
<obj_property name="ObjectShortName">mon_sdo_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/mon_n_reset_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">mon_n_reset_o</obj_property>
<obj_property name="ObjectShortName">mon_n_reset_o</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/mon_n_int_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">mon_n_int_i</obj_property>
<obj_property name="ObjectShortName">mon_n_int_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/prsnt_m2c_l_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">prsnt_m2c_l_i</obj_property>
<obj_property name="ObjectShortName">prsnt_m2c_l_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/wbs_adr_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wbs_adr_o[3:0]</obj_property>
<obj_property name="ObjectShortName">wbs_adr_o[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/wbs_dat_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wbs_dat_o[31:0]</obj_property>
<obj_property name="ObjectShortName">wbs_dat_o[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/wbs_cyc_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wbs_cyc_o</obj_property>
<obj_property name="ObjectShortName">wbs_cyc_o</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/wbs_stb_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wbs_stb_o</obj_property>
<obj_property name="ObjectShortName">wbs_stb_o</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/wbs_we_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wbs_we_o</obj_property>
<obj_property name="ObjectShortName">wbs_we_o</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/wbs_sel_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wbs_sel_o[3:0]</obj_property>
<obj_property name="ObjectShortName">wbs_sel_o[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/wbs_ack_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wbs_ack_i</obj_property>
<obj_property name="ObjectShortName">wbs_ack_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/wbs_stall_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wbs_stall_i</obj_property>
<obj_property name="ObjectShortName">wbs_stall_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/wbs_err_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wbs_err_i</obj_property>
<obj_property name="ObjectShortName">wbs_err_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/wbs_rty_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wbs_rty_i</obj_property>
<obj_property name="ObjectShortName">wbs_rty_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/s_mmcm_adc_locked" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">s_mmcm_adc_locked</obj_property>
<obj_property name="ObjectShortName">s_mmcm_adc_locked</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/s_adc_dout" type="array" db_ref_id="1">
<obj_property name="ElementShortName">s_adc_dout[31:0]</obj_property>
<obj_property name="ObjectShortName">s_adc_dout[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/s_clk_adc" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">s_clk_adc</obj_property>
<obj_property name="ObjectShortName">s_clk_adc</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/s_fmc150_rst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">s_fmc150_rst</obj_property>
<obj_property name="ObjectShortName">s_fmc150_rst</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/s_wbs_packet_counter" type="array" db_ref_id="1">
<obj_property name="ElementShortName">s_wbs_packet_counter[4:0]</obj_property>
<obj_property name="ObjectShortName">s_wbs_packet_counter[4:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/s_addr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">s_addr[3:0]</obj_property>
<obj_property name="ObjectShortName">s_addr[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/s_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">s_data[31:0]</obj_property>
<obj_property name="ObjectShortName">s_data[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/s_dvalid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">s_dvalid</obj_property>
<obj_property name="ObjectShortName">s_dvalid</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/s_sof" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">s_sof</obj_property>
<obj_property name="ObjectShortName">s_sof</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/s_eof" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">s_eof</obj_property>
<obj_property name="ObjectShortName">s_eof</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/s_error" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">s_error</obj_property>
<obj_property name="ObjectShortName">s_error</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/s_bytesel" type="array" db_ref_id="1">
<obj_property name="ElementShortName">s_bytesel[3:0]</obj_property>
<obj_property name="ObjectShortName">s_bytesel[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/s_dreq" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">s_dreq</obj_property>
<obj_property name="ObjectShortName">s_dreq</obj_property>
</wvobject>
<wvobject fp_name="divider213" type="divider">
<obj_property name="label">cmp_wb_source</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="BkColor">128 128 255</obj_property>
<obj_property name="TextColor">230 230 230</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/cmp_wb_source_if/clk_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk_i</obj_property>
<obj_property name="ObjectShortName">clk_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/cmp_wb_source_if/rst_n_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst_n_i</obj_property>
<obj_property name="ObjectShortName">rst_n_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/cmp_wb_source_if/src_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">src_i</obj_property>
<obj_property name="ObjectShortName">src_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/cmp_wb_source_if/src_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">src_o</obj_property>
<obj_property name="ObjectShortName">src_o</obj_property>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/cmp_wb_source_if/src_o.adr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.adr</obj_property>
<obj_property name="ObjectShortName">src_o.adr</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/cmp_wb_source_if/src_o.dat" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.dat</obj_property>
<obj_property name="ObjectShortName">src_o.dat</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/cmp_wb_source_if/src_o.cyc" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">.cyc</obj_property>
<obj_property name="ObjectShortName">src_o.cyc</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/cmp_wb_source_if/src_o.stb" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">.stb</obj_property>
<obj_property name="ObjectShortName">src_o.stb</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/cmp_wb_source_if/src_o.we" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">.we</obj_property>
<obj_property name="ObjectShortName">src_o.we</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/cmp_wb_source_if/src_o.sel" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.sel</obj_property>
<obj_property name="ObjectShortName">src_o.sel</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/cmp_wb_source_if/addr_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">addr_i[3:0]</obj_property>
<obj_property name="ObjectShortName">addr_i[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/cmp_wb_source_if/data_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">data_i[31:0]</obj_property>
<obj_property name="ObjectShortName">data_i[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/cmp_wb_source_if/dvalid_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">dvalid_i</obj_property>
<obj_property name="ObjectShortName">dvalid_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/cmp_wb_source_if/sof_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sof_i</obj_property>
<obj_property name="ObjectShortName">sof_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/cmp_wb_source_if/eof_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">eof_i</obj_property>
<obj_property name="ObjectShortName">eof_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/cmp_wb_source_if/error_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">error_i</obj_property>
<obj_property name="ObjectShortName">error_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/cmp_wb_source_if/bytesel_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">bytesel_i</obj_property>
<obj_property name="ObjectShortName">bytesel_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/cmp_wb_source_if/dreq_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">dreq_o</obj_property>
<obj_property name="ObjectShortName">dreq_o</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/g_sim" type="other" db_ref_id="1">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">g_sim</obj_property>
<obj_property name="ObjectShortName">g_sim</obj_property>
<obj_property name="label">g_sim</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/cmp_wb_source_if/post_sof" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">post_sof</obj_property>
<obj_property name="ObjectShortName">post_sof</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/cmp_wb_source_if/post_bytesel" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">post_bytesel</obj_property>
<obj_property name="ObjectShortName">post_bytesel</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/cmp_wb_source_if/post_eof" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">post_eof</obj_property>
<obj_property name="ObjectShortName">post_eof</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/cmp_wb_source_if/post_dvalid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">post_dvalid</obj_property>
<obj_property name="ObjectShortName">post_dvalid</obj_property>
</wvobject>
<wvobject fp_name="/wb_fmc150_tb/cmp_dut/cmp_wb_fmc150/cmp_wb_source_if/fout" type="array" db_ref_id="1">
<obj_property name="ElementShortName">fout[39:0]</obj_property>
<obj_property name="ObjectShortName">fout[39:0]</obj_property>
</wvobject>
</wave_config>
......@@ -3,9 +3,14 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Custom Wishbone Modules
use work.custom_wishbone_pkg.all;
-- Wishbone Stream Interface
use work.wb_stream_pkg.all;
-- Register Bank
use work.fmc150_wbgen2_pkg.all;
entity wb_fmc150_tb is
end wb_fmc150_tb;
......@@ -16,6 +21,8 @@ architecture sim of wb_fmc150_tb is
constant c_100mhz_clk_period : time := 10.00 ns;
-- 200.00 MHz clock
constant c_200mhz_clk_period : time := 5.00 ns;
-- 61.44 MHz clock
constant c_61_44mhz_clk_period : time := 16.00 ns;
constant c_sim_time : time := 10000.00 ns;
signal g_end_simulation : boolean := false; -- Set to true to halt the simulation
......@@ -30,12 +37,15 @@ architecture sim of wb_fmc150_tb is
signal wb_slv_in : t_wishbone_slave_in := cc_dummy_slave_in;
signal wb_slv_out : t_wishbone_slave_out;
signal wbs_src_in : t_wbs_source_in := c_dummy_src_in;
signal wbs_src_in : t_wbs_source_in := cc_dummy_src_in;
signal wbs_src_out : t_wbs_source_out;
-- Dummy signals
constant cc_dummy_bit : std_logic := '0';
constant cc_dummy_slv : std_logic_vector := '0';
-- Simulation signals
signal s_adc_clk_ab_p : std_logic := '0';
signal s_adc_clk_ab_n : std_logic := '0';
-- Generate dummy (0) values
function f_zeros(size : integer)
......@@ -67,6 +77,19 @@ begin -- sim
end loop;
wait; -- simulation stops here
end process;
p_61_44mhz_clk_gen : process
begin
while g_end_simulation = false loop
wait for c_61_44mhz_clk_period/2;
s_adc_clk_ab_p <= not s_adc_clk_ab_p;
s_adc_clk_ab_n <= not s_adc_clk_ab_n;
wait for c_61_44mhz_clk_period/2;
s_adc_clk_ab_p <= not s_adc_clk_ab_p;
s_adc_clk_ab_n <= not s_adc_clk_ab_n;
end loop;
wait; -- simulation stops here
end process;
p_main_simulation : process
begin
......@@ -81,12 +104,13 @@ begin -- sim
end process;
cmp_dut : xwb_fmc150
--generic map
--(
generic map
(
--g_interface_mode => PIPELINED,
--g_address_granularity => WORD,
--g_packet_size => 32
--);
g_sim => true
)
port map
(
rst_n_i => rst_n_i,
......@@ -105,8 +129,8 @@ begin -- sim
-- External ports
-----------------------------
--Clock/Data connection to ADC on FMC150 (ADS62P49)
adc_clk_ab_p_i => '0',
adc_clk_ab_n_i => '0',
adc_clk_ab_p_i => s_adc_clk_ab_p,
adc_clk_ab_n_i => s_adc_clk_ab_n,
adc_cha_p_i => f_zeros(7),
adc_cha_n_i => f_zeros(7),
adc_chb_p_i => f_zeros(7),
......@@ -122,10 +146,10 @@ begin -- sim
txenable_o => open,
--Clock/Trigger connection to FMC150
clk_to_fpga_p_i => '0',
clk_to_fpga_n_i => '0',
ext_trigger_p_i => '0',
ext_trigger_n_i => '0',
--clk_to_fpga_p_i => cc_dummy_bit,
--clk_to_fpga_n_i => cc_dummy_bit,
--ext_trigger_p_i => cc_dummy_bit,
--ext_trigger_n_i => cc_dummy_bit,
-- Control signals from/to FMC150
--Serial Peripheral Interface (SPI)
......@@ -134,29 +158,29 @@ begin -- sim
-- ADC specific signals
adc_n_en_o => open, -- SPI chip select
adc_sdo_i => '0', -- SPI data out
adc_sdo_i => cc_dummy_bit, -- SPI data out
adc_reset_o => open, -- SPI reset
-- CDCE specific signals
cdce_n_en_o => open, -- SPI chip select
cdce_sdo_i =>'0', -- SPI data out
cdce_sdo_i => cc_dummy_bit, -- SPI data out
cdce_n_reset_o => open,
cdce_n_pd_o => open,
cdce_ref_en_o => open,
cdce_pll_status_i => '0',
cdce_pll_status_i => cc_dummy_bit,
-- DAC specific signals
dac_n_en_o => open, -- SPI chip select
dac_sdo_i => '0', -- SPI data out
dac_sdo_i => cc_dummy_bit, -- SPI data out
-- Monitoring specific signals
mon_n_en_o => open, -- SPI chip select
mon_sdo_i => '0', -- SPI data out
mon_sdo_i => cc_dummy_bit, -- SPI data out
mon_n_reset_o => open,
mon_n_int_i => '0',
mon_n_int_i => cc_dummy_bit,
--FMC Present status
prsnt_m2c_l_i => '0',
prsnt_m2c_l_i => cc_dummy_bit,
-- Wishbone Streaming Interface Source
wbs_source_i => wbs_src_in,
......
-- Default lib mapping for Simulator
std=$XILINX/vhdl/hdp/lin64/std
ieee=$XILINX/vhdl/hdp/lin64/ieee
ieee_proposed=$XILINX/vhdl/hdp/lin64/ieee_proposed
vl=$XILINX/vhdl/hdp/lin64/vl
synopsys=$XILINX/vhdl/hdp/lin64/synopsys
simprim=$XILINX/vhdl/hdp/lin64/simprim
unisim=$XILINX/vhdl/hdp/lin64/unisim
unimacro=$XILINX/vhdl/hdp/lin64/unimacro
aim=$XILINX/vhdl/hdp/lin64/aim
cpld=$XILINX/vhdl/hdp/lin64/cpld
pls=$XILINX/vhdl/hdp/lin64/pls
xilinxcorelib=$XILINX/vhdl/hdp/lin64/xilinxcorelib
aim_ver=$XILINX/verilog/hdp/lin64/aim_ver
cpld_ver=$XILINX/verilog/hdp/lin64/cpld_ver
simprims_ver=$XILINX/verilog/hdp/lin64/simprims_ver
unisims_ver=$XILINX/verilog/hdp/lin64/unisims_ver
uni9000_ver=$XILINX/verilog/hdp/lin64/uni9000_ver
unimacro_ver=$XILINX/verilog/hdp/lin64/unimacro_ver
xilinxcorelib_ver=$XILINX/verilog/hdp/lin64/xilinxcorelib_ver
secureip=$XILINX/verilog/hdp/lin64/xip/secureip
work=work
fifo_generator_v6_1=fifo_generator_v6_1
==========================================================
Folder containing all of the Beam Position Monitor software.
==========================================================
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