Commit 68ccd175 authored by Lucas Russo's avatar Lucas Russo

Merge branch 'devel'

Conflicts:
	hdl/modules/dbe_common/reset_synch/reset_synch.vhd
	hdl/top/afc_v3/vivado/dbe_bpm/dbe_bpm.xdc
	hdl/top/afc_v3/vivado/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux_ddr_2_3/pcie_core.xdc

Version v0.2
parents c4b452f8 5196a1d8
......@@ -6,6 +6,7 @@ modules = { "local": [
# "modules/rffe_top",
"modules/fabric",
"modules/fmc_adc_common",
"modules/utils",
"modules/pcie",
"ip_cores/general-cores",
"ip_cores/etherbone-core",
......
Subproject commit dbd00a073c94d2a484712e9ffa3be9299c08cd78
Subproject commit 61127ed11e010b182e62239906f627a6caa50dbc
if (action == "synthesis"):
files = ["bram_x64.ngc",
"eb_fifo_counted_resized.ngc",
"mbuf_128x72.ngc",
"prime_FIFO_plain.ngc",
"sfifo_15x128.ngc"]
else:
files = ["bram_x64.vhd",
"eb_fifo_counted_resized.vhd",
"mbuf_128x72.vhd",
"prime_FIFO_plain.vhd",
"sfifo_15x128.vhd"]
modules = {"local" : ["pcie_core/source",
"ddr_core_2_3/user_design"]}
#"ddr_core/user_design"]}
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##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Thu Feb 21 11:41:21 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:blk_mem_gen:7.3
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = false
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc7a200t
SET devicefamily = artix7
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ffg1156
SET removerpms = false
SET simulationfiles = Structural
SET speedgrade = -2
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.3
# END Select
# BEGIN Parameters
CSET additional_inputs_for_power_estimation=false
CSET algorithm=Minimum_Area
CSET assume_synchronous_clk=false
CSET axi_id_width=4
CSET axi_slave_type=Memory_Slave
CSET axi_type=AXI4_Full
CSET byte_size=8
CSET coe_file=no_coe_file_loaded
CSET collision_warnings=ALL
CSET component_name=bram_x64
CSET disable_collision_warnings=false
CSET disable_out_of_range_warnings=false
CSET ecc=false
CSET ecctype=No_ECC
CSET enable_32bit_address=false
CSET enable_a=Always_Enabled
CSET enable_b=Always_Enabled
CSET error_injection_type=Single_Bit_Error_Injection
CSET fill_remaining_memory_locations=false
CSET interface_type=Native
CSET load_init_file=false
CSET mem_file=no_Mem_file_loaded
CSET memory_type=True_Dual_Port_RAM
CSET operating_mode_a=WRITE_FIRST
CSET operating_mode_b=WRITE_FIRST
CSET output_reset_value_a=0
CSET output_reset_value_b=0
CSET pipeline_stages=0
CSET port_a_clock=100
CSET port_a_enable_rate=100
CSET port_a_write_rate=50
CSET port_b_clock=100
CSET port_b_enable_rate=100
CSET port_b_write_rate=50
CSET primitive=8kx2
CSET read_width_a=64
CSET read_width_b=64
CSET register_porta_input_of_softecc=false
CSET register_porta_output_of_memory_core=false
CSET register_porta_output_of_memory_primitives=false
CSET register_portb_output_of_memory_core=false
CSET register_portb_output_of_memory_primitives=true
CSET register_portb_output_of_softecc=false
CSET remaining_memory_locations=0
CSET reset_memory_latch_a=false
CSET reset_memory_latch_b=false
CSET reset_priority_a=CE
CSET reset_priority_b=CE
CSET reset_type=SYNC
CSET softecc=false
CSET use_axi_id=false
CSET use_bram_block=Stand_Alone
CSET use_byte_write_enable=true
CSET use_error_injection_pins=false
CSET use_regcea_pin=false
CSET use_regceb_pin=false
CSET use_rsta_pin=false
CSET use_rstb_pin=false
CSET write_depth_a=4096
CSET write_width_a=64
CSET write_width_b=64
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-11-19T16:22:25Z
# END Extra information
GENERATE
# CRC: a305062d
This diff is collapsed.
This source diff could not be displayed because it is too large. You can view the blob instead.
# Date: Fri Nov 22 11:22:48 2013
SET addpads = false
SET asysymbol = false
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc7a200t
SET devicefamily = artix7
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ffg1156
SET removerpms = false
SET simulationfiles = Structural
SET speedgrade = -1
SET verilogsim = true
SET vhdlsim = false
SET workingdirectory = ./tmp/
# CRC: ef472270
##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Fri Nov 22 11:22:21 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:mig_7series:1.9
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = false
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc7a200t
SET devicefamily = artix7
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ffg1156
SET removerpms = false
SET simulationfiles = Structural
SET speedgrade = -1
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT MIG_7_Series family Xilinx,_Inc. 1.9
# END Select
# BEGIN Parameters
CSET component_name=ddr_core
CSET xml_input_file=./ddr_core/mig.prj
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2013-10-13T18:46:09Z
# END Extra information
GENERATE
# CRC: ca08b313
This diff is collapsed.
NET "ddr3_dq[0]" LOC = "AD11" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[1]" LOC = "AE10" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[2]" LOC = "AF12" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[3]" LOC = "AG11" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[4]" LOC = "AE11" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[5]" LOC = "AH11" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[6]" LOC = "AG12" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[7]" LOC = "AH9" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[8]" LOC = "AD6" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[9]" LOC = "AG7" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[10]" LOC = "AF9" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[11]" LOC = "AH7" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[12]" LOC = "AE8" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[13]" LOC = "AF8" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[14]" LOC = "AE7" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[15]" LOC = "AF7" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[16]" LOC = "AF4" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[17]" LOC = "AF5" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[18]" LOC = "AD3" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[19]" LOC = "AG5" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[20]" LOC = "AD5" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[21]" LOC = "AG6" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[22]" LOC = "AD4" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[23]" LOC = "AE3" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[24]" LOC = "AG1" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[25]" LOC = "AG2" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[26]" LOC = "AE1" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[27]" LOC = "AF3" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[28]" LOC = "AE2" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[29]" LOC = "AH3" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[30]" LOC = "AD1" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[31]" LOC = "AF2" | IOSTANDARD = SSTL15 ;
NET "ddr3_dm[0]" LOC = "AD10" | IOSTANDARD = SSTL15 ;
NET "ddr3_dm[1]" LOC = "AH6" | IOSTANDARD = SSTL15 ;
NET "ddr3_dm[2]" LOC = "AG4" | IOSTANDARD = SSTL15 ;
NET "ddr3_dm[3]" LOC = "AH1" | IOSTANDARD = SSTL15 ;
NET "ddr3_dqs_p[0]" LOC = "AG10" | IOSTANDARD = DIFF_SSTL15 ;
NET "ddr3_dqs_n[0]" LOC = "AG9" | IOSTANDARD = DIFF_SSTL15 ;
NET "ddr3_dqs_p[1]" LOC = "AD9" | IOSTANDARD = DIFF_SSTL15 ;
NET "ddr3_dqs_n[1]" LOC = "AD8" | IOSTANDARD = DIFF_SSTL15 ;
NET "ddr3_dqs_p[2]" LOC = "AH4" | IOSTANDARD = DIFF_SSTL15 ;
NET "ddr3_dqs_n[2]" LOC = "AJ4" | IOSTANDARD = DIFF_SSTL15 ;
NET "ddr3_dqs_p[3]" LOC = "AH2" | IOSTANDARD = DIFF_SSTL15 ;
NET "ddr3_dqs_n[3]" LOC = "AJ1" | IOSTANDARD = DIFF_SSTL15 ;
NET "ddr3_addr[15]" LOC = "AP3" | IOSTANDARD = SSTL15 ;
NET "ddr3_addr[14]" LOC = "AK8" | IOSTANDARD = SSTL15 ;
NET "ddr3_addr[13]" LOC = "AM7" | IOSTANDARD = SSTL15 ;
NET "ddr3_addr[12]" LOC = "AP5" | IOSTANDARD = SSTL15 ;
NET "ddr3_addr[11]" LOC = "AJ8" | IOSTANDARD = SSTL15 ;
NET "ddr3_addr[10]" LOC = "AN2" | IOSTANDARD = SSTL15 ;
NET "ddr3_addr[9]" LOC = "AL4" | IOSTANDARD = SSTL15 ;
NET "ddr3_addr[8]" LOC = "AK6" | IOSTANDARD = SSTL15 ;
NET "ddr3_addr[7]" LOC = "AP6" | IOSTANDARD = SSTL15 ;
NET "ddr3_addr[6]" LOC = "AK5" | IOSTANDARD = SSTL15 ;
NET "ddr3_addr[5]" LOC = "AK3" | IOSTANDARD = SSTL15 ;
NET "ddr3_addr[4]" LOC = "AN4" | IOSTANDARD = SSTL15 ;
NET "ddr3_addr[3]" LOC = "AM6" | IOSTANDARD = SSTL15 ;
NET "ddr3_addr[2]" LOC = "AM4" | IOSTANDARD = SSTL15 ;
NET "ddr3_addr[1]" LOC = "AJ6" | IOSTANDARD = SSTL15 ;
NET "ddr3_addr[0]" LOC = "AP4" | IOSTANDARD = SSTL15 ;
NET "ddr3_ba[2]" LOC = "AK1" | IOSTANDARD = SSTL15 ;
NET "ddr3_ba[1]" LOC = "AK2" | IOSTANDARD = SSTL15 ;
NET "ddr3_ba[0]" LOC = "AM2" | IOSTANDARD = SSTL15 ;
NET "ddr3_ck_p[0]" LOC = "AL5" | IOSTANDARD = DIFF_SSTL15 ;
NET "ddr3_ck_n[0]" LOC = "AM5" | IOSTANDARD = DIFF_SSTL15 ;
NET "ddr3_ras_n" LOC = "AN1" | IOSTANDARD = SSTL15 ;
NET "ddr3_cas_n" LOC = "AL2" | IOSTANDARD = SSTL15 ;
NET "ddr3_we_n" LOC = "AM1" | IOSTANDARD = SSTL15 ;
NET "ddr3_reset_n" LOC = "AJ9" | IOSTANDARD = LVCMOS15 ;
NET "ddr3_cke[0]" LOC = "AJ5" | IOSTANDARD = SSTL15 ;
NET "ddr3_odt[0]" LOC = "AP1" | IOSTANDARD = SSTL15 ;
NET "ddr3_cs_n[0]" LOC = "AN3" | IOSTANDARD = SSTL15 ;
files = ["rtl/ddr_core.vhd",
"rtl/clocking/",
"rtl/controller/",
"rtl/ecc/",
"rtl/ip_top/",
"rtl/phy/",
"rtl/ui/"]
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:%version
// \ \ Application: MIG
// / / Filename: clk_ibuf.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:34:56 $
// \ \ / \ Date Created:Mon Aug 3 2009
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
// Clock generation/distribution and reset synchronization
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ns/1ps
module mig_7series_v1_9_clk_ibuf #
(
parameter SYSCLK_TYPE = "DIFFERENTIAL",
// input clock type
parameter DIFF_TERM_SYSCLK = "TRUE"
// Differential Termination
)
(
// Clock inputs
input sys_clk_p, // System clock diff input
input sys_clk_n,
input sys_clk_i,
output mmcm_clk
);
(* KEEP = "TRUE" *) wire sys_clk_ibufg /* synthesis syn_keep = 1 */;
generate
if (SYSCLK_TYPE == "DIFFERENTIAL") begin: diff_input_clk
//***********************************************************************
// Differential input clock input buffers
//***********************************************************************
IBUFGDS #
(
.DIFF_TERM (DIFF_TERM_SYSCLK),
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_sys_clk
(
.I (sys_clk_p),
.IB (sys_clk_n),
.O (sys_clk_ibufg)
);
end else if (SYSCLK_TYPE == "SINGLE_ENDED") begin: se_input_clk
//***********************************************************************
// SINGLE_ENDED input clock input buffers
//***********************************************************************
IBUFG #
(
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_sys_clk
(
.I (sys_clk_i),
.O (sys_clk_ibufg)
);
end else if (SYSCLK_TYPE == "NO_BUFFER") begin: internal_clk
//***********************************************************************
// System clock is driven from FPGA internal clock (clock from fabric)
//***********************************************************************
assign sys_clk_ibufg = sys_clk_i;
end
endgenerate
assign mmcm_clk = sys_clk_ibufg;
endmodule
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: iodelay_ctrl.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:34:56 $
// \ \ / \ Date Created: Wed Aug 16 2006
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
// This module instantiates the IDELAYCTRL primitive, which continously
// calibrates the IODELAY elements in the region to account for varying
// environmental conditions. A 200MHz or 300MHz reference clock (depending
// on the desired IODELAY tap resolution) must be supplied
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: iodelay_ctrl.v,v 1.1 2011/06/02 08:34:56 mishra Exp $
**$Date: 2011/06/02 08:34:56 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/clocking/iodelay_ctrl.v,v $
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v1_9_iodelay_ctrl #
(
parameter TCQ = 100,
// clk->out delay (sim only)
parameter IODELAY_GRP = "IODELAY_MIG",
// May be assigned unique name when
// multiple IP cores used in design
parameter REFCLK_TYPE = "DIFFERENTIAL",
// Reference clock type
// "DIFFERENTIAL","SINGLE_ENDED"
// NO_BUFFER, USE_SYSTEM_CLOCK
parameter SYSCLK_TYPE = "DIFFERENTIAL",
// input clock type
// DIFFERENTIAL, SINGLE_ENDED,
// NO_BUFFER
parameter SYS_RST_PORT = "FALSE",
// "TRUE" - if pin is selected for sys_rst
// and IBUF will be instantiated.
// "FALSE" - if pin is not selected for sys_rst
parameter RST_ACT_LOW = 1,
// Reset input polarity
// (0 = active high, 1 = active low)
parameter DIFF_TERM_REFCLK = "TRUE"
// Differential Termination
)
(
input clk_ref_p,
input clk_ref_n,
input clk_ref_i,
input sys_rst,
output clk_ref,
output sys_rst_o,
output iodelay_ctrl_rdy
);
// # of clock cycles to delay deassertion of reset. Needs to be a fairly
// high number not so much for metastability protection, but to give time
// for reset (i.e. stable clock cycles) to propagate through all state
// machines and to all control signals (i.e. not all control signals have
// resets, instead they rely on base state logic being reset, and the effect
// of that reset propagating through the logic). Need this because we may not
// be getting stable clock cycles while reset asserted (i.e. since reset
// depends on DCM lock status)
// COMMENTED, RC, 01/13/09 - causes pack error in MAP w/ larger #
localparam RST_SYNC_NUM = 15;
// localparam RST_SYNC_NUM = 25;
wire clk_ref_bufg;
wire clk_ref_ibufg;
wire rst_ref;
(* keep = "true", max_fanout = 10 *) reg [RST_SYNC_NUM-1:0] rst_ref_sync_r /* synthesis syn_maxfan = 10 */;
wire rst_tmp_idelay;
wire sys_rst_act_hi;
//***************************************************************************
// If the pin is selected for sys_rst in GUI, IBUF will be instantiated.
// If the pin is not selected in GUI, sys_rst signal is expected to be
// driven internally.
generate
if (SYS_RST_PORT == "TRUE")
IBUF u_sys_rst_ibuf
(
.I (sys_rst),
.O (sys_rst_o)
);
else
assign sys_rst_o = sys_rst;
endgenerate
// Possible inversion of system reset as appropriate
assign sys_rst_act_hi = RST_ACT_LOW ? ~sys_rst_o: sys_rst_o;
//***************************************************************************
// 1) Input buffer for IDELAYCTRL reference clock - handle either a
// differential or single-ended input. Global clock buffer is used to
// drive the rest of FPGA logic.
// 2) For NO_BUFFER option, Reference clock will be driven from internal
// clock i.e., clock is driven from fabric. Input buffers and Global
// clock buffers will not be instaitaed.
// 3) For USE_SYSTEM_CLOCK, input buffer output of system clock will be used
// as the input reference clock. Global clock buffer is used to drive
// the rest of FPGA logic.
//***************************************************************************
generate
if (REFCLK_TYPE == "DIFFERENTIAL") begin: diff_clk_ref
IBUFGDS #
(
.DIFF_TERM (DIFF_TERM_REFCLK),
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_clk_ref
(
.I (clk_ref_p),
.IB (clk_ref_n),
.O (clk_ref_ibufg)
);
BUFG u_bufg_clk_ref
(
.O (clk_ref_bufg),
.I (clk_ref_ibufg)
);
end else if (REFCLK_TYPE == "SINGLE_ENDED") begin : se_clk_ref
IBUFG #
(
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_clk_ref
(
.I (clk_ref_i),
.O (clk_ref_ibufg)
);
BUFG u_bufg_clk_ref
(
.O (clk_ref_bufg),
.I (clk_ref_ibufg)
);
end else if ((REFCLK_TYPE == "NO_BUFFER") ||
(REFCLK_TYPE == "USE_SYSTEM_CLOCK" && SYSCLK_TYPE == "NO_BUFFER")) begin : clk_ref_noibuf_nobuf
assign clk_ref_bufg = clk_ref_i;
end else if (REFCLK_TYPE == "USE_SYSTEM_CLOCK" && SYSCLK_TYPE != "NO_BUFFER") begin : clk_ref_noibuf
BUFG u_bufg_clk_ref
(
.O (clk_ref_bufg),
.I (clk_ref_i)
);
end
endgenerate
//***************************************************************************
// Global clock buffer for IDELAY reference clock
//***************************************************************************
assign clk_ref = clk_ref_bufg;
//*****************************************************************
// IDELAYCTRL reset
// This assumes an external clock signal driving the IDELAYCTRL
// blocks. Otherwise, if a PLL drives IDELAYCTRL, then the PLL
// lock signal will need to be incorporated in this.
//*****************************************************************
// Add PLL lock if PLL drives IDELAYCTRL in user design
assign rst_tmp_idelay = sys_rst_act_hi;
always @(posedge clk_ref_bufg or posedge rst_tmp_idelay)
if (rst_tmp_idelay)
rst_ref_sync_r <= #TCQ {RST_SYNC_NUM{1'b1}};
else
rst_ref_sync_r <= #TCQ rst_ref_sync_r << 1;
assign rst_ref = rst_ref_sync_r[RST_SYNC_NUM-1];
//*****************************************************************
(* IODELAY_GROUP = IODELAY_GRP *) IDELAYCTRL u_idelayctrl
(
.RDY (iodelay_ctrl_rdy),
.REFCLK (clk_ref_bufg),
.RST (rst_ref)
);
endmodule
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