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Beam Positoning Monitor - Gateware
Commit 0e56a4ec authored by Lucas Russo's avatar Lucas Russo
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hdl/: small sanitization changes

parent 6091e945
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README
View file @ 0e56a4ec
......@@ -69,3 +69,12 @@ Synthesis instructions:
hdlmake2 --make-ise --ise-proj
make
==========================================================
Know Issues:
wb_fmc150/sim/: This folder containts behavioral simulation models
for memories (ROMs). However, the xilinx initialization file (.mif)
paths are absolute to a specific machine! You either have to change
the path to match your machine or figure a way to specifies a relative
path (specifiying only the name of the mif file does not work as the
simulator is not called within this folder).
hdl/modules/custom_wishbone/wb_fmc150/build_wb.sh
View file @ 0e56a4ec
#!/bin/bash
wbgen2 -V wb_fmc150_port.vhd -H record -p xfmc150_regs_pkg.vhd -K ../../../sim/regs/xfmc150_regs_regs.vh -s struct -C xfmc150_regs_regs.h -D doc/xfmc150_regs_wb.html xfmc150.wb
wbgen2 -V wb_fmc150_port.vhd -H record -p xfmc150_regs_pkg.vhd -K ../../../sim/regs/xfmc150_regs.vh -s struct -C wb_fmc150.h -D doc/xfmc150_regs_wb.html xfmc150.wb
hdl/modules/custom_wishbone/wb_fmc150/doc/xfmc150_regs_wb.html
View file @ 0e56a4ec
......@@ -703,6 +703,23 @@ fmc150_flgs_out_spi_busy_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc150_flgs_out_pll_status_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc150_flgs_out_adc_clk_locked_i
......@@ -711,6 +728,23 @@ fmc150_flgs_out_adc_clk_locked_i
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc150_flgs_out_fmc_prst_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
</table>
<h3><a name="sect_3_0">3. Register description</a></h3>
......@@ -2782,16 +2816,16 @@ FLGS_OUT
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=1 class="td_field">
FMC_PRST
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
ADC_CLK_LOCKED
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
PLL_STATUS
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
SPI_BUSY
</td>
</tr>
......@@ -2802,9 +2836,17 @@ SPI_BUSY
</b>[<i>read-only</i>]: SPI Busy
<br>read 1: spi busy.<br> read 0: spi idle
<li><b>
PLL_STATUS
</b>[<i>read-only</i>]: CDCE72010 PLL Status
<br>read 1: PLL locked.<br> read 0: PLL not locked
<li><b>
ADC_CLK_LOCKED
</b>[<i>read-only</i>]: FPGA ADC clock locked
<br>read 1: FPGA ADC PLL locked.<br> read 0: FPGA ADC PLL not locked
<li><b>
FMC_PRST
</b>[<i>read-only</i>]: FMC present
<br>read 1: FMC present.<br> read 0: FMC not present
</ul>
......
hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_adc_if.vhd
View file @ 0e56a4ec
......@@ -15,7 +15,7 @@ generic (
);
port
(
clk_200MHz_i : in std_logic;
--clk_200MHz_i : in std_logic;
clk_100MHz_i : in std_logic;
rst_i : in std_logic;
cha_p_i : in std_logic_vector(6 downto 0);
......
hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_pkg.vhd
View file @ 0e56a4ec
......@@ -75,7 +75,7 @@ package fmc150_pkg is
);
port
(
clk_200MHz_i : in std_logic;
--clk_200MHz_i : in std_logic;
clk_100MHz_i : in std_logic;
rst_i : in std_logic;
cha_p_i : in std_logic_vector(6 downto 0);
......
hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_testbench.vhd
View file @ 0e56a4ec
......@@ -150,25 +150,29 @@ begin
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
--CLKFBOUT_MULT_F => 16.000,
CLKFBOUT_MULT_F => 8.000,
CLKFBOUT_MULT_F => 16.000,
--CLKFBOUT_MULT_F => 8.000,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
--CLKOUT0_DIVIDE_F => 16.000,
CLKOUT0_DIVIDE_F => 8.000,
CLKOUT0_DIVIDE_F => 16.000,
--CLKOUT0_DIVIDE_F => 8.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
--CLKOUT1_DIVIDE => 8,
CLKOUT1_DIVIDE => 4,
CLKOUT1_DIVIDE => 8,
--CLKOUT1_DIVIDE => 4,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_USE_FINE_PS => FALSE,
-- 61.44 MHZ input clock
--CLKIN1_PERIOD => 16.276,
CLKIN1_PERIOD => 16.276,
-- 122.88 MHZ input clock
CLKIN1_PERIOD => 8.138,
REF_JITTER1 => 0.010
--CLKIN1_PERIOD => 8.138,
REF_JITTER1 => 0.010,
-- Not used. Just to bypass Xilinx errors
-- Just input 61.44 MHz input clock
CLKIN2_PERIOD => 16.276,
REF_JITTER2 => 0.010
)
port map
(
......@@ -251,7 +255,7 @@ begin
)
port map
(
clk_200MHz_i => clk_200MHz,
--clk_200MHz_i => clk_200MHz,
clk_100MHz_i => clk_100MHz,
rst_i => mmcm_adc_locked,
str_p_i => adc_clk_ab_p,
......
hdl/modules/custom_wishbone/wb_fmc150/xfmc150_regs_regs.h → hdl/modules/custom_wishbone/wb_fmc150/wb_fmc150.h
View file @ 0e56a4ec
/*
Register definitions for slave core: FMC ADC/DAC interface registers
* File : xfmc150_regs_regs.h
* File : wb_fmc150.h
* Author : auto-generated by wbgen2 from xfmc150.wb
* Created : Tue Oct 9 14:47:14 2012
* Created : Thu Oct 11 10:21:39 2012
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE xfmc150.wb
......@@ -86,8 +86,14 @@
/* definitions for field: SPI Busy in reg: Flags out from Chips on FMC150 */
#define FMC150_FLGS_OUT_SPI_BUSY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: CDCE72010 PLL Status in reg: Flags out from Chips on FMC150 */
#define FMC150_FLGS_OUT_PLL_STATUS WBGEN2_GEN_MASK(1, 1)
/* definitions for field: FPGA ADC clock locked in reg: Flags out from Chips on FMC150 */
#define FMC150_FLGS_OUT_ADC_CLK_LOCKED WBGEN2_GEN_MASK(1, 1)
#define FMC150_FLGS_OUT_ADC_CLK_LOCKED WBGEN2_GEN_MASK(2, 1)
/* definitions for field: FMC present in reg: Flags out from Chips on FMC150 */
#define FMC150_FLGS_OUT_FMC_PRST WBGEN2_GEN_MASK(3, 1)
PACKED struct FMC150_WB {
/* [0x0]: REG Input Flags for Pulsing Registers */
......
hdl/modules/custom_wishbone/wb_fmc150/xfmc150.wb
View file @ 0e56a4ec
......@@ -21,7 +21,7 @@ peripheral {
--prefix = "start";
-- Pulse to start
type = MONOSTABLE;
clock = "clk_100Mhz_i";
--clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -38,7 +38,7 @@ peripheral {
write 0: read from SPI";
prefix = "spi_rw";
type = BIT;
clock = "clk_100Mhz_i";
--clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -49,7 +49,7 @@ peripheral {
write 0: internal clock for ADC";
prefix = "ext_clk";
type = BIT;
clock = "clk_100Mhz_i";
--clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -66,7 +66,7 @@ peripheral {
--prefix = "addr";
type = SLV;
size = 16;
clock = "clk_100Mhz_i";
--clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -83,7 +83,7 @@ peripheral {
--prefix = "data";
type = SLV;
size = 32;
clock = "clk_100Mhz_i";
--clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -100,7 +100,7 @@ peripheral {
write 0: no effect";
prefix = "cdce72010";
type = BIT;
clock = "clk_100Mhz_i";
--clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -111,7 +111,7 @@ peripheral {
write 0: no effect";
prefix = "ads62p49";
type = BIT;
clock = "clk_100Mhz_i";
--clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -122,7 +122,7 @@ peripheral {
write 0: no effect";
prefix = "dac3283";
type = BIT;
clock = "clk_100Mhz_i";
--clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -133,7 +133,7 @@ peripheral {
write 0: no effect";
prefix = "amc7823";
type = BIT;
clock = "clk_100Mhz_i";
--clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -151,7 +151,7 @@ peripheral {
type = SLV;
size = 5;
align = 8;
clock = "clk_100Mhz_i";
--clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -163,7 +163,7 @@ peripheral {
type = SLV;
size = 5;
align = 8;
clock = "clk_100Mhz_i";
--clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -175,7 +175,7 @@ peripheral {
type = SLV;
size = 5;
align = 8;
clock = "clk_100Mhz_i";
--clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -222,17 +222,17 @@ peripheral {
access_dev = WRITE_ONLY;
};
--field {
-- name = "CDCE72010 PLL Status";
-- description = "read 1: PLL locked.\
-- read 0: PLL not locked";
-- prefix = "pll_status";
-- type = BIT;
-- --clock = "clk_100Mhz";
-- clock = "clk_wb_i";
-- access_bus = READ_ONLY;
-- access_dev = WRITE_ONLY;
--};
field {
name = "CDCE72010 PLL Status";
description = "read 1: PLL locked.\
read 0: PLL not locked";
prefix = "pll_status";
type = BIT;
--clock = "clk_100Mhz";
--clock = "clk_wb_i";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "FPGA ADC clock locked";
......@@ -245,17 +245,17 @@ peripheral {
access_dev = WRITE_ONLY;
};
--field {
-- name = "FMC present";
-- description = "read 1: FMC present.\
-- read 0: FMC not present";
-- prefix = "fmc_prst";
-- type = BIT;
-- --clock = "clk_100Mhz";
-- clock = "clk_wb_i";
-- access_bus = READ_ONLY;
-- access_dev = WRITE_ONLY;
--};
field {
name = "FMC present";
description = "read 1: FMC present.\
read 0: FMC not present";
prefix = "fmc_prst";
type = BIT;
--clock = "clk_100Mhz";
--clock = "clk_wb_i";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
hdl/modules/custom_wishbone/wb_fmc150/xfmc150_regs_pkg.vhd
View file @ 0e56a4ec
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : xfmc150_regs_pkg.vhd
-- Author : auto-generated by wbgen2 from xfmc150.wb
-- Created : Tue Oct 9 14:47:14 2012
-- Created : Thu Oct 11 10:21:39 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE xfmc150.wb
......@@ -22,13 +22,17 @@ package fmc150_wbgen2_pkg is
type t_fmc150_in_registers is record
data_out_i : std_logic_vector(31 downto 0);
flgs_out_spi_busy_i : std_logic;
flgs_out_pll_status_i : std_logic;
flgs_out_adc_clk_locked_i : std_logic;
flgs_out_fmc_prst_i : std_logic;
end record;
constant c_fmc150_in_registers_init_value: t_fmc150_in_registers := (
data_out_i => (others => '0'),
flgs_out_spi_busy_i => '0',
flgs_out_adc_clk_locked_i => '0'
flgs_out_pll_status_i => '0',
flgs_out_adc_clk_locked_i => '0',
flgs_out_fmc_prst_i => '0'
);
-- Output registers (WB slave -> user design)
......@@ -93,7 +97,9 @@ variable tmp: t_fmc150_in_registers;
begin
tmp.data_out_i := f_x_to_zero(left.data_out_i) or f_x_to_zero(right.data_out_i);
tmp.flgs_out_spi_busy_i := f_x_to_zero(left.flgs_out_spi_busy_i) or f_x_to_zero(right.flgs_out_spi_busy_i);
tmp.flgs_out_pll_status_i := f_x_to_zero(left.flgs_out_pll_status_i) or f_x_to_zero(right.flgs_out_pll_status_i);
tmp.flgs_out_adc_clk_locked_i := f_x_to_zero(left.flgs_out_adc_clk_locked_i) or f_x_to_zero(right.flgs_out_adc_clk_locked_i);
tmp.flgs_out_fmc_prst_i := f_x_to_zero(left.flgs_out_fmc_prst_i) or f_x_to_zero(right.flgs_out_fmc_prst_i);
return tmp;
end function;
end package body;
hdl/modules/custom_wishbone/wb_fmc150/xwb_fmc150.vhd
View file @ 0e56a4ec
......@@ -16,13 +16,13 @@ generic
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_packet_size : natural := 32;
g_sim : boolean := false
g_sim : integer := 0
);
port
(
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
clk_100Mhz_i : in std_logic;
--clk_100Mhz_i : in std_logic;
clk_200Mhz_i : in std_logic;
-----------------------------
......@@ -35,12 +35,12 @@ port
-----------------------------
-- Simulation Only ports
-----------------------------
sim_adc_clk_i : in std_logic;
sim_adc_clk2x_i : in std_logic;
sim_adc_cha_data_i : in std_logic_vector(13 downto 0);
sim_adc_chb_data_i : in std_logic_vector(13 downto 0);
sim_adc_data_valid : in std_logic;
sim_adc_clk_i : in std_logic;
sim_adc_clk2x_i : in std_logic;
sim_adc_cha_data_i : in std_logic_vector(13 downto 0);
sim_adc_chb_data_i : in std_logic_vector(13 downto 0);
sim_adc_data_valid : in std_logic;
-----------------------------
-- External ports
......@@ -99,6 +99,10 @@ port
--FMC Present status
prsnt_m2c_l_i : in std_logic;
-- ADC output signals
adc_dout_o : out std_logic_vector(31 downto 0);
clk_adc_o : out std_logic;
-- Wishbone Streaming Interface Source
wbs_source_i : in t_wbs_source_in;
wbs_source_o : out t_wbs_source_out
......@@ -107,120 +111,6 @@ port
end xwb_fmc150;
architecture rtl of xwb_fmc150 is
component wb_fmc150
generic
(
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_packet_size : natural := 32;
g_sim : boolean := false
);
port
(
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
clk_100Mhz_i : in std_logic;
clk_200Mhz_i : in std_logic;
-----------------------------
-- Wishbone signals
-----------------------------
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := (others => '0');
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0) := (others => '0');
wb_we_i : in std_logic := '0';
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
-----------------------------
-- Simulation Only ports
-----------------------------
sim_adc_clk_i : in std_logic;
sim_adc_clk2x_i : in std_logic;
sim_adc_cha_data_i : in std_logic_vector(13 downto 0);
sim_adc_chb_data_i : in std_logic_vector(13 downto 0);
sim_adc_data_valid : in std_logic;
-----------------------------
-- External ports
-----------------------------
--Clock/Data connection to ADC on FMC150 (ADS62P49)
adc_clk_ab_p_i : in std_logic;
adc_clk_ab_n_i : in std_logic;
adc_cha_p_i : in std_logic_vector(6 downto 0);
adc_cha_n_i : in std_logic_vector(6 downto 0);
adc_chb_p_i : in std_logic_vector(6 downto 0);
adc_chb_n_i : in std_logic_vector(6 downto 0);
--Clock/Data connection to DAC on FMC150 (DAC3283)
dac_dclk_p_o : out std_logic;
dac_dclk_n_o : out std_logic;
dac_data_p_o : out std_logic_vector(7 downto 0);
dac_data_n_o : out std_logic_vector(7 downto 0);
dac_frame_p_o : out std_logic;
dac_frame_n_o : out std_logic;
txenable_o : out std_logic;
--Clock/Trigger connection to FMC150
--clk_to_fpga_p_i : in std_logic;
--clk_to_fpga_n_i : in std_logic;
--ext_trigger_p_i : in std_logic;
--ext_trigger_n_i : in std_logic;
-- Control signals from/to FMC150
--Serial Peripheral Interface (SPI)
spi_sclk_o : out std_logic; -- Shared SPI clock line
spi_sdata_o : out std_logic; -- Shared SPI data line
-- ADC specific signals
adc_n_en_o : out std_logic; -- SPI chip select
adc_sdo_i : in std_logic; -- SPI data out
adc_reset_o : out std_logic; -- SPI reset
-- CDCE specific signals
cdce_n_en_o : out std_logic; -- SPI chip select
cdce_sdo_i : in std_logic; -- SPI data out
cdce_n_reset_o : out std_logic;
cdce_n_pd_o : out std_logic;
cdce_ref_en_o : out std_logic;
cdce_pll_status_i : in std_logic;
-- DAC specific signals
dac_n_en_o : out std_logic; -- SPI chip select
dac_sdo_i : in std_logic; -- SPI data out
-- Monitoring specific signals
mon_n_en_o : out std_logic; -- SPI chip select
mon_sdo_i : in std_logic; -- SPI data out
mon_n_reset_o : out std_logic;
mon_n_int_i : in std_logic;
--FMC Present status
prsnt_m2c_l_i : in std_logic;
-- Wishbone Streaming Interface Source
wbs_adr_o : out std_logic_vector(c_wbs_address_width-1 downto 0);
wbs_dat_o : out std_logic_vector(c_wbs_data_width-1 downto 0);
wbs_cyc_o : out std_logic;
wbs_stb_o : out std_logic;
wbs_we_o : out std_logic;
wbs_sel_o : out std_logic_vector((c_wbs_data_width/8)-1 downto 0);
wbs_ack_i : in std_logic;
wbs_stall_i : in std_logic;
wbs_err_i : in std_logic;
wbs_rty_i : in std_logic
);
end component;
begin
cmp_wb_fmc150 : wb_fmc150
......@@ -235,7 +125,7 @@ begin
(
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
clk_100Mhz_i => clk_100Mhz_i,
--clk_100Mhz_i => clk_100Mhz_i,
clk_200Mhz_i => clk_200Mhz_i,
-----------------------------
......@@ -321,6 +211,10 @@ begin
--FMC Present status
prsnt_m2c_l_i => prsnt_m2c_l_i,
-- ADC output signals
adc_dout_o => adc_dout_o,
clk_adc_o => clk_adc_o,
-- Wishbone Streaming Interface Source
wbs_adr_o => wbs_source_o.adr,
wbs_dat_o => wbs_source_o.dat,
......
hdl/modules/custom_wishbone/wb_stream/wb_stream_pkg.vhd
View file @ 0e56a4ec
......@@ -84,48 +84,48 @@ package wb_stream_pkg is
constant cc_dummy_snk_in : t_wbs_sink_in :=
(cc_dummy_wbs_addr, cc_dummy_wbs_dat, '0', '0', '0', cc_dummy_wbs_sel);
-- Components
component xwb_stream_source
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone Fabric Interface I/O
src_i : in t_wbs_source_in;
src_o : out t_wbs_source_out;
-- Decoded & buffered logic
addr_i : in std_logic_vector(c_wbs_address_width-1 downto 0);
data_i : in std_logic_vector(c_wbs_data_width-1 downto 0);
dvalid_i : in std_logic;
sof_i : in std_logic;
eof_i : in std_logic;
error_i : in std_logic;
bytesel_i : in std_logic_vector((c_wbs_data_width/8)-1 downto 0);
dreq_o : out std_logic
);
end component;
component xwb_stream_sink
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone Fabric Interface I/O
snk_i : in t_wbs_sink_in;
snk_o : out t_wbs_sink_out;
-- Decoded & buffered fabric
addr_o : out std_logic_vector(c_wbs_address_width-1 downto 0);
data_o : out std_logic_vector(c_wbs_data_width-1 downto 0);
dvalid_o : out std_logic;
sof_o : out std_logic;
eof_o : out std_logic;
error_o : out std_logic;
bytesel_o : out std_logic_vector((c_wbs_data_width/8)-1 downto 0);
dreq_i : in std_logic
);
end component;
-- Components
component xwb_stream_source
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone Fabric Interface I/O
src_i : in t_wbs_source_in;
src_o : out t_wbs_source_out;
-- Decoded & buffered logic
addr_i : in std_logic_vector(c_wbs_address_width-1 downto 0);
data_i : in std_logic_vector(c_wbs_data_width-1 downto 0);
dvalid_i : in std_logic;
sof_i : in std_logic;
eof_i : in std_logic;
error_i : in std_logic;
bytesel_i : in std_logic_vector((c_wbs_data_width/8)-1 downto 0);
dreq_o : out std_logic
);
end component;
component xwb_stream_sink
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone Fabric Interface I/O
snk_i : in t_wbs_sink_in;
snk_o : out t_wbs_sink_out;
-- Decoded & buffered fabric
addr_o : out std_logic_vector(c_wbs_address_width-1 downto 0);
data_o : out std_logic_vector(c_wbs_data_width-1 downto 0);
dvalid_o : out std_logic;
sof_o : out std_logic;
eof_o : out std_logic;
error_o : out std_logic;
bytesel_o : out std_logic_vector((c_wbs_data_width/8)-1 downto 0);
dreq_i : in std_logic
);
end component;
end wb_stream_pkg;
......
hdl/platform/virtex6/chipscope/Manifest.py
View file @ 0e56a4ec
files = ["chipscope_icon.ngc", "chipscope_ila.ngc"]
\ No newline at end of file
files = ["icon_1_port/chipscope_icon_1_port.ngc", "icon_2_port/chipscope_icon_2_port.ngc", "chipscope_ila.ngc"]
hdl/platform/virtex6/chipscope/chipscope_ila.vhd 0 → 100644
View file @ 0e56a4ec
-------------------------------------------------------------------------------
-- Copyright (c) 2012 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 13.4
-- \ \ Application: XILINX CORE Generator
-- / / Filename : chipscope_ila.vhd
-- /___/ /\ Timestamp : Thu Oct 11 16:52:09 BRT 2012
-- \ \ / \
-- \___\/\___\
--
-- Design Name: VHDL Synthesis Wrapper
-------------------------------------------------------------------------------
-- This wrapper is used to integrate with Project Navigator and PlanAhead
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY chipscope_ila IS
port (
CONTROL: inout std_logic_vector(35 downto 0);
CLK: in std_logic;
TRIG0: in std_logic_vector(31 downto 0);
TRIG1: in std_logic_vector(31 downto 0);
TRIG2: in std_logic_vector(31 downto 0);
TRIG3: in std_logic_vector(31 downto 0));
END chipscope_ila;
ARCHITECTURE chipscope_ila_a OF chipscope_ila IS
BEGIN
END chipscope_ila_a;
hdl/sim/regs/xfmc150_regs.vh 0 → 100644
View file @ 0e56a4ec
`define ADDR_FMC150_FLGS_PULSE 5'h0
`define ADDR_FMC150_FLGS_IN 5'h4
`define FMC150_FLGS_IN_SPI_RW_OFFSET 0
`define FMC150_FLGS_IN_SPI_RW 32'h00000001
`define FMC150_FLGS_IN_EXT_CLK_OFFSET 1
`define FMC150_FLGS_IN_EXT_CLK 32'h00000002
`define ADDR_FMC150_ADDR 5'h8
`define ADDR_FMC150_DATA_IN 5'hc
`define ADDR_FMC150_CS 5'h10
`define FMC150_CS_CDCE72010_OFFSET 0
`define FMC150_CS_CDCE72010 32'h00000001
`define FMC150_CS_ADS62P49_OFFSET 1
`define FMC150_CS_ADS62P49 32'h00000002
`define FMC150_CS_DAC3283_OFFSET 2
`define FMC150_CS_DAC3283 32'h00000004
`define FMC150_CS_AMC7823_OFFSET 3
`define FMC150_CS_AMC7823 32'h00000008
`define ADDR_FMC150_ADC_DLY 5'h14
`define FMC150_ADC_DLY_STR_OFFSET 0
`define FMC150_ADC_DLY_STR 32'h0000001f
`define FMC150_ADC_DLY_CHA_OFFSET 8
`define FMC150_ADC_DLY_CHA 32'h00001f00
`define FMC150_ADC_DLY_CHB_OFFSET 16
`define FMC150_ADC_DLY_CHB 32'h001f0000
`define ADDR_FMC150_DATA_OUT 5'h18
`define ADDR_FMC150_FLGS_OUT 5'h1c
`define FMC150_FLGS_OUT_SPI_BUSY_OFFSET 0
`define FMC150_FLGS_OUT_SPI_BUSY 32'h00000001
`define FMC150_FLGS_OUT_PLL_STATUS_OFFSET 1
`define FMC150_FLGS_OUT_PLL_STATUS 32'h00000002
`define FMC150_FLGS_OUT_ADC_CLK_LOCKED_OFFSET 2
`define FMC150_FLGS_OUT_ADC_CLK_LOCKED 32'h00000004
`define FMC150_FLGS_OUT_FMC_PRST_OFFSET 3
`define FMC150_FLGS_OUT_FMC_PRST 32'h00000008
hdl/sim/regs/xfmc150_regs_regs.vh
View file @ 0e56a4ec
......@@ -26,5 +26,9 @@
`define ADDR_FMC150_FLGS_OUT 5'h1c
`define FMC150_FLGS_OUT_SPI_BUSY_OFFSET 0
`define FMC150_FLGS_OUT_SPI_BUSY 32'h00000001
`define FMC150_FLGS_OUT_ADC_CLK_LOCKED_OFFSET 1
`define FMC150_FLGS_OUT_ADC_CLK_LOCKED 32'h00000002
`define FMC150_FLGS_OUT_PLL_STATUS_OFFSET 1
`define FMC150_FLGS_OUT_PLL_STATUS 32'h00000002
`define FMC150_FLGS_OUT_ADC_CLK_LOCKED_OFFSET 2
`define FMC150_FLGS_OUT_ADC_CLK_LOCKED 32'h00000004
`define FMC150_FLGS_OUT_FMC_PRST_OFFSET 3
`define FMC150_FLGS_OUT_FMC_PRST 32'h00000008
hdl/syn/dbe_bpm_simple/Makefile 0 → 100644
View file @ 0e56a4ec
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
PROJECT := dbe_bpm_simple.xise
ISE_CRAP := *.b dbe_bpm_simple_top_summary.html *.tcl dbe_bpm_simple_top.bld dbe_bpm_simple_top.cmd_log *.drc dbe_bpm_simple_top.lso *.ncd dbe_bpm_simple_top.ngc dbe_bpm_simple_top.ngd dbe_bpm_simple_top.ngr dbe_bpm_simple_top.pad dbe_bpm_simple_top.par dbe_bpm_simple_top.pcf dbe_bpm_simple_top.prj dbe_bpm_simple_top.ptwx dbe_bpm_simple_top.stx dbe_bpm_simple_top.syr dbe_bpm_simple_top.twr dbe_bpm_simple_top.twx dbe_bpm_simple_top.gise dbe_bpm_simple_top.unroutes dbe_bpm_simple_top.ut dbe_bpm_simple_top.xpi dbe_bpm_simple_top.xst dbe_bpm_simple_top_bitgen.xwbt dbe_bpm_simple_top_envsettings.html dbe_bpm_simple_top_guide.ncd dbe_bpm_simple_top_map.map dbe_bpm_simple_top_map.mrp dbe_bpm_simple_top_map.ncd dbe_bpm_simple_top_map.ngm dbe_bpm_simple_top_map.xrpt dbe_bpm_simple_top_ngdbuild.xrpt dbe_bpm_simple_top_pad.csv dbe_bpm_simple_top_pad.txt dbe_bpm_simple_top_par.xrpt dbe_bpm_simple_top_summary.xml dbe_bpm_simple_top_usage.xml dbe_bpm_simple_top_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl
#target for performing local synthesis
local:
echo "project open $(PROJECT)" > run.tcl
echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
xtclsh run.tcl
#target for cleaing all intermediate stuff
clean:
rm -f $(ISE_CRAP)
rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
#target for cleaning final files
mrproper:
rm -f *.bit *.bin *.mcs
hdl/syn/dbe_bpm_simple/Manifest.py 0 → 100755
View file @ 0e56a4ec
target = "xilinx"
action = "synthesis"
syn_device = "xc6vlx240t"
syn_grade = "-1"
syn_package = "ff1156"
syn_top = "dbe_bpm_simple_top"
syn_project = "dbe_bpm_simple.xise"
modules = { "local" : [ "../../top/ml_605/dbe_bpm_simple" ] };
hdl/syn/dbe_bpm_simple/dbe_bpm_simple.gise 0 → 100644
View file @ 0e56a4ec
This diff is collapsed.
hdl/syn/dbe_bpm_simple/dbe_bpm_simple.xise 0 → 100644
View file @ 0e56a4ec
This diff is collapsed.
hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.bgn 0 → 100644
View file @ 0e56a4ec
This diff is collapsed.
hdl/syn/dbe_bpm_simple/make_output.txt 0 → 100644
View file @ 0e56a4ec
This diff is collapsed.
hdl/top/ml_605/dbe_bpm/Manifest.py deleted 100644 → 0
View file @ 6091e945
files = [ "dbe_demo_top.vhd", "sys_pll.vhd", "clk_gen.vhd", "dbe_demo_top.ucf" ];
modules = { "local" : ["../../.." ] };
hdl/top/ml_605/dbe_bpm/clk_gen.vhd deleted 100644 → 0
View file @ 6091e945
library UNISIM;
use UNISIM.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity clk_gen is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic
);
end clk_gen;
architecture syn of clk_gen is
-- Internal clock signal
signal s_sys_clk : std_logic;
begin
-- IBUFGDS: Differential Global Clock Input Buffer
-- Virtex-6
-- Xilinx HDL Language Template, version 13.4
cpm_ibufgds_clk_gen : IBUFGDS
generic map (
DIFF_TERM => FALSE, -- Differential Termination
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => s_sys_clk, -- Clock buffer output
I => sys_clk_p_i, -- Diff_p clock buffer input (connect directly to top-level port)
IB => sys_clk_n_i -- Diff_n clock buffer input (connect directly to top-level port)
);
-- BUFG: Global Clock Buffer
-- Virtex-6
-- Xilinx HDL Language Template, version 13.4
cmp_bufg_clk_gen : BUFG
port map (
O => sys_clk_o, -- 1-bit output: Clock buffer output
I => s_sys_clk -- 1-bit input: Clock buffer input
);
end syn;
hdl/top/ml_605/dbe_bpm/dbe_bpm_top.ucf deleted 100644 → 0
View file @ 6091e945
NET "buttons_i[0]" LOC = D22;
NET "buttons_i[1]" LOC = C22;
NET "buttons_i[2]" LOC = L21;
NET "buttons_i[3]" LOC = L20;
NET "buttons_i[4]" LOC = C18;
NET "buttons_i[5]" LOC = B18;
NET "buttons_i[6]" LOC = K22;
NET "buttons_i[7]" LOC = K21;
NET "leds_o[0]" LOC = AC22;
NET "leds_o[1]" LOC = AC24;
NET "leds_o[2]" LOC = AE22;
NET "leds_o[3]" LOC = AE23;
NET "leds_o[4]" LOC = AB23;
NET "leds_o[5]" LOC = AG23;
NET "leds_o[6]" LOC = AE24;
NET "leds_o[7]" LOC = AD24;
NET "buttons_i[7]" IOSTANDARD = LVCMOS25;
NET "buttons_i[6]" IOSTANDARD = LVCMOS25;
NET "buttons_i[5]" IOSTANDARD = LVCMOS25;
NET "buttons_i[4]" IOSTANDARD = LVCMOS25;
NET "buttons_i[3]" IOSTANDARD = LVCMOS25;
NET "buttons_i[2]" IOSTANDARD = LVCMOS25;
NET "buttons_i[1]" IOSTANDARD = LVCMOS25;
NET "buttons_i[0]" IOSTANDARD = LVCMOS25;
NET "leds_o[7]" IOSTANDARD = LVCMOS25;
NET "leds_o[7]" DRIVE = 12;
NET "leds_o[7]" SLEW = SLOW;
NET "leds_o[6]" IOSTANDARD = LVCMOS25;
NET "leds_o[6]" DRIVE = 12;
NET "leds_o[6]" SLEW = SLOW;
NET "leds_o[5]" IOSTANDARD = LVCMOS25;
NET "leds_o[5]" DRIVE = 12;
NET "leds_o[5]" SLEW = SLOW;
NET "leds_o[4]" IOSTANDARD = LVCMOS25;
NET "leds_o[4]" DRIVE = 12;
NET "leds_o[4]" SLEW = SLOW;
NET "leds_o[3]" IOSTANDARD = LVCMOS25;
NET "leds_o[3]" DRIVE = 12;
NET "leds_o[3]" SLEW = SLOW;
NET "leds_o[2]" IOSTANDARD = LVCMOS25;
NET "leds_o[2]" DRIVE = 12;
NET "leds_o[2]" SLEW = SLOW;
NET "leds_o[1]" IOSTANDARD = LVCMOS25;
NET "leds_o[1]" DRIVE = 12;
NET "leds_o[1]" SLEW = SLOW;
NET "leds_o[0]" IOSTANDARD = LVCMOS25;
NET "leds_o[0]" DRIVE = 12;
NET "leds_o[0]" SLEW = SLOW;
NET "sys_clk_p_i" IOSTANDARD = LVDS_25;
NET "sys_clk_n_i" IOSTANDARD = LVDS_25;
# PlanAhead Generated physical constraints
NET "sys_clk_n_i" LOC = H9;
NET "sys_clk_p_i" LOC = J9;
hdl/top/ml_605/dbe_bpm/dbe_bpm_top.vhd deleted 100755 → 0
View file @ 6091e945
This diff is collapsed.
hdl/top/ml_605/dbe_bpm/sw/Makefile deleted 100644 → 0
View file @ 6091e945
PLATFORM = lm32
OBJS_WRC = main.o gpio.o dma.o target/lm32/crt0.o
CROSS_COMPILE ?= /opt/gcc-lm32/bin/lm32-elf-
CFLAGS_PLATFORM = -mmultiply-enabled -mbarrel-shift-enabled -I.
LDFLAGS_PLATFORM = -mmultiply-enabled -mbarrel-shift-enabled -nostdlib -T target/lm32/ram.ld
CC=$(CROSS_COMPILE)gcc
OBJCOPY=$(CROSS_COMPILE)objcopy
OBJDUMP=$(CROSS_COMPILE)objdump
CFLAGS= $(CFLAGS_PLATFORM) -ffunction-sections -fdata-sections -Os -Iinclude $(PTPD_CFLAGS) -Iptp-noposix/PTPWRd
LDFLAGS= $(LDFLAGS_PLATFORM) -ffunction-sections -fdata-sections -Os -Iinclude
SIZE = $(CROSS_COMPILE)size
OBJS=$(OBJS_PLATFORM) $(OBJS_WRC) $(OBJS_PTPD) $(OBJS_PTPD_FREE)
OUTPUT=main
all: $(OBJS)
$(SIZE) -t $(OBJS)
${CC} -o $(OUTPUT).elf $(OBJS) $(LDFLAGS)
${OBJCOPY} -O binary $(OUTPUT).elf $(OUTPUT).bin
${OBJDUMP} -d $(OUTPUT).elf > $(OUTPUT)_disasm.S
./genraminit $(OUTPUT).bin 0 > $(OUTPUT).ram
clean:
rm -f $(OBJS) $(OUTPUT).elf $(OUTPUT).bin $(OUTPUT).ram $(OUTPUT)_disasm.S
%.o: %.c
${CC} $(CFLAGS) $(PTPD_CFLAGS) $(INCLUDE_DIR) $(LIB_DIR) -c $^ -o $@
hdl/top/ml_605/dbe_bpm/sw/board.h deleted 100644 → 0
View file @ 6091e945
#ifndef __BOARD_H
#define __BOARD_H
/* Automate the address peripheral discover */
#define BASE_DMA_ADDR 0x20000400
#define BASE_LEDS_ADDR 0x20000500
#define BASE_BUTTONS_ADDR 0x20000600
static inline int delay(int x)
{
while(x--) asm volatile("nop");
}
#endif
hdl/top/ml_605/dbe_bpm/sw/dma.c deleted 100644 → 0
View file @ 6091e945
#include "dma.h"
/* DMA user interface definition */
static inline int read_is_addr(dma_t dma)
{
return dma->RD_ADDR;
}
static inline void write_is_addr(dma_t dma, int addr)
{
dma->WR_ADDR = (uint32_t) addr;
}
static inline int read_strd(dma_t dma)
{
return dma->RD_STRD;
}
static inline void write_strd(dma_t dma, int strd)
{
dma->WR_STRD = (uint32_t) strd;
}
static inline int read_tr_count(dma_t dma)
{
return dma->TR_COUNT;
}
#endif
hdl/top/ml_605/dbe_bpm/sw/genraminit.c deleted 100644 → 0
View file @ 6091e945
#include <stdio.h>
#include <stdlib.h>
int main(int argc, char *argv[])
{
if(argc < 3) return -1;
FILE *f = fopen(argv[1],"rb");
if(!f) return -1;
unsigned char x[4];
int i=0;
int n = atoi(argv[2]);
while(!feof(f)){
fread(x,1,4,f);
printf("write %x %02X%02X%02X%02X\n", i++, x[0],x[1],x[2],x[3]);
}
for(;i<n;){
printf("write %x %02X%02X%02X%02X\n", i++, 0,0,0,0);
}
fclose(f);
return 0;
}
hdl/top/ml_605/dbe_bpm/sw/gpio.c deleted 100644 → 0
View file @ 6091e945
#include "gpio.h"
/* GPIO user interface definition */
static inline void gpio_out(gpio_t gpio, int pin, int val)
{
if(val)
gpio->SODR = (1<<pin);
else
gpio->CODR = (1<<pin);
}
static inline void gpio_dir(gpio_t gpio, int pin, int val)
{
if(val)
gpio->DDR |= (1<<pin);
else
gpio->DDR &= ~(1<<pin);
}
static inline int gpio_in(gpio_t gpio, int pin)
{
return gpio->PSR & (1<<pin) ? 1 : 0;
}
hdl/top/ml_605/dbe_bpm/sw/include/board.h deleted 100644 → 0
View file @ 6091e945
#ifndef __BOARD_H
#define __BOARD_H
/* Automate the address peripheral discover */
#define BASE_DMA_ADDR 0x20000400
#define BASE_LEDS_ADDR 0x20000500
#define BASE_BUTTONS_ADDR 0x20000600
static inline int delay(int x)
{
while(x--) asm volatile("nop");
}
#endif
hdl/top/ml_605/dbe_bpm/sw/include/dma.h deleted 100644 → 0
View file @ 6091e945
#ifndef __DMA_H
#define __DMA_H
#include "inttypes.h"
#include "board.h"
/*
This structure must conform to what it is specified in the
FPGA software-acessible registers. See general-cores/cores/wishbone/wb_dma.vhd
*/
struct DMA_WB
{
uint32_t RD_ADDR; /* Read issue address register */
uint32_t WR_ADDR; /* Write issue address register */
uint32_t RD_STRD; /* Read stride */
uint32_t WR_STRD; /* Write stride */
uint32_t TR_COUNT /* Transfer count */
};
typedef volatile struct DMA_WB * dma_t;
/* DMA user interface */
static inline int read_is_addr(dma_t dma);
static inline void write_is_addr(dma_t dma, int addr);
static inline int read_strd(dma_t dma);
static inline void write_strd(dma_t dma, int strd);
static inline int read_tr_count(dma_t dma);
#endif
hdl/top/ml_605/dbe_bpm/sw/include/gpio.h deleted 100644 → 0
View file @ 6091e945
#ifndef __GPIO_H
#define __GPIO_H
#include "inttypes.h"
#include "board.h"
/*
This structure must conform to what it is specified in the
FPGA software-acessible registers. See general-cores/cores/wishbone/wb_gpio_port.vhd
*/
struct GPIO_WB
{
uint32_t CODR; /* Clear output register */
uint32_t SODR; /* Set output register */
uint32_t DDR; /* Data direction register (1 means out) */
uint32_t PSR; /* Pin state register */
};
typedef volatile struct GPIO_WB * gpio_t;
//static volatile struct GPIO_WB *__gpio = (volatile struct GPIO_WB *) BASE_GPIO;
/* GPIO user interface */
static inline void gpio_out(gpio_t gpio, int pin, int val);
static inline void gpio_dir(gpio_t gpio, int pin, int val);
static inline int gpio_in(gpio_t gpio, int pin);
#endif
hdl/top/ml_605/dbe_bpm/sw/include/inttypes.h deleted 100644 → 0
View file @ 6091e945
#ifndef __WRAPPED_INTTYPES_H
#define __WRAPPED_INTTYPES_H
typedef unsigned char uint8_t;
typedef unsigned short uint16_t;
typedef unsigned int uint32_t;
typedef signed long long uint64_t;
typedef signed char int8_t;
typedef signed short int16_t;
typedef signed int int32_t;
typedef signed long long int64_t;
#endif
hdl/top/ml_605/dbe_bpm/sw/main.c deleted 100644 → 0
View file @ 6091e945
#include "gpio.h"
#include "dma.h"
/* Each loop iteration takes 4 cycles.
* It runs at 100MHz.
* Sleep 0.2 second.
*/
#define LED_DELAY (100000000/4/5)
//#define LED_DELAY 100000000
/* Placeholder for IRQ vector */
void _irq_entry(void){}
int main(void)
{
int i, j;
gpio_t leds = (volatile struct GPIO_WB *) BASE_LEDS_ADDR;
gpio_t buttons = (volatile struct GPIO_WB *) BASE_BUTTONS_ADDR;
dma_t buttons = (volatile struct DMA_WB *) BASE_DMA_ADDR;
while (1) {
/* Rotate the LEDs */
for (i = 0; i < 8; ++i) {
// Set led at position i
gpio_out(leds, i, 1);
/* Each loop iteration takes 4 cycles.
* It runs at 100MHz.
* Sleep 0.2 second.
*/
delay(LED_DELAY);
// Clear led at position i
gpio_out(leds, i, 0);
}
/* Rotate the LEDs */
}
return 0;
}
hdl/top/ml_605/dbe_bpm/sw/target/lm32/crt0.S deleted 100755 → 0
View file @ 6091e945
/****************************************************************************
**
** Name: crt0ram.S
**
** Description:
** Implements boot-code that calls LatticeDDInit (that calls main())
** Implements exception handlers (actually, redirectors)
**
** $Revision: $
**
** Disclaimer:
**
** This source code is intended as a design reference which
** illustrates how these types of functions can be implemented. It
** is the user's responsibility to verify their design for
** consistency and functionality through the use of formal
** verification methods. Lattice Semiconductor provides no warranty
** regarding the use or functionality of this code.
**
** --------------------------------------------------------------------
**
** Lattice Semiconductor Corporation
** 5555 NE Moore Court
** Hillsboro, OR 97214
** U.S.A
**
** TEL: 1-800-Lattice (USA and Canada)
** (503)268-8001 (other locations)
**
** web: http://www.latticesemi.com
** email: techsupport@latticesemi.com
**
** --------------------------------------------------------------------------
**
** Change History (Latest changes on top)
**
** Ver Date Description
** --------------------------------------------------------------------------
** 3.8 Apr-15-2011 Added __MICO_USER_<handler>_HANDLER__ preprocessor to
** allow customers to implement their own handlers for:
** DATA_ABORT, INST_ABORT
**
** 3.1 Jun-18-2008 Added __MICO_NO_INTERRUPTS__ preprocessor
** option to exclude invoking MicoISRHandler
** to reduce code-size in apps that don't use
** interrupts
**
** 3.0 Mar-25-2008 Added Header
**
**---------------------------------------------------------------------------
*****************************************************************************/
/*
* LatticeMico32 C startup code.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/* From include/sys/signal.h */
#define SIGINT 2 /* interrupt */
#define SIGTRAP 5 /* trace trap */
#define SIGFPE 8 /* arithmetic exception */
#define SIGSEGV 11 /* segmentation violation */
//#define MICO32_FULL_CONTEXT_SAVE_RESTORE
/* Exception handlers - Must be 32 bytes long. */
.section .boot, "ax", @progbits
.global _start
_start:
.global _reset_handler
.type _reset_handler, @function
_reset_handler:
xor r0, r0, r0
wcsr IE, r0
wcsr IM, r0
mvhi r1, hi(_reset_handler)
ori r1, r1, lo(_reset_handler)
wcsr EBA, r1
calli _crt0
nop
.size _reset_handler, .-_reset_handler
.extern _irq_entry
.org 0xc0
.global _interrupt_handler
.type _interrupt_handler, @function
_interrupt_handler:
sw (sp+0), ra
calli _save_all
mvi r1, SIGINT
#ifndef __MICO_NO_INTERRUPTS__
calli _irq_entry
#else
wcsr IE, r0
#endif
bi _restore_all_and_return
nop
nop
nop
.org 0x100
.global _crt0
.type _crt0, @function
_crt0:
/* Clear r0 */
xor r0, r0, r0
/* Setup stack and global pointer */
mvhi sp, hi(_fstack)
ori sp, sp, lo(_fstack)
mvhi gp, hi(_gp)
ori gp, gp, lo(_gp)
mvhi r1, hi(_fbss)
ori r1, r1, lo(_fbss)
mvi r2, 0
mvhi r3, hi(_ebss)
ori r3, r3, lo(_ebss)
sub r3, r3, r1
calli memset
mvi r1, 0
mvi r2, 0
mvi r3, 0
calli main
loopf:
bi loopf
.global _save_all
.type _save_all, @function
_save_all:
#ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE
addi sp, sp, -128
#else
addi sp, sp, -60
#endif
sw (sp+4), r1
sw (sp+8), r2
sw (sp+12), r3
sw (sp+16), r4
sw (sp+20), r5
sw (sp+24), r6
sw (sp+28), r7
sw (sp+32), r8
sw (sp+36), r9
sw (sp+40), r10
#ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE
sw (sp+44), r11
sw (sp+48), r12
sw (sp+52), r13
sw (sp+56), r14
sw (sp+60), r15
sw (sp+64), r16
sw (sp+68), r17
sw (sp+72), r18
sw (sp+76), r19
sw (sp+80), r20
sw (sp+84), r21
sw (sp+88), r22
sw (sp+92), r23
sw (sp+96), r24
sw (sp+100), r25
sw (sp+104), r26
sw (sp+108), r27
sw (sp+120), ea
sw (sp+124), ba
/* ra and sp need special handling, as they have been modified */
lw r1, (sp+128)
sw (sp+116), r1
mv r1, sp
addi r1, r1, 128
sw (sp+112), r1
#else
sw (sp+52), ea
sw (sp+56), ba
/* ra and sp need special handling, as they have been modified */
lw r1, (sp+60)
sw (sp+48), r1
mv r1, sp
addi r1, r1, 60
sw (sp+44), r1
#endif
// xor r1, r1, r1
// wcsr ie, r1
ret
.size _save_all, .-_save_all
.global _restore_all_and_return
.type _restore_all_and_return, @function
/* Restore all registers and return from exception */
_restore_all_and_return:
// addi r1, r0, 2
// wcsr ie, r1
lw r1, (sp+4)
lw r2, (sp+8)
lw r3, (sp+12)
lw r4, (sp+16)
lw r5, (sp+20)
lw r6, (sp+24)
lw r7, (sp+28)
lw r8, (sp+32)
lw r9, (sp+36)
lw r10, (sp+40)
#ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE
lw r11, (sp+44)
lw r12, (sp+48)
lw r13, (sp+52)
lw r14, (sp+56)
lw r15, (sp+60)
lw r16, (sp+64)
lw r17, (sp+68)
lw r18, (sp+72)
lw r19, (sp+76)
lw r20, (sp+80)
lw r21, (sp+84)
lw r22, (sp+88)
lw r23, (sp+92)
lw r24, (sp+96)
lw r25, (sp+100)
lw r26, (sp+104)
lw r27, (sp+108)
lw ra, (sp+116)
lw ea, (sp+120)
lw ba, (sp+124)
/* Stack pointer must be restored last, in case it has been updated */
lw sp, (sp+112)
#else
lw ra, (sp+48)
lw ea, (sp+52)
lw ba, (sp+56)
/* Stack pointer must be restored last, in case it has been updated */
lw sp, (sp+44)
#endif
nop
eret
.size _restore_all_and_return, .-_restore_all_and_return
hdl/top/ml_605/dbe_bpm/sw/target/lm32/irq.c deleted 100644 → 0
View file @ 6091e945
#include "irq.h"
void disable_irq()
{
unsigned int ie, im;
unsigned int Mask = ~1;
/* disable peripheral interrupts in case they were enabled */
asm volatile ("rcsr %0,ie":"=r"(ie));
ie &= (~0x1);
asm volatile ("wcsr ie, %0"::"r"(ie));
/* disable mask-bit in im */
asm volatile ("rcsr %0, im":"=r"(im));
im &= Mask;
asm volatile ("wcsr im, %0"::"r"(im));
}
void enable_irq()
{
unsigned int ie, im;
unsigned int Mask = 1;
/* disable peripheral interrupts in-case they were enabled*/
asm volatile ("rcsr %0,ie":"=r"(ie));
ie &= (~0x1);
asm volatile ("wcsr ie, %0"::"r"(ie));
/* enable mask-bit in im */
asm volatile ("rcsr %0, im":"=r"(im));
im |= Mask;
asm volatile ("wcsr im, %0"::"r"(im));
ie |= 0x1;
asm volatile ("wcsr ie, %0"::"r"(ie));
}
hdl/top/ml_605/dbe_bpm/sw/target/lm32/ram.ld deleted 100644 → 0
View file @ 6091e945
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hdl/top/ml_605/dbe_bpm/sys_pll.vhd deleted 100644 → 0
View file @ 6091e945
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