# wb_fmc_250m_4ch_csr

### FMC ADC 250MS/s core registers

Wishbone slave for FMC ADC 250MS/s core

### Contents:

1. Memory map summary
2. HDL symbol
3. Register description
3.1. Global ADC Status register
3.2. Global ADC Control register
3.3. Channel 0 status register
3.4. Channel 0 fine delay register
3.5. Channel 0 coarse delay register
3.6. Channel 1 status register
3.7. Channel 1 fine delay register
3.8. Channel 1 coarse delay register
3.9. Channel 2 status register
3.10. Channel 2 fine delay register
3.11. Channel 2 coarse delay register
3.12. Channel 3 status register
3.13. Channel 3 fine delay register
3.14. Channel 3 coarse delay register
3.15. FMC temperature monitor register

### 1. Memory map summary

H/W Address | Type | Name | VHDL/Verilog prefix | C prefix
--- | --- | --- | --- | ---
0x0 | REG | Global ADC Status register | wb_fmc_250m_4ch_csr_adc_sta | ADC_STA
0x1 | REG | Global ADC Control register | wb_fmc_250m_4ch_csr_adc_ctl | ADC_CTL
0x2 | REG | Channel 0 status register | wb_fmc_250m_4ch_csr_ch0_sta | CH0_STA
0x3 | REG | Channel 0 fine delay register | wb_fmc_250m_4ch_csr_ch0_fn_dly | CH0_FN_DLY
0x4 | REG | Channel 0 coarse delay register | wb_fmc_250m_4ch_csr_ch0_cs_dly | CH0_CS_DLY
0x5 | REG | Channel 1 status register | wb_fmc_250m_4ch_csr_ch1_sta | CH1_STA
0x6 | REG | Channel 1 fine delay register | wb_fmc_250m_4ch_csr_ch1_fn_dly | CH1_FN_DLY
0x7 | REG | Channel 1 coarse delay register | wb_fmc_250m_4ch_csr_ch1_cs_dly | CH1_CS_DLY
0x8 | REG | Channel 2 status register | wb_fmc_250m_4ch_csr_ch2_sta | CH2_STA
0x9 | REG | Channel 2 fine delay register | wb_fmc_250m_4ch_csr_ch2_fn_dly | CH2_FN_DLY
0xa | REG | Channel 2 coarse delay register | wb_fmc_250m_4ch_csr_ch2_cs_dly | CH2_CS_DLY
0xb | REG | Channel 3 status register | wb_fmc_250m_4ch_csr_ch3_sta | CH3_STA
0xc | REG | Channel 3 fine delay register | wb_fmc_250m_4ch_csr_ch3_fn_dly | CH3_FN_DLY
0xd | REG | Channel 3 coarse delay register | wb_fmc_250m_4ch_csr_ch3_cs_dly | CH3_CS_DLY
0xe | REG | FMC temperature monitor register | wb_fmc_250m_4ch_csr_temp | TEMP

### 2. HDL symbol

→ | rst_n_i |  | Global ADC Status register: |
→ | clk_sys_i |  | wb_fmc_250m_4ch_csr_adc_sta_clk_chains_i[3:0] | ⇐
⇒ | wb_adr_i[3:0] |  | wb_fmc_250m_4ch_csr_adc_sta_reserved_clk_chains_i[3:0] | ⇐
⇒ | wb_dat_i[31:0] |  | wb_fmc_250m_4ch_csr_adc_sta_data_chains_i[3:0] | ⇐
⇐ | wb_dat_o[31:0] |  | wb_fmc_250m_4ch_csr_adc_sta_reserved_data_chains_i[3:0] | ⇐
→ | wb_cyc_i |  | wb_fmc_250m_4ch_csr_adc_sta_adc_pkt_size_i[15:0] | ⇐
⇒ | wb_sel_i[3:0] |  |  |
→ | wb_stb_i |  | Global ADC Control register: |
→ | wb_we_i |  | wb_fmc_250m_4ch_csr_adc_ctl_update_clk_dly_o | →
← | wb_ack_o |  | wb_fmc_250m_4ch_csr_adc_ctl_update_data_dly_o | →
← | wb_stall_o |  | wb_fmc_250m_4ch_csr_adc_ctl_rst_adcs_o | →
|  |  | wb_fmc_250m_4ch_csr_adc_ctl_rst_div_adcs_o | →
|  |  | wb_fmc_250m_4ch_csr_adc_ctl_sleep_adcs_o | →
|  |  | wb_fmc_250m_4ch_csr_adc_ctl_reserved_i[26:0] | ⇐
|  |  | Channel 0 status register: |
|  |  | wb_fmc_250m_4ch_csr_ch0_sta_val_i[15:0] | ⇐
|  |  | wb_fmc_250m_4ch_csr_ch0_sta_reserved_i[15:0] | ⇐
|  |  | Channel 0 fine delay register: |
|  |  | wb_fmc_250m_4ch_csr_ch0_fn_dly_clk_chain_dly_o[4:0] | ⇒
|  |  | wb_fmc_250m_4ch_csr_ch0_fn_dly_clk_chain_dly_i[4:0] | ⇐
|  |  | wb_fmc_250m_4ch_csr_ch0_fn_dly_clk_chain_dly_load_o | →
|  |  | wb_fmc_250m_4ch_csr_ch0_fn_dly_reserved_clk_chain_dly_i[2:0] | ⇐
|  |  | wb_fmc_250m_4ch_csr_ch0_fn_dly_data_chain_dly_o[4:0] | ⇒
|  |  | wb_fmc_250m_4ch_csr_ch0_fn_dly_data_chain_dly_i[4:0] | ⇐
|  |  | wb_fmc_250m_4ch_csr_ch0_fn_dly_data_chain_dly_load_o | →
|  |  | wb_fmc_250m_4ch_csr_ch0_fn_dly_reserved_data_chain_dly_i[2:0] | ⇐
|  |  | wb_fmc_250m_4ch_csr_ch0_fn_dly_inc_clk_chain_dly_o | →
|  |  | wb_fmc_250m_4ch_csr_ch0_fn_dly_dec_clk_chain_dly_o | →
|  |  | wb_fmc_250m_4ch_csr_ch0_fn_dly_reserved_clk_incdec_dly_o[5:0] | ⇒
|  |  | wb_fmc_250m_4ch_csr_ch0_fn_dly_inc_data_chain_dly_o | →
|  |  | wb_fmc_250m_4ch_csr_ch0_fn_dly_dec_data_chain_dly_o | →
|  |  | wb_fmc_250m_4ch_csr_ch0_fn_dly_reserved_data_incdec_dly_o[5:0] | ⇒
|  |  | Channel 0 coarse delay register: |
|  |  | wb_fmc_250m_4ch_csr_ch0_cs_dly_fe_dly_o[1:0] | ⇒
|  |  | wb_fmc_250m_4ch_csr_ch0_cs_dly_reserved_fe_dly_o[5:0] | ⇒
|  |  | wb_fmc_250m_4ch_csr_ch0_cs_dly_rg_dly_o[1:0] | ⇒
|  |  | wb_fmc_250m_4ch_csr_ch0_cs_dly_reserved_rg_dly_o[21:0] | ⇒
|  |  | Channel 1 status register: |
|  |  | wb_fmc_250m_4ch_csr_ch1_sta_val_i[15:0] | ⇐
|  |  | wb_fmc_250m_4ch_csr_ch1_sta_reserved_i[15:0] | ⇐
|  |  | Channel 1 fine delay register: |
|  |  | wb_fmc_250m_4ch_csr_ch1_fn_dly_clk_chain_dly_o[4:0] | ⇒
|  |  | wb_fmc_250m_4ch_csr_ch1_fn_dly_clk_chain_dly_i[4:0] | ⇐
|  |  | wb_fmc_250m_4ch_csr_ch1_fn_dly_clk_chain_dly_load_o | →
|  |  | wb_fmc_250m_4ch_csr_ch1_fn_dly_reserved_clk_chain_dly_i[2:0] | ⇐
|  |  | wb_fmc_250m_4ch_csr_ch1_fn_dly_data_chain_dly_o[4:0] | ⇒
|  |  | wb_fmc_250m_4ch_csr_ch1_fn_dly_data_chain_dly_i[4:0] | ⇐
|  |  | wb_fmc_250m_4ch_csr_ch1_fn_dly_data_chain_dly_load_o | →
|  |  | wb_fmc_250m_4ch_csr_ch1_fn_dly_reserved_data_chain_dly_i[2:0] | ⇐
|  |  | wb_fmc_250m_4ch_csr_ch1_fn_dly_inc_clk_chain_dly_o | →
|  |  | wb_fmc_250m_4ch_csr_ch1_fn_dly_dec_clk_chain_dly_o | →
|  |  | wb_fmc_250m_4ch_csr_ch1_fn_dly_reserved_clk_incdec_dly_o[5:0] | ⇒
|  |  | wb_fmc_250m_4ch_csr_ch1_fn_dly_inc_data_chain_dly_o | →
|  |  | wb_fmc_250m_4ch_csr_ch1_fn_dly_dec_data_chain_dly_o | →
|  |  | wb_fmc_250m_4ch_csr_ch1_fn_dly_reserved_data_incdec_dly_o[5:0] | ⇒
|  |  | Channel 1 coarse delay register: |
|  |  | wb_fmc_250m_4ch_csr_ch1_cs_dly_fe_dly_o[1:0] | ⇒
|  |  | wb_fmc_250m_4ch_csr_ch1_cs_dly_reserved_fe_dly_o[5:0] | ⇒
|  |  | wb_fmc_250m_4ch_csr_ch1_cs_dly_rg_dly_o[1:0] | ⇒
|  |  | wb_fmc_250m_4ch_csr_ch1_cs_dly_reserved_rg_dly_o[21:0] | ⇒
|  |  | Channel 2 status register: |
|  |  | wb_fmc_250m_4ch_csr_ch2_sta_val_i[15:0] | ⇐
|  |  | wb_fmc_250m_4ch_csr_ch2_sta_reserved_i[15:0] | ⇐
|  |  | Channel 2 fine delay register: |
|  |  | wb_fmc_250m_4ch_csr_ch2_fn_dly_clk_chain_dly_o[4:0] | ⇒
|  |  | wb_fmc_250m_4ch_csr_ch2_fn_dly_clk_chain_dly_i[4:0] | ⇐
|  |  | wb_fmc_250m_4ch_csr_ch2_fn_dly_clk_chain_dly_load_o | →
|  |  | wb_fmc_250m_4ch_csr_ch2_fn_dly_reserved_clk_chain_dly_i[2:0] | ⇐
|  |  | wb_fmc_250m_4ch_csr_ch2_fn_dly_data_chain_dly_o[4:0] | ⇒
|  |  | wb_fmc_250m_4ch_csr_ch2_fn_dly_data_chain_dly_i[4:0] | ⇐
|  |  | wb_fmc_250m_4ch_csr_ch2_fn_dly_data_chain_dly_load_o | →
|  |  | wb_fmc_250m_4ch_csr_ch2_fn_dly_reserved_data_chain_dly_i[2:0] | ⇐
|  |  | wb_fmc_250m_4ch_csr_ch2_fn_dly_inc_clk_chain_dly_o | →
|  |  | wb_fmc_250m_4ch_csr_ch2_fn_dly_dec_clk_chain_dly_o | →
|  |  | wb_fmc_250m_4ch_csr_ch2_fn_dly_reserved_clk_incdec_dly_o[5:0] | ⇒
|  |  | wb_fmc_250m_4ch_csr_ch2_fn_dly_inc_data_chain_dly_o | →
|  |  | wb_fmc_250m_4ch_csr_ch2_fn_dly_dec_data_chain_dly_o | →
|  |  | wb_fmc_250m_4ch_csr_ch2_fn_dly_reserved_data_incdec_dly_o[5:0] | ⇒
|  |  | Channel 2 coarse delay register: |
|  |  | wb_fmc_250m_4ch_csr_ch2_cs_dly_fe_dly_o[1:0] | ⇒
|  |  | wb_fmc_250m_4ch_csr_ch2_cs_dly_reserved_fe_dly_o[5:0] | ⇒
|  |  | wb_fmc_250m_4ch_csr_ch2_cs_dly_rg_dly_o[1:0] | ⇒
|  |  | wb_fmc_250m_4ch_csr_ch2_cs_dly_reserved_rg_dly_o[21:0] | ⇒
|  |  | Channel 3 status register: |
|  |  | wb_fmc_250m_4ch_csr_ch3_sta_val_i[15:0] | ⇐
|  |  | wb_fmc_250m_4ch_csr_ch3_sta_reserved_i[15:0] | ⇐
|  |  | Channel 3 fine delay register: |
|  |  | wb_fmc_250m_4ch_csr_ch3_fn_dly_clk_chain_dly_o[4:0] | ⇒
|  |  | wb_fmc_250m_4ch_csr_ch3_fn_dly_clk_chain_dly_i[4:0] | ⇐
|  |  | wb_fmc_250m_4ch_csr_ch3_fn_dly_clk_chain_dly_load_o | →
|  |  | wb_fmc_250m_4ch_csr_ch3_fn_dly_reserved_clk_chain_dly_i[2:0] | ⇐
|  |  | wb_fmc_250m_4ch_csr_ch3_fn_dly_data_chain_dly_o[4:0] | ⇒
|  |  | wb_fmc_250m_4ch_csr_ch3_fn_dly_data_chain_dly_i[4:0] | ⇐
|  |  | wb_fmc_250m_4ch_csr_ch3_fn_dly_data_chain_dly_load_o | →
|  |  | wb_fmc_250m_4ch_csr_ch3_fn_dly_reserved_data_chain_dly_i[2:0] | ⇐
|  |  | wb_fmc_250m_4ch_csr_ch3_fn_dly_inc_clk_chain_dly_o | →
|  |  | wb_fmc_250m_4ch_csr_ch3_fn_dly_dec_clk_chain_dly_o | →
|  |  | wb_fmc_250m_4ch_csr_ch3_fn_dly_reserved_clk_incdec_dly_o[5:0] | ⇒
|  |  | wb_fmc_250m_4ch_csr_ch3_fn_dly_inc_data_chain_dly_o | →
|  |  | wb_fmc_250m_4ch_csr_ch3_fn_dly_dec_data_chain_dly_o | →
|  |  | wb_fmc_250m_4ch_csr_ch3_fn_dly_reserved_data_incdec_dly_o[5:0] | ⇒
|  |  | Channel 3 coarse delay register: |
|  |  | wb_fmc_250m_4ch_csr_ch3_cs_dly_fe_dly_o[1:0] | ⇒
|  |  | wb_fmc_250m_4ch_csr_ch3_cs_dly_reserved_fe_dly_o[5:0] | ⇒
|  |  | wb_fmc_250m_4ch_csr_ch3_cs_dly_rg_dly_o[1:0] | ⇒
|  |  | wb_fmc_250m_4ch_csr_ch3_cs_dly_reserved_rg_dly_o[21:0] | ⇒
|  |  | FMC temperature monitor register: |
|  |  | wb_fmc_250m_4ch_csr_temp_mon_dev_i | ←

### 3. Register description

### 3.1. Global ADC Status register

HW prefix: | wb_fmc_250m_4ch_csr_adc_sta
HW address: | 0x0
C prefix: | ADC_STA
C offset: | 0x0

Global ADC status register.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
ADC_PKT_SIZE[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
ADC_PKT_SIZE[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RESERVED_DATA_CHAINS[3:0] | DATA_CHAINS[3:0] |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RESERVED_CLK_CHAINS[3:0] | CLK_CHAINS[3:0] |  |  |  |  |  |

- CLK_CHAINS [read-only]: FMC ADC clock chains
  FMC ADC used clock chains.
  read 1: clock chain is used
  read 0: clock chain is not used
- RESERVED_CLK_CHAINS [read-only]: Reserved
  Ignore on write, read as 0's
- DATA_CHAINS [read-only]: FMC ADC Data chains
  FMC ADC used clock chains.
  read 1: data chain is used
  read 0: data chain is not used
- RESERVED_DATA_CHAINS [read-only]: Reserved
  Ignore on write, read as 0's
- ADC_PKT_SIZE [read-only]: FMC ADC packet size
  Size of the packet sent to the Wishbone Streaming Interface.
  This will appear as cycles of clock cycles on
  the wishbone interface

### 3.2. Global ADC Control register

HW prefix: | wb_fmc_250m_4ch_csr_adc_ctl
HW address: | 0x1
C prefix: | ADC_CTL
C offset: | 0x4

Global ADC control register.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED[26:19] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED[18:11] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RESERVED[10:3] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RESERVED[2:0] | SLEEP_ADCS | RST_DIV_ADCS | RST_ADCS | UPDATE_DATA_DLY | UPDATE_CLK_DLY |  |

- UPDATE_CLK_DLY [read/write]: Reset/Update ADC clock chains delay
  write 1: reset/update clock chains to its default
  values or from the values in the delay registers.
  write 0: no effect
- UPDATE_DATA_DLY [read/write]: Reset/Update ADC data chains delay
  write 1: reset/update data chains to its default
  values or from the values in the delay registers.
  write 0: no effect
- RST_ADCS [read/write]: Reset ADCs
  Reset and recalibrate ADCs
  write 0: no reset
  write 1: enable ADC reset
- RST_DIV_ADCS [read/write]: Reset Div ADCs
  Reset for synchronization between multiple ADCs
  write 0: no reset
  write 1: enable ADC div reset
- SLEEP_ADCS [read/write]: Sleep ADCs
  Sleep for ADCs
  write 0: normal operation
  write 1: enable sleep mode
- RESERVED [read-only]: Reserved
  Ignore on write, read as 0's

### 3.3. Channel 0 status register

HW prefix: | wb_fmc_250m_4ch_csr_ch0_sta
HW address: | 0x2
C prefix: | CH0_STA
C offset: | 0x8

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
VAL[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
VAL[7:0] |  |  |  |  |  |  |

- VAL [read-only]: Channel 0 current ADC value
  Current ADC raw value. The format is binary two's complement.
- RESERVED [read-only]: Reserved
  Ignore on write, read as 0's

### 3.4. Channel 0 fine delay register

HW prefix: | wb_fmc_250m_4ch_csr_ch0_fn_dly
HW address: | 0x3
C prefix: | CH0_FN_DLY
C offset: | 0xc

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED_DATA_INCDEC_DLY[5:0] | DEC_DATA_CHAIN_DLY | INC_DATA_CHAIN_DLY |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED_CLK_INCDEC_DLY[5:0] | DEC_CLK_CHAIN_DLY | INC_CLK_CHAIN_DLY |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RESERVED_DATA_CHAIN_DLY[2:0] | DATA_CHAIN_DLY[4:0] |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RESERVED_CLK_CHAIN_DLY[2:0] | CLK_CHAIN_DLY[4:0] |  |  |  |  |  |

- CLK_CHAIN_DLY [read/write]: ADC clock chain delay
  ADC clock chain delay
- RESERVED_CLK_CHAIN_DLY [read-only]: Reserved
  Ignore on write, read as 0's
- DATA_CHAIN_DLY [read/write]: ADC data chain delay
  ADC data chain delay
- RESERVED_DATA_CHAIN_DLY [read-only]: Reserved
  Ignore on write, read as 0's
- INC_CLK_CHAIN_DLY [read/write]: Increment ADC clock chains delay
  write 1: increment clock chains delay.
  write 0: no effect
- DEC_CLK_CHAIN_DLY [read/write]: Decrement ADC clock chains delay
  write 1: decrement clock chains delay.
  write 0: no effect
- RESERVED_CLK_INCDEC_DLY [read/write]: Reserved
  Ignore on write, read as 0's
- INC_DATA_CHAIN_DLY [read/write]: Increment ADC data chains delay
  write 1: increment clock chains delay.
  write 0: no effect
- DEC_DATA_CHAIN_DLY [read/write]: Decrement ADC data chains delay
  write 1: decrement clock chains delay.
  write 0: no effect
- RESERVED_DATA_INCDEC_DLY [read/write]: Reserved
  Ignore on write, read as 0's

### 3.5. Channel 0 coarse delay register

HW prefix: | wb_fmc_250m_4ch_csr_ch0_cs_dly
HW address: | 0x4
C prefix: | CH0_CS_DLY
C offset: | 0x10

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED_RG_DLY[21:14] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED_RG_DLY[13:6] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RESERVED_RG_DLY[5:0] | RG_DLY[1:0] |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RESERVED_FE_DLY[5:0] | FE_DLY[1:0] |  |  |  |  |  |

- FE_DLY [read/write]: Falling edge data delay
  write 3: delay falling edge data by two.
  write 1: delay falling edge data by one.
  write 0: no effect
- RESERVED_FE_DLY [read/write]: Reserved
  Ignore on write, read as 0's
- RG_DLY [read/write]: Regular data delay
  write 3: delay data by two.
  write 1: delay data by one.
  write 0: no effect
- RESERVED_RG_DLY [read/write]: Reserved
  Ignore on write, read as 0's

### 3.6. Channel 1 status register

HW prefix: | wb_fmc_250m_4ch_csr_ch1_sta
HW address: | 0x5
C prefix: | CH1_STA
C offset: | 0x14

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
VAL[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
VAL[7:0] |  |  |  |  |  |  |

- VAL [read-only]: Channel 1 current ADC value
  Current ADC raw value. The format is binary two's complement.
- RESERVED [read-only]: Reserved
  Ignore on write, read as 0's

### 3.7. Channel 1 fine delay register

HW prefix: | wb_fmc_250m_4ch_csr_ch1_fn_dly
HW address: | 0x6
C prefix: | CH1_FN_DLY
C offset: | 0x18

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED_DATA_INCDEC_DLY[5:0] | DEC_DATA_CHAIN_DLY | INC_DATA_CHAIN_DLY |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED_CLK_INCDEC_DLY[5:0] | DEC_CLK_CHAIN_DLY | INC_CLK_CHAIN_DLY |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RESERVED_DATA_CHAIN_DLY[2:0] | DATA_CHAIN_DLY[4:0] |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RESERVED_CLK_CHAIN_DLY[2:0] | CLK_CHAIN_DLY[4:0] |  |  |  |  |  |

- CLK_CHAIN_DLY [read/write]: ADC clock chain delay
  ADC clock chain delay
- RESERVED_CLK_CHAIN_DLY [read-only]: Reserved
  Ignore on write, read as 0's
- DATA_CHAIN_DLY [read/write]: ADC data chain delay
  ADC data chain delay
- RESERVED_DATA_CHAIN_DLY [read-only]: Reserved
  Ignore on write, read as 0's
- INC_CLK_CHAIN_DLY [read/write]: Increment ADC clock chains delay
  write 1: increment clock chains delay.
  write 0: no effect
- DEC_CLK_CHAIN_DLY [read/write]: Decrement ADC clock chains delay
  write 1: decrement clock chains delay.
  write 0: no effect
- RESERVED_CLK_INCDEC_DLY [read/write]: Reserved
  Ignore on write, read as 0's
- INC_DATA_CHAIN_DLY [read/write]: Increment ADC data chains delay
  write 1: increment clock chains delay.
  write 0: no effect
- DEC_DATA_CHAIN_DLY [read/write]: Decrement ADC data chains delay
  write 1: decrement clock chains delay.
  write 0: no effect
- RESERVED_DATA_INCDEC_DLY [read/write]: Reserved
  Ignore on write, read as 0's

### 3.8. Channel 1 coarse delay register

HW prefix: | wb_fmc_250m_4ch_csr_ch1_cs_dly
HW address: | 0x7
C prefix: | CH1_CS_DLY
C offset: | 0x1c

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED_RG_DLY[21:14] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED_RG_DLY[13:6] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RESERVED_RG_DLY[5:0] | RG_DLY[1:0] |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RESERVED_FE_DLY[5:0] | FE_DLY[1:0] |  |  |  |  |  |

- FE_DLY [read/write]: Falling edge data delay
  write 3: delay falling edge data by two.
  write 1: delay falling edge data by one.
  write 0: no effect
- RESERVED_FE_DLY [read/write]: Reserved
  Ignore on write, read as 0's
- RG_DLY [read/write]: Regular data delay
  write 3: delay data by two.
  write 1: delay data by one.
  write 0: no effect
- RESERVED_RG_DLY [read/write]: Reserved
  Ignore on write, read as 0's

### 3.9. Channel 2 status register

HW prefix: | wb_fmc_250m_4ch_csr_ch2_sta
HW address: | 0x8
C prefix: | CH2_STA
C offset: | 0x20

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
VAL[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
VAL[7:0] |  |  |  |  |  |  |

- VAL [read-only]: Channel 2 current ADC value
  Current ADC raw value. The format is binary two's complement.
- RESERVED [read-only]: Reserved
  Ignore on write, read as 0's

### 3.10. Channel 2 fine delay register

HW prefix: | wb_fmc_250m_4ch_csr_ch2_fn_dly
HW address: | 0x9
C prefix: | CH2_FN_DLY
C offset: | 0x24

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED_DATA_INCDEC_DLY[5:0] | DEC_DATA_CHAIN_DLY | INC_DATA_CHAIN_DLY |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED_CLK_INCDEC_DLY[5:0] | DEC_CLK_CHAIN_DLY | INC_CLK_CHAIN_DLY |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RESERVED_DATA_CHAIN_DLY[2:0] | DATA_CHAIN_DLY[4:0] |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RESERVED_CLK_CHAIN_DLY[2:0] | CLK_CHAIN_DLY[4:0] |  |  |  |  |  |

- CLK_CHAIN_DLY [read/write]: ADC clock chain delay
  ADC clock chain delay
- RESERVED_CLK_CHAIN_DLY [read-only]: Reserved
  Ignore on write, read as 0's
- DATA_CHAIN_DLY [read/write]: ADC data chain delay
  ADC data chain delay
- RESERVED_DATA_CHAIN_DLY [read-only]: Reserved
  Ignore on write, read as 0's
- INC_CLK_CHAIN_DLY [read/write]: Increment ADC clock chains delay
  write 1: increment clock chains delay.
  write 0: no effect
- DEC_CLK_CHAIN_DLY [read/write]: Decrement ADC clock chains delay
  write 1: decrement clock chains delay.
  write 0: no effect
- RESERVED_CLK_INCDEC_DLY [read/write]: Reserved
  Ignore on write, read as 0's
- INC_DATA_CHAIN_DLY [read/write]: Increment ADC data chains delay
  write 1: increment clock chains delay.
  write 0: no effect
- DEC_DATA_CHAIN_DLY [read/write]: Decrement ADC data chains delay
  write 1: decrement clock chains delay.
  write 0: no effect
- RESERVED_DATA_INCDEC_DLY [read/write]: Reserved
  Ignore on write, read as 0's

### 3.11. Channel 2 coarse delay register

HW prefix: | wb_fmc_250m_4ch_csr_ch2_cs_dly
HW address: | 0xa
C prefix: | CH2_CS_DLY
C offset: | 0x28

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED_RG_DLY[21:14] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED_RG_DLY[13:6] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RESERVED_RG_DLY[5:0] | RG_DLY[1:0] |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RESERVED_FE_DLY[5:0] | FE_DLY[1:0] |  |  |  |  |  |

- FE_DLY [read/write]: Falling edge data delay
  write 3: delay falling edge data by two.
  write 1: delay falling edge data by one.
  write 0: no effect
- RESERVED_FE_DLY [read/write]: Reserved
  Ignore on write, read as 0's
- RG_DLY [read/write]: Regular data delay
  write 3: delay data by two.
  write 1: delay data by one.
  write 0: no effect
- RESERVED_RG_DLY [read/write]: Reserved
  Ignore on write, read as 0's

### 3.12. Channel 3 status register

HW prefix: | wb_fmc_250m_4ch_csr_ch3_sta
HW address: | 0xb
C prefix: | CH3_STA
C offset: | 0x2c

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
VAL[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
VAL[7:0] |  |  |  |  |  |  |

- VAL [read-only]: Channel 3 current ADC value
  Current ADC raw value. The format is binary two's complement.
- RESERVED [read-only]: Reserved
  Ignore on write, read as 0's

### 3.13. Channel 3 fine delay register

HW prefix: | wb_fmc_250m_4ch_csr_ch3_fn_dly
HW address: | 0xc
C prefix: | CH3_FN_DLY
C offset: | 0x30

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED_DATA_INCDEC_DLY[5:0] | DEC_DATA_CHAIN_DLY | INC_DATA_CHAIN_DLY |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED_CLK_INCDEC_DLY[5:0] | DEC_CLK_CHAIN_DLY | INC_CLK_CHAIN_DLY |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RESERVED_DATA_CHAIN_DLY[2:0] | DATA_CHAIN_DLY[4:0] |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RESERVED_CLK_CHAIN_DLY[2:0] | CLK_CHAIN_DLY[4:0] |  |  |  |  |  |

- CLK_CHAIN_DLY [read/write]: ADC clock chain delay
  ADC clock chain delay
- RESERVED_CLK_CHAIN_DLY [read-only]: Reserved
  Ignore on write, read as 0's
- DATA_CHAIN_DLY [read/write]: ADC data chain delay
  ADC data chain delay
- RESERVED_DATA_CHAIN_DLY [read-only]: Reserved
  Ignore on write, read as 0's
- INC_CLK_CHAIN_DLY [read/write]: Increment ADC clock chains delay
  write 1: increment clock chains delay.
  write 0: no effect
- DEC_CLK_CHAIN_DLY [read/write]: Decrement ADC clock chains delay
  write 1: decrement clock chains delay.
  write 0: no effect
- RESERVED_CLK_INCDEC_DLY [read/write]: Reserved
  Ignore on write, read as 0's
- INC_DATA_CHAIN_DLY [read/write]: Increment ADC data chains delay
  write 1: increment clock chains delay.
  write 0: no effect
- DEC_DATA_CHAIN_DLY [read/write]: Decrement ADC data chains delay
  write 1: decrement clock chains delay.
  write 0: no effect
- RESERVED_DATA_INCDEC_DLY [read/write]: Reserved
  Ignore on write, read as 0's

### 3.14. Channel 3 coarse delay register

HW prefix: | wb_fmc_250m_4ch_csr_ch3_cs_dly
HW address: | 0xd
C prefix: | CH3_CS_DLY
C offset: | 0x34

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED_RG_DLY[21:14] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED_RG_DLY[13:6] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RESERVED_RG_DLY[5:0] | RG_DLY[1:0] |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RESERVED_FE_DLY[5:0] | FE_DLY[1:0] |  |  |  |  |  |

- FE_DLY [read/write]: Falling edge data delay
  write 3: delay falling edge data by two.
  write 1: delay falling edge data by one.
  write 0: no effect
- RESERVED_FE_DLY [read/write]: Reserved
  Ignore on write, read as 0's
- RG_DLY [read/write]: Regular data delay
  write 3: delay data by two.
  write 1: delay data by one.
  write 0: no effect
- RESERVED_RG_DLY [read/write]: Reserved
  Ignore on write, read as 0's

### 3.15. FMC temperature monitor register

HW prefix: | wb_fmc_250m_4ch_csr_temp
HW address: | 0xe
C prefix: | TEMP
C offset: | 0x38

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | MON_DEV

- MON_DEV [read-only]: Monitor device
  Data valid from AMC7823 chip (monitor, active low)
  0 - data available
  1 - data not valid or DAV deactivated