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//-----------------------------------------------------------------------------
// Project    : Series-7 Integrated Block for PCI Express
// File       : pipe_interconnect.v
// Version    : 1.7

`define EP board.EP.pcie_core_i.pcie_top_i
`define RP board.RP.rport.pcie_top_i

//----------------------------------------------------------  PIO RTL & RP simulation  -------------------------------------------------------------------//  
generate
 if (PIPE_SIM == "TRUE")
  begin
   assign `EP.pipe_rx0_char_is_k_gt = `RP.pipe_tx0_char_is_k_gt;   
   assign `EP.pipe_rx1_char_is_k_gt = `RP.pipe_tx1_char_is_k_gt;   
   assign `EP.pipe_rx2_char_is_k_gt = `RP.pipe_tx2_char_is_k_gt;   
   assign `EP.pipe_rx3_char_is_k_gt = `RP.pipe_tx3_char_is_k_gt;   
   assign `EP.pipe_rx4_char_is_k_gt = `RP.pipe_tx4_char_is_k_gt;   
   assign `EP.pipe_rx5_char_is_k_gt = `RP.pipe_tx5_char_is_k_gt;   
   assign `EP.pipe_rx6_char_is_k_gt = `RP.pipe_tx6_char_is_k_gt;   
   assign `EP.pipe_rx7_char_is_k_gt = `RP.pipe_tx7_char_is_k_gt;   

   assign `EP.pipe_rx0_data_gt      = `RP.pipe_tx0_data_gt;   
   assign `EP.pipe_rx1_data_gt      = `RP.pipe_tx1_data_gt;   
   assign `EP.pipe_rx2_data_gt      = `RP.pipe_tx2_data_gt;   
   assign `EP.pipe_rx3_data_gt      = `RP.pipe_tx3_data_gt;   
   assign `EP.pipe_rx4_data_gt      = `RP.pipe_tx4_data_gt;   
   assign `EP.pipe_rx5_data_gt      = `RP.pipe_tx5_data_gt;   
   assign `EP.pipe_rx6_data_gt      = `RP.pipe_tx6_data_gt;   
   assign `EP.pipe_rx7_data_gt      = `RP.pipe_tx7_data_gt;   
//-------------------------------------------------------------------------------------------------------------------------//  
   assign `RP.pipe_rx0_char_is_k_gt = `EP.pipe_tx0_char_is_k_gt;   
   assign `RP.pipe_rx1_char_is_k_gt = `EP.pipe_tx1_char_is_k_gt;   
   assign `RP.pipe_rx2_char_is_k_gt = `EP.pipe_tx2_char_is_k_gt;   
   assign `RP.pipe_rx3_char_is_k_gt = `EP.pipe_tx3_char_is_k_gt;   
   assign `RP.pipe_rx4_char_is_k_gt = `EP.pipe_tx4_char_is_k_gt;   
   assign `RP.pipe_rx5_char_is_k_gt = `EP.pipe_tx5_char_is_k_gt;   
   assign `RP.pipe_rx6_char_is_k_gt = `EP.pipe_tx6_char_is_k_gt;   
   assign `RP.pipe_rx7_char_is_k_gt = `EP.pipe_tx7_char_is_k_gt;   

   assign `RP.pipe_rx0_data_gt      = `EP.pipe_tx0_data_gt;
   assign `RP.pipe_rx1_data_gt      = `EP.pipe_tx1_data_gt;
   assign `RP.pipe_rx2_data_gt      = `EP.pipe_tx2_data_gt;
   assign `RP.pipe_rx3_data_gt      = `EP.pipe_tx3_data_gt;
   assign `RP.pipe_rx4_data_gt      = `EP.pipe_tx4_data_gt;
   assign `RP.pipe_rx5_data_gt      = `EP.pipe_tx5_data_gt;
   assign `RP.pipe_rx6_data_gt      = `EP.pipe_tx6_data_gt;
   assign `RP.pipe_rx7_data_gt      = `EP.pipe_tx7_data_gt;
  end
 endgenerate
//----------------------------------------------------------------------------------------------------------------------------------------------------------//  
