--------------------------------------------------------------------------------
-- Title      : 10/100/1G Ethernet FIFO
-- Project    : Xilinx LogiCORE Virtex-6 Embedded Tri-Mode Ethernet MAC
-- File       : ten_100_1g_eth_fifo.vhd
-- Version    : 2.2
-------------------------------------------------------------------------------
--
-- (c) Copyright 2004-2011 Xilinx, Inc. All rights reserved.
--
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-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
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--
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--
--------------------------------------------------------------------------------
-- Description: This is the top level wrapper for the 10/100/1G Ethernet FIFO.
--              The top level wrapper consists of individual FIFOs on the
--              transmitter path and on the receiver path.
--------------------------------------------------------------------------------


library unisim;
use unisim.vcomponents.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;


--------------------------------------------------------------------------------
-- The entity declaration for the FIFO
--------------------------------------------------------------------------------

entity ten_100_1g_eth_fifo is
   generic (
        FULL_DUPLEX_ONLY    : boolean := true);      -- If fifo is to be used only in full
                                              -- duplex set to true for optimized implementation
   port (
        tx_fifo_aclk                : in  std_logic;
        tx_fifo_resetn              : in  std_logic;
        tx_axis_fifo_tdata          : in  std_logic_vector(7 downto 0);
        tx_axis_fifo_tvalid         : in  std_logic;
        tx_axis_fifo_tlast          : in  std_logic;
        tx_axis_fifo_tready         : out std_logic;

        tx_mac_aclk                 : in  std_logic;
        tx_mac_resetn               : in  std_logic;
        tx_axis_mac_tdata           : out std_logic_vector(7 downto 0);
        tx_axis_mac_tvalid          : out std_logic;
        tx_axis_mac_tlast           : out std_logic;
        tx_axis_mac_tready          : in  std_logic;
        tx_axis_mac_tuser           : out std_logic;
        tx_fifo_overflow            : out std_logic;
        tx_fifo_status              : out std_logic_vector(3 downto 0);
        tx_collision                : in  std_logic;
        tx_retransmit               : in  std_logic;

        rx_fifo_aclk                : in  std_logic;
        rx_fifo_resetn              : in  std_logic;
        rx_axis_fifo_tdata          : out std_logic_vector(7 downto 0);
        rx_axis_fifo_tvalid         : out std_logic;
        rx_axis_fifo_tlast          : out std_logic;
        rx_axis_fifo_tready         : in  std_logic;

        rx_mac_aclk                 : in  std_logic;
        rx_mac_resetn               : in  std_logic;
        rx_axis_mac_tdata           : in  std_logic_vector(7 downto 0);
        rx_axis_mac_tvalid          : in  std_logic;
        rx_axis_mac_tlast           : in  std_logic;
        rx_axis_mac_tready          : out std_logic;
        rx_axis_mac_tuser           : in  std_logic;
        rx_fifo_status              : out std_logic_vector(3 downto 0);
        rx_fifo_overflow            : out std_logic
  );
end ten_100_1g_eth_fifo;

architecture RTL of ten_100_1g_eth_fifo is

component rx_client_fifo_8
  port (
     -- User-side (read-side) AxiStream interface
     rx_fifo_aclk   : in  std_logic;
     rx_fifo_resetn : in  std_logic;
     rx_axis_fifo_tdata : out std_logic_vector(7 downto 0);
     rx_axis_fifo_tvalid : out std_logic;
     rx_axis_fifo_tlast  : out std_logic;
     rx_axis_fifo_tready : in  std_logic;

     -- MAC-side (write-side) AxiStream interface
     rx_mac_aclk    : in  std_logic;
     rx_mac_resetn  : in  std_logic;
     rx_axis_mac_tdata : in  std_logic_vector(7 downto 0);
     rx_axis_mac_tvalid : in  std_logic;
     rx_axis_mac_tlast  : in  std_logic;
     rx_axis_mac_tready : out std_logic;
     rx_axis_mac_tuser  : in  std_logic;

     -- FIFO status and overflow indication,
     -- synchronous to write-side (rx_mac_aclk) interface
     fifo_status    : out std_logic_vector(3 downto 0);
     fifo_overflow  : out std_logic
     );
end component;

component tx_client_fifo_8
  generic (
     FULL_DUPLEX_ONLY : boolean := false);
  port (
     -- User-side (write-side) AxiStream interface
     tx_fifo_aclk    : in  std_logic;
     tx_fifo_resetn  : in  std_logic;
     tx_axis_fifo_tdata : in  std_logic_vector(7 downto 0);
     tx_axis_fifo_tvalid : in  std_logic;
     tx_axis_fifo_tlast  : in  std_logic;
     tx_axis_fifo_tready : out std_logic;

     -- MAC-side (read-side) AxiStream interface
     tx_mac_aclk     : in  std_logic;
     tx_mac_resetn   : in  std_logic;
     tx_axis_mac_tdata : out  std_logic_vector(7 downto 0);
     tx_axis_mac_tvalid : out std_logic;
     tx_axis_mac_tlast  : out std_logic;
     tx_axis_mac_tready : in  std_logic;
     tx_axis_mac_tuser  : out std_logic;

     -- FIFO collision and retransmission requests from MAC
     tx_collision    : in  std_logic;
     tx_retransmit   : in  std_logic;
     
     -- FIFO status and overflow indication,
     -- synchronous to write-side (tx_user_aclk) interface
     fifo_overflow   : out std_logic;
     fifo_status     : out std_logic_vector(3 downto 0)

     );
end component;

begin

  ------------------------------------------------------------------------------
  -- Instantiate the Transmitter FIFO
  ------------------------------------------------------------------------------
  tx_fifo_i : tx_client_fifo_8
  generic map(
    FULL_DUPLEX_ONLY    => FULL_DUPLEX_ONLY
  )
  port map(
    tx_fifo_aclk        => tx_fifo_aclk,
    tx_fifo_resetn      => tx_fifo_resetn,
    tx_axis_fifo_tdata  => tx_axis_fifo_tdata,
    tx_axis_fifo_tvalid => tx_axis_fifo_tvalid,
    tx_axis_fifo_tlast  => tx_axis_fifo_tlast,
    tx_axis_fifo_tready => tx_axis_fifo_tready,

    tx_mac_aclk         => tx_mac_aclk,
    tx_mac_resetn       => tx_mac_resetn,
    tx_axis_mac_tdata   => tx_axis_mac_tdata,
    tx_axis_mac_tvalid  => tx_axis_mac_tvalid,
    tx_axis_mac_tlast   => tx_axis_mac_tlast,
    tx_axis_mac_tready  => tx_axis_mac_tready,
    tx_axis_mac_tuser   => tx_axis_mac_tuser,

    tx_collision        => tx_collision,
    tx_retransmit       => tx_retransmit,

    fifo_overflow       => tx_fifo_overflow,
    fifo_status         => tx_fifo_status
  );


  ------------------------------------------------------------------------------
  -- Instantiate the Receiver FIFO
  ------------------------------------------------------------------------------
  rx_fifo_i : rx_client_fifo_8
  port map(

    rx_fifo_aclk        => rx_fifo_aclk,
    rx_fifo_resetn      => rx_fifo_resetn,
    rx_axis_fifo_tdata  => rx_axis_fifo_tdata,
    rx_axis_fifo_tvalid => rx_axis_fifo_tvalid,
    rx_axis_fifo_tlast  => rx_axis_fifo_tlast,
    rx_axis_fifo_tready => rx_axis_fifo_tready,

    rx_mac_aclk         => rx_mac_aclk,
    rx_mac_resetn       => rx_mac_resetn,
    rx_axis_mac_tdata   => rx_axis_mac_tdata,
    rx_axis_mac_tvalid  => rx_axis_mac_tvalid,
    rx_axis_mac_tlast   => rx_axis_mac_tlast,
    rx_axis_mac_tready  => rx_axis_mac_tready,
    rx_axis_mac_tuser   => rx_axis_mac_tuser,

    fifo_status         => rx_fifo_status,
    fifo_overflow       => rx_fifo_overflow
  );


end RTL;
