BabyWR
Project description
BabyWR is being developed as a cost effective and small pluggable WR node. BabyWR has a M.2 form-factor. BabyWR is designed for low phase noise (10 MHz; < -100 dBc/Hz @ 10 Hz) timing generation. For applications that demand ultimate low phase noise, an external high precision oscillator can be disciplined and used as reference clock.
This M.2 Type 2280-D6-M form factor module is a Phase Noise improved version of it's predecessor. The 10 MHz and 1 PPS signals that are generated by the White Rabbit PTP Core on the FPGA are re-clocked by the clean reference oscillator. By re-arranging the assembly of a few resistors, the module allows to output the clean 100 MHz reference clock signal directly, once "lock sweep" is implemented.
BabyWR-Carrier is a SPEC like PCIe card (Figure 3) that can accept a BabyWR for test purposes. Like the SPEC, BabyWR-Carrier has a PCIe interface, an SFP+ cage, a (not fully populated) LPC FMC connector, JTAG- and USB-interface, LEDs, button and GPIO headers.
BabyWR Main Features
Figure 1: BabyWR PCB (11300.13.01.1).
Figure 2: BabyWR Phase Noise performance.
Figure 2 shows the 10MHz Phase Noise performance of BabyWR (blue trace). The orange trace shows the performance of the SiTime reference oscillator (in this case 100MHz). In order to be able to compare the 10 and 100 MHz trace the SiTime 100 MHz trace is normalized to 10MHz by subtracting 20 dB (this is just an indication; in reality the dashed line may be below the actual noise floor at higher offset frequencies).
From 1 KHz and beyond the noise floor is dominated by the re-clocking Flip-Flops.
BabyWR Main Features
- M.2 Type 2280-D6-M
- Form-factor 22x80 mm
- Key-M (Socket 3 PCIe-based Adapter)
- PCIe x1 Gen3
-
Xilinx Artix UltraScale+ xcau10p-sbvb484-1 (-1= slowest, commercial temp range, fast enough for most applications). Note that xcau15p-sbvb484-1 is pin compatible.
- 12 GTH (12.5 Gb/s: 1 used for PCIe, 1 used for SFP)
- 2 GTH reference clocks (PCIe clock, Local WR refclk, External WR refclk via M.2 connector, External WR refclk via U.FL coax or M.2 connector)
- Clocking resources
- 1x SiTime5359-100.000 MHz DCTCXO WR local reference clock (-85 dBc/Hz @ 10 Hz)
- 1x SiTime5359-124.992 MHz DCTCXO WR dmtd helper clock (-85 dBc/Hz @ 10 Hz)
- Possibility for connecting high precision low phase noise external reference oscillator via either M.2 connector (pin 17, 19) or via U.FL connectors (2, 3)
- 1:4 clock fan-out and two re-clocking Flip-Flops to cleanup 10 MHz and 1 PPS
- On board memory
- 128 Mbit FLASH (can contain 2 FPGA configuration images)
- 64K (8K x 8-bit) I2C Serial EEPROM (24AA64T-I/MC) for storing serial number, calibration parameters and other critical data
- 2K (128 x 8-bit) I2C Serial EEPROM (24AA025E48) which provides EUI-48
- Miscellaneous
- 4x U.FL coaxial conectors (1-2 for absolute calibration or general purpose, 3-4 for external reference clock)
- JTAG interface via M.2 connector pins
- SFP logical signals (I2C, LOS_Fault, Mod_ABS) via M.2 connector pins
- WRCLK (default 10 MHz), 1 PPS differential outputs via M.2 connector pins
- 9 GPIO3V3 lines (can be used for: UART, SPI DAC interface for external reference oscillator, reset, auxiliary I2C, etc.)
- 3 GPIO1V8 lines (can be used for: reset etc.)
- 10 MHz, 1 PPS differential inputs on testpads (possibility to use BabyWR in Grand-Master mode)
- 4 GPIO LEDs
- 1 LED FPGA configuration DONE
- SMD 0402 land pattern used as configuration button.
- 8 layer PCB
- All signals ESD protected
- Power consumption
- 1,9 Watt (3V3)
BabyWR-Carrier
BabyWR-Carrier Main Features
- PCIe x1 Gen3 Carrier Board
- a test vehicle for BabyWR M.2 module
- FMC slot with LPC connector containing IO signals from BabyWR
- 7 differential pairs
- 5 single ended signals
- Vadj 3V3
- Front panel containing
- 1x Small Formfactor Pluggable+ (SFP+) cage for fibre-optic transceiver (WhiteRabbit support)
- Red and Green LEDs connected to programmable BabyWR GPIO lines
- Internal connectors
- M.2 Card Connector, Key-M, Height 4.2
- 1x JTAG header to access BabyWR Xilinx programming and during debugging
- 1x USB-C connector
- Can serve two UARTs over the same single USB-C connector with CP2105 - Dual UART bridge IC
- UART signals available on programmable BabyWR GPIO signals
- 10x SMA connectors
- 2x for differential external 125 MHz WR reference clock input from optional high precision external oscillator
- 2x for differential WRCLK (default 10 MHz) output clock (or other signal depending on BabyWR configuration)
- 2x for differential PPS output (or other signal depending on BabyWR configuration)
- 4x SMA connectors that translate to 4x U.FL connectors
- 4x U.FL connectors that can connected the BabyWR U.FL connectors via coax
- access to BabyWR optional external reference clock and RF GPIO (U.FL connectors)
- 1x10 pin header for access programmable BabyWR 3V3 GPIO signals
- 1x5 pin header for access programmable BabyWR 1V8 GPIO signals
- 4x 3-pin jumper to select UART or FMC pins for connecting to programmable BabyWR GPIO signals
- 2 Test points for BabyWR power Supply current sensing (20mV/A)
- Stand-alone features
- External 12V ATX power supply connector
- USB-C connector
- SFP+ cage for fibre-optic transceiver (WhiteRabbit support)
- 4x LEDs on programmable BabyWR GPIO lines
- 1x Button on programmable BabyWR GPIO line (e.g. for Reset)
- All signals ESD protected
- 8 layer PCB
- Power consumption 400 mW (Bare, without BabyWR module plugged).
Project information
- Official production documentation
- BabyWR Schematics 11300.13.02.1 (Note: Design created with Mentor Graphics using a Xpedition License).
- BabyWR PCB Manufacturing files 11300.13.01.1_PCB (available once Qualified by the WR Calaboration) (Note: PCB Design created with Mentor Graphics using a Xpedition License)
- BabyWR Assembly Manufacturing files 11300.13.01.1_PCA (available once Qualified by the WR Calaboration) (Note: PCB Design created with Mentor Graphics using a Xpedition License)
- BabyWR-Carrier Schematics 11300.10.02.1 (Note: Design created with Mentor Graphics using a Xpedition License).
- BabyWR-Carrier Manufacturing files 11300.10.02.1 (Note: PCB Design created with Mentor Graphics using a Xpedition License)
- Frequently Asked Questions
- VCXOPlayGround_i2c, a pre-study project was started to test the feasibility of SiTime-5359 I2C controllable DCTCXO
- Related BabyWR information, for example older versions.
Projects that are planning to use BabyWR
Contacts
Commercial producers
- Once designed and debugged, the board might become commercially available.
General questions about project
- Peter Jansweijer, Guido Visser - Nikhef
Status
Date | Event |
---|---|
03-01-2022 | Start working on project. |
05-07-2022 | BabyWR PCB layout Ready, BabyWR-Carrier PCB layout starting. |
13-09-2022 | BabyWR PCB layout revised, BabyWR-Carrier PCB layout ready. |
25-11-2022 | 2 BabyWR M.2 modules and 5 BabyWR-Carrier boards received |
26-01-2023 | After solving small issues BabyWR and BabyWR-Carrier fully functional but don't meet phase noise expectations |
05-04-2023 | 4 more BabyWR M.2 modules boards received or further testing and characterization. |
03-11-2023 | Layout for a next version BabyWR M.2 module is in progress. |
07-11-2023 | Four BabyWR Carriers (next version repairing few bugs) received and functional. |
11-03-2024 | Received 5 BabyWR_2280-D6-M boards (with ReClocking FlipFlops; unfortunately the wrong PCB thickness). |
13-03-2024 | Added Phase Noise performance for BabyWR v2.0. |
25 March 2024