Add Verilog versions for the basic AsyncArt library

c3ae952a · Javier D. Garcia-Lasheras · f650972c · c3ae952a · c3ae952a · c3ae952a
Commit c3ae952a authored Aug 24, 2019 by Javier D. Garcia-Lasheras
Showing with 168 additions and 0 deletions

asyncart_demo.v hdl/verilog/asyncart_demo.v +98 -0

asyncart_reg.v hdl/verilog/asyncart_reg.v +24 -0

asyncart_sink.v hdl/verilog/asyncart_sink.v +23 -0

asyncart_source.v hdl/verilog/asyncart_source.v +23 -0

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--- a/hdl/verilog/asyncart_demo.v
+++ b/hdl/verilog/asyncart_demo.v
+
+`include "asyncart_source.v"
+`include "asyncart_sink.v"
+`include "asyncart_reg.v"
+
+module sync_register_32b (
+    output [31:0] data_out,
+    input [31:0] data_in,
+    input clk,
+    input enable,
+    input reset);
+    reg [31:0] data_reg;
+    always @(posedge clk)
+    if (reset) begin
+        data_reg <= 32'b0 ;
+    end else if (enable) begin
+        data_reg <= data_in;
+    end
+    assign data_out = data_reg;
+endmodule
+
+
+module asyncart_demo(
+	input act_in,
+	input rst_in,
+	output [31:0] data_out,
+	);
+
+
+	wire reset = 0;
+	wire enable = 1;
+
+        parameter PIPE_DEPTH = 3;
+
+        wire [PIPE_DEPTH-1:0] fire;
+        wire [PIPE_DEPTH-1:0] phase;
+        wire [31:0] data_link [PIPE_DEPTH:0];
+        wire act, rst;
+
+        assign act = act_in;
+        assign rst = rst_in;
+
+
+        asyncart_source asyncart_source_instance (
+            .fire_out(fire[0]),
+            .phase_out(phase[0]),
+            .phase_in_neg(phase[1]),
+            .act(act),
+            .rst(rst)
+        );
+
+
+        genvar i;
+        generate
+            for (i=1; i<PIPE_DEPTH-1; i=i+1) begin : asyncart_reg_block
+            asyncart_reg asyncart_reg_instance (
+                .fire_out(fire[i]),
+                .phase_out(phase[i]),
+                .phase_in_pos(phase[i-1]),
+                .phase_in_neg(phase[i+1]),
+                .act(act),
+                .rst(rst)
+            );
+        end 
+        endgenerate
+
+
+        asyncart_sink asyncart_sink_instance (
+            .fire_out(fire[PIPE_DEPTH-1]),
+            .phase_out(phase[PIPE_DEPTH-1]),
+            .phase_in_pos(phase[PIPE_DEPTH-2]),
+            .act(act),
+            .rst(rst)
+        );
+
+
+
+        genvar j;
+        generate
+            for (j=0; j<=PIPE_DEPTH-1; j=j+1) begin : sync_register_block
+            sync_register_32b sync_register_32b_instance (
+                .data_in(data_link[j]),
+                .data_out(data_link[j+1]),
+                .clk(fire[j]),
+                .enable(enable),
+                .reset(reset)
+            );
+        end
+        endgenerate
+
+
+        // Implement an Up-Counter in the source register (first pipeline stage)
+	assign data_link[0] = data_link[1] + 1;
+
+        // Connect the Red LEDs to the 4 MSB bits in the sink registed (last pipeline stage)
+	assign data_out = data_link[PIPE_DEPTH];
+
+endmodule
--- a/hdl/verilog/asyncart_reg.v
+++ b/hdl/verilog/asyncart_reg.v
+module asyncart_reg (
+    output fire_out, 
+    output phase_out,
+    input phase_in_pos,
+    input phase_in_neg,
+    input act,
+    input rst);
+
+reg phase;
+wire fire;
+
+always @(posedge fire or posedge rst)
+begin
+    if (rst) 
+            phase <= 1'b0 ;
+    else
+            phase <= ! phase;
+end
+
+assign fire = (phase_in_pos ^ phase) & (phase_in_neg ~^ phase) & act;
+assign phase_out = phase;
+assign fire_out = fire;
+
+endmodule
--- a/hdl/verilog/asyncart_sink.v
+++ b/hdl/verilog/asyncart_sink.v
+module asyncart_sink (
+    output fire_out,
+    output phase_out,
+    input phase_in_pos,
+    input act,
+    input rst);
+
+reg phase;
+wire fire;
+
+always @(posedge fire or posedge rst)
+begin
+    if (rst)
+            phase <= 1'b0 ;
+    else
+            phase <= ! phase;
+end
+
+assign fire = (phase_in_pos ^ phase) & act;
+assign phase_out = phase;
+assign fire_out = fire;
+
+endmodule
--- a/hdl/verilog/asyncart_source.v
+++ b/hdl/verilog/asyncart_source.v
+module asyncart_source (
+    output fire_out, 
+    output phase_out,
+    input phase_in_neg,
+    input act,
+    input rst);
+
+reg phase;
+wire fire;
+
+always @(posedge fire or posedge rst)
+begin
+    if (rst) 
+            phase <= 1'b0 ;
+    else
+            phase <= ! phase;
+end
+
+assign fire = (phase_in_neg ~^ phase) & act;
+assign phase_out = phase;
+assign fire_out = fire;
+
+endmodule