Proper license and attribution for the iCEstick hardware demo

79795124 · Javier D. Garcia-Lasheras · f213171c · 79795124 · 79795124
Commit 79795124 authored Aug 25, 2019 by Javier D. Garcia-Lasheras
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LICENSE.txt demo/hardware/LICENSE.txt +202 -0

micropipeline.v demo/hardware/micropipeline.v +36 -0

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--- a/demo/hardware/LICENSE.txt
+++ b/demo/hardware/LICENSE.txt
--- a/demo/hardware/micropipeline.v
+++ b/demo/hardware/micropipeline.v
+//-----------------------------------------------------------------------------
+// Title      : AsyncArt micropipeline demo for iCEstick
+// Project    : AsyncArt
+// URL        : https://www.ohwr.org/project/asyncart
+//-----------------------------------------------------------------------------
+// File       : micropipeline.v
+// Author(s)  : Javier Garcia Lasheras <jgarcia@gl-research.com>
+// Company    : GL Research Corporation SLU
+//-----------------------------------------------------------------------------
+// Description: Demonstrative micropipeline demo for the iCEstick FPGA board.
+//-----------------------------------------------------------------------------
+// Copyright (c) 2019 GL Research Corporation SLU
+//-----------------------------------------------------------------------------
+// APACHE LICENSE, VERSION 2.0
+//-----------------------------------------------------------------------------
+
+/*
+ * This micropipeline demo for the iCEstick is based on:
+ *
+ *    https://github.com/cyrozap/iCEstick-UART-Demo
+ *
+ * Copyright 2015 Forest Crossman <cyrozap@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */

 `include "../../ip_cores/osdvu/uart.v"
 `include "../../hdl/verilog/asyncart_demo.v"