... | ... | @@ -56,8 +56,7 @@ tricks and blocks than can be easily reused. |
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In order to make easier the use of this techniques for educative
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purposes, the released reference designs has been standarized by porting
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them to a free to use for non commercial purposes project development
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environment.
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them to a free to use project development environment.
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By date of 2012/12/27, the development environment is comprised by:
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... | ... | @@ -81,13 +80,19 @@ By date of 2012/12/27, the development environment is comprised by: |
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synthesis and simulation, implementation, device fitting, and JTAG
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programming.
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## Micropipelines
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The AsyncArt project deriverables are then compressed full Xilinx ISE
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projects, all of them consisting in two fundamental blocks:
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## Dual-Rail
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- TOP-Level Schematic:
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## 1 to N Bus
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<!-- end list -->
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- VHDL Test Bench:
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NOTE: A single deliverable may contain more than one schematic/testbench
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pair
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[demo1](demo1)
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[Design-Catalog](Design-Catalog)
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# Licensing
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... | ... | |