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AMC CPU COM6
Commit 00ff7a96 authored by Tomasz Janicki's avatar Tomasz Janicki 💬
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DOC/SCB_SAM9G45_GK/CPU_100M_Ethernet.Harness 0 → 100644
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ETH_100MHz=SHIELD,TX_P,TX_N,RX_P,RX_N,LED_LINK,LED_ACT
DOC/SCB_SAM9G45_GK/CPU_100M_Ethernet.SchDocPreview 0 → 100644
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DOC/SCB_SAM9G45_GK/CPU_DDR2.SchDocPreview 0 → 100644
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DOC/SCB_SAM9G45_GK/CPU_EBI1_FPGA_Memory.SchDocPreview 0 → 100644
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DOC/SCB_SAM9G45_GK/CPU_IO_Ports.Harness 0 → 100644
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CPU_SSC=RF1,RK1,RD1,TD1,TK1,TF1
SPI1=SPI1_NPCS0,SPI1_SPCK,SPI1_MOSI,SPI1_MISO
DOC/SCB_SAM9G45_GK/CPU_IO_Ports.SchDocPreview 0 → 100644
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DOC/SCB_SAM9G45_GK/CPU_JTAG_Power_PLL.Harness 0 → 100644
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CPU_JTAG=JNRST,JTDO,JRTCK,JTCK,JTMS,JTDI,JNTRST
DOC/SCB_SAM9G45_GK/CPU_JTAG_Power_PLL.SchDocPreview 0 → 100644
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DOC/SCB_SAM9G45_GK/Connectors.Harness 0 → 100644
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CPU_JTAG=JNTRST,JTDI,JTMS,JTCK,JRTCK,JTDO,JNRST
CPU_SSC=TF1,TK1,TD1,RD1,RK1,RF1
CPU_USB=USB_HDP_N,USB_HDP_P,USB_DDP_N,USB_DDP_P
ETH_100MHz=LED_ACT,LED_LINK,RX_N,RX_P,TX_N,TX_P,SHIELD
FPGA_JTAG=FPGA_TMS,FPGA_TCK,FPGA_TDO,FPGA_TDI
MGTRX112PN=MGTRX112_0_P,MGTRX112_0_N,MGTRX112_1_P,MGTRX112_1_N,MGTRX112_2_P,MGTRX112_2_N,MGTRX112_3_P,MGTRX112_3_N
MGTRX113PN=MGTRX113_0_P,MGTRX113_0_N,MGTRX113_1_P,MGTRX113_1_N,MGTRX113_2_P,MGTRX113_2_N,MGTRX113_3_P,MGTRX113_3_N
MGTRX114PN=MGTRX114_0_P,MGTRX114_0_N,MGTRX114_1_P,MGTRX114_1_N,MGTRX114_2_P,MGTRX114_2_N,MGTRX114_3_P,MGTRX114_3_N
MGTRX115PN=MGTRX115_0_P,MGTRX115_0_N,MGTRX115_1_P,MGTRX115_1_N,MGTRX115_2_P,MGTRX115_2_N,MGTRX115_3_P,MGTRX115_3_N
MGTRX116PN=MGTRX116_0_P,MGTRX116_0_N,MGTRX116_1_P,MGTRX116_1_N,MGTRX116_2_P,MGTRX116_2_N,MGTRX116_3_P,MGTRX116_3_N
MGTTX112PN=MGTTX112_0_N,MGTTX112_0_P,MGTTX112_1_P,MGTTX112_1_N,MGTTX112_2_P,MGTTX112_2_N,MGTTX112_3_P,MGTTX112_3_N
MGTTX113PN=MGTTX113_0_P,MGTTX113_0_N,MGTTX113_1_P,MGTTX113_1_N,MGTTX113_2_P,MGTTX113_2_N,MGTTX113_3_P,MGTTX113_3_N
MGTTX114PN=MGTTX114_0_P,MGTTX114_0_N,MGTTX114_1_P,MGTTX114_1_N,MGTTX114_2_P,MGTTX114_2_N,MGTTX114_3_P,MGTTX114_3_N
MGTTX115PN=MGTTX115_0_P,MGTTX115_0_N,MGTTX115_1_P,MGTTX115_1_N,MGTTX115_2_P,MGTTX115_2_N,MGTTX115_3_P,MGTTX115_3_N
MGTTX116PN=MGTTX116_0_P,MGTTX116_0_N,MGTTX116_1_P,MGTTX116_1_N,MGTTX116_2_P,MGTTX116_2_N,MGTTX116_3_P,MGTTX116_3_N
RS232_MNG=RS232_MNG_TXD,RS232_MNG_RXD,RS232_FPGA_TXD,RS232_FPGA_RXD
uTCA_CLK=UTCA_TONGUE2_CLK1_P,UTCA_TONGUE2_CLK1_N,UTCA_TONGUE2_CLK2_P,UTCA_TONGUE2_CLK2_N,MINIBACKPLANE_CLK_P,MINIBACKPLANE_CLK_N
DOC/SCB_SAM9G45_GK/Connectors.SchDocPreview 0 → 100644
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DOC/SCB_SAM9G45_GK/External WatchDogs.Harness 0 → 100644
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FPGA_WD=FPGA_WD_SCL,FPGA_WD_SDA,FPGA_WD_INT,FPGA_WD_PROGRAM
DOC/SCB_SAM9G45_GK/External WatchDogs.SchDocPreview 0 → 100644
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DOC/SCB_SAM9G45_GK/FPGA_Configuration.Harness 0 → 100644
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FPGA_JTAG=FPGA_TMS,FPGA_TCK,FPGA_TDI,FPGA_TDO
FPGA_WD=FPGA_WD_SCL,FPGA_WD_SDA,FPGA_WD_INT,FPGA_WD_PROGRAM
QDRII_CLKS=QDRII_CLK_P,QDRII_CLK_N,QDRII_200CLK_P,QDRII_200CLK_N
DOC/SCB_SAM9G45_GK/FPGA_Configuration.SchDocPreview 0 → 100644
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DOC/SCB_SAM9G45_GK/FPGA_GPIOs.SchDocPreview 0 → 100644
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DOC/SCB_SAM9G45_GK/FPGA_GTX.Harness 0 → 100644
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MGTREFCLK=MGTREFCLK112_P,MGTREFCLK112_N,MGTREFCLK113_P,MGTREFCLK113_N,MGTREFCLK114_P,MGTREFCLK114_N,MGTREFCLK115_P,MGTREFCLK115_N,MGTREFCLK116_P,MGTREFCLK116_N
MGTRX112PN=MGTRX112_0_P,MGTRX112_0_N,MGTRX112_1_P,MGTRX112_1_N,MGTRX112_2_P,MGTRX112_2_N,MGTRX112_3_P,MGTRX112_3_N
MGTRX113PN=MGTRX113_0_P,MGTRX113_0_N,MGTRX113_1_P,MGTRX113_1_N,MGTRX113_2_P,MGTRX113_2_N,MGTRX113_3_P,MGTRX113_3_N
MGTRX114PN=MGTRX114_0_P,MGTRX114_0_N,MGTRX114_1_P,MGTRX114_1_N,MGTRX114_2_P,MGTRX114_2_N,MGTRX114_3_P,MGTRX114_3_N
MGTRX115PN=MGTRX115_0_P,MGTRX115_0_N,MGTRX115_1_P,MGTRX115_1_N,MGTRX115_2_P,MGTRX115_2_N,MGTRX115_3_P,MGTRX115_3_N
MGTRX116PN=MGTRX116_0_P,MGTRX116_0_N,MGTRX116_1_P,MGTRX116_1_N,MGTRX116_2_P,MGTRX116_2_N,MGTRX116_3_P,MGTRX116_3_N
MGTTX112PN=MGTTX112_0_P,MGTTX112_0_N,MGTTX112_1_P,MGTTX112_1_N,MGTTX112_2_P,MGTTX112_2_N,MGTTX112_3_P,MGTTX112_3_N
MGTTX113PN=MGTTX113_0_P,MGTTX113_0_N,MGTTX113_1_P,MGTTX113_1_N,MGTTX113_2_P,MGTTX113_2_N,MGTTX113_3_P,MGTTX113_3_N
MGTTX114PN=MGTTX114_0_P,MGTTX114_0_N,MGTTX114_1_P,MGTTX114_1_N,MGTTX114_2_P,MGTTX114_2_N,MGTTX114_3_P,MGTTX114_3_N
MGTTX115PN=MGTTX115_0_P,MGTTX115_0_N,MGTTX115_1_P,MGTTX115_1_N,MGTTX115_2_P,MGTTX115_2_N,MGTTX115_3_P,MGTTX115_3_N
MGTTX116PN=MGTTX116_0_P,MGTTX116_0_N,MGTTX116_1_P,MGTTX116_1_N,MGTTX116_2_P,MGTTX116_2_N,MGTTX116_3_P,MGTTX116_3_N
DOC/SCB_SAM9G45_GK/FPGA_GTX.SchDocPreview 0 → 100644
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DOC/SCB_SAM9G45_GK/FPGA_PLLs.Harness 0 → 100644
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MGTREFCLK=MGTREFCLK116_P,MGTREFCLK116_N,MGTREFCLK115_P,MGTREFCLK115_N,MGTREFCLK114_P,MGTREFCLK114_N,MGTREFCLK113_P,MGTREFCLK113_N,MGTREFCLK112_P,MGTREFCLK112_N
PLL_CONTROL=PLL_SYNC,PLL_SDI,PLL_SDO,PLL_SCLK,PLL_REFSEL,PLL_RESET,PLL_LOCK,PLL_STAT,PLL_CS,CLK1_SEL
QDRII_CLKS=QDRII_CLK_P,QDRII_CLK_N,QDRII_200CLK_P,QDRII_200CLK_N
uTCA_CLK=UTCA_TONGUE2_CLK1_P,UTCA_TONGUE2_CLK1_N,UTCA_TONGUE2_CLK2_P,UTCA_TONGUE2_CLK2_N
DOC/SCB_SAM9G45_GK/FPGA_POWER_DGND.SchDocPreview 0 → 100644
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DOC/SCB_SAM9G45_GK/FPGA_Peripherals_Control.Harness 0 → 100644
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DAC_CONTROL=DAC_DMTD_DIN,DAC_DMTD_SYNC,DAC_DMTD_SCLK,DAC_REF_DIN,DAC_REF_SYNC,DAC_REF_SCLK
PLL_CONTROL=CLK_EN,CLK1_SEL,PLL_CS,PLL_STAT,PLL_LOCK,PLL_RESET,PLL_REFSEL,PLL_SCLK,PLL_SDO,PLL_SDI,PLL_SYNC
Power-Good=+1V0_GTX_PG,+3V3_PLL_PG,+2V5_PLL_PG,+1V2_GTX_PG,+3V3_PG
SPI1=SPI1_MISO,SPI1_MOSI,SPI1_SPCK,SPI1_NPCS0
DOC/SCB_SAM9G45_GK/FPGA_Peripherals_Control.SchDocPreview 0 → 100644
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DOC/SCB_SAM9G45_GK/FPGA_QDRII.Harness 0 → 100644
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qdr2_1_bus=A[18..0],D[35..0],Q[35..0],B\W\S\[3..0],K,K\,CQ,C\Q\,D\O\F\F\,R\P\S\,W\P\S\
qdr2_2_bus=A[18..0],D[35..0],Q[35..0],B\W\S\[3..0],K,K\,CQ,C\Q\,D\O\F\F\,R\P\S\,W\P\S\
DOC/SCB_SAM9G45_GK/FPGA_QDRII.SchDocPreview 0 → 100644
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DOC/SCB_SAM9G45_GK/FPGA_System_Monitor.SchDocPreview 0 → 100644
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DOC/SCB_SAM9G45_GK/Peripherals_Control.Harness 0 → 100644
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DAC_CONTROL=DAC_DMTD_DIN,DAC_DMTD_SYNC,DAC_DMTD_SCLK,DAC_REF_DIN,DAC_REF_SYNC,DAC_REF_SCLK
PLL_CONTROL=PLL_CS,PLL_STAT,PLL_LOCK,PLL_RESET,PLL_REFSEL,PLL_SCLK,PLL_SDO,PLL_SDI,PLL_SYNC,CLK1_SEL
Power-Good=+1V0_GTX_PG,+3V3_PLL_PG,+2V5_PLL_PG,+1V2_GTX_PG,+3V3_PG,+1V2_CPU_PG
SPI1=SPI1_MISO,SPI1_MOSI,SPI1_SPCK,SPI1_NPCS0
DOC/SCB_SAM9G45_GK/Power_Supply.Harness 0 → 100644
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Power-Good=+1V0_GTX_PG,+3V3_PLL_PG,+2V5_PLL_PG,+1V2_GTX_PG,+3V3_PG
DOC/SCB_SAM9G45_GK/Power_Supply.SchDocPreview 0 → 100644
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DOC/SCB_SAM9G45_GK/QDRII_mem.Harness 0 → 100644
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qdr2_1_bus=A[18..0],D[35..0],Q[35..0],B\W\S\[3..0],K,K\,CQ,C\Q\,D\O\F\F\,R\P\S\,W\P\S\
qdr2_2_bus=A[18..0],D[35..0],Q[35..0],B\W\S\[3..0],K,K\,CQ,C\Q\,D\O\F\F\,R\P\S\,W\P\S\
DOC/SCB_SAM9G45_GK/QDRII_mem.SchDocPreview 0 → 100644
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DOC/SCB_SAM9G45_GK/QDRII_power.SchDocPreview 0 → 100644
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DOC/SCB_SAM9G45_GK/RS232_and_USB_ports.Harness 0 → 100644
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CPU_USB=USB_HDP_P,USB_HDP_N,USB_DDP_P,USB_DDP_N
RS232_MNG=RS232_MNG_TXD,RS232_MNG_RXD,RS232_FPGA_TXD,RS232_FPGA_RXD
DOC/SCB_SAM9G45_GK/RS232_and_USB_ports.SchDocPreview 0 → 100644
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DOC/SCB_SAM9G45_GK/SCB.PrjPCB 0 → 100644
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DOC/SCB_SAM9G45_GK/SCB.PrjPCBStructure 0 → 100644
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DOC/SCB_SAM9G45_GK/SCB_CLKs.Harness 0 → 100644
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DAC_CONTROL=DAC_REF_SCLK,DAC_REF_SYNC,DAC_REF_DIN,DAC_DMTD_SCLK,DAC_DMTD_SYNC,DAC_DMTD_DIN
DOC/SCB_SAM9G45_GK/SCB_CLKs.SchDocPreview 0 → 100644
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DOC/SCB_SAM9G45_GK/SCB_MAIN.SchDocPreview 0 → 100644
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DOC/SCB_SAM9G45_GK/SCB_PLLs.Harness 0 → 100644
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MGTREFCLK=MGTREFCLK116_P,MGTREFCLK116_N,MGTREFCLK115_P,MGTREFCLK115_N,MGTREFCLK114_P,MGTREFCLK114_N,MGTREFCLK113_P,MGTREFCLK113_N,MGTREFCLK112_P,MGTREFCLK112_N
PLL_CONTROL=PLL_SYNC,PLL_SDI,PLL_SDO,PLL_SCLK,PLL_REFSEL,PLL_RESET,PLL_LOCK,PLL_STAT,PLL_CS,CLK1_SEL,CLK_EN
QDRII_CLKS=QDRII_CLK_P,QDRII_CLK_N,QDRII_200CLK_P,QDRII_200CLK_N
uTCA_CLK=UTCA_TONGUE2_CLK1_P,UTCA_TONGUE2_CLK1_N,UTCA_TONGUE2_CLK2_P,UTCA_TONGUE2_CLK2_N,MINIBACKPLANE_CLK_P,MINIBACKPLANE_CLK_N
DOC/SCB_SAM9G45_GK/SCB_PLLs.SchDocPreview 0 → 100644
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DOC/SCB_SAM9G45_GK/SCBv3.OutJob 0 → 100644
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DOC/SCB_SAM9G45_GK/SMI_Link_7-12.SchDocPreview 0 → 100644
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DOC/SCB_SAM9G45_GK/uTCA_MCH_PCB3.pcbdoc.htm 0 → 100644
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DOC/SCB_SAM9G45_GK/uTCA_Tongue3.SchDocPreview 0 → 100644
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PCB/PCB_AFC_CPU_COM_EXPRESS/AMC_CPU_COM_EXPRESS.PcbDoc.htm 0 → 100644
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