AMC FMC Carrier AFC issueshttps://ohwr.org/project/afc/issues2023-09-22T17:47:19Zhttps://ohwr.org/project/afc/issues/186Change of location LED32023-09-22T17:47:19ZFilip ŚwitakowskiChange of location LED3Due to assembly issues, LED3 is going to be moved from center of the board to under FMC1 location.
![image](/uploads/eebbd2c19f3a0d474617817b08b9ff45/image.png)AFC v4.0.2https://ohwr.org/project/afc/issues/188AFCv4.0.2 changelog2022-08-04T13:39:23ZFilip ŚwitakowskiAFCv4.0.2 changelogList of changes from v4.0.1 to v4.0.2
* Added MMC JTAG switch - #179
* Added jumper R552 instead of IC22, R441 and R446 marked as umnounted - #184. Additional SW1, D33 and R555 for R&D purpose.
* Added jumpers for Si549 OE signal R449, R474 - #167
* Added RC filter on INA inputs - #167
* Changed R260/R261 to 1K8 - #168
* Renamed MLVDS nets - #180
* Changed IC59 to CERN lib component
* Changed ESD JTAG diodes from PESD3V3S1UB to ESD8351XV2T1G
* Added PU resistors on PROG_TDI and PROG_TMS - DNP by default
* IC11 reset signal swapped from MMC to IC66(expander)
* Added jumpers R542, R550, R553, R554 on FIN1101 inputs.
* Deleted TPD33, DNP: B5, B6, B7, B8 - #187
* Radiator overlay rotated by 90 deg
* Components movement on assembly dept. request: R260, R262, R277, R278, C226, C578, C592, C593, C475, IC13, C313, LED3 and surroundings components - #186
* Enlarged pads on assembly dept. request: J2, L8, C41, C55, C64, L2, L7, FB5, FB6, FB7, FB8
https://ohwr.org/project/afc/issues/185xc2c256 device on AFCv4 JTAG chain2022-01-18T10:38:35ZLucas Maziero Russoxc2c256 device on AFCv4 JTAG chainWhen debugging a design with Vivado chipscope in a AFCv4 via NAT XVC (JSM module) I get the following devices on the JTAG chain:
- xca7a200t: Artix-7 FPGA (ok)
- xc2c256: Xilinx CPLD (?)
Attached are pictures of Vivado hardware manager showing this device.
![vivado_cpld_afcv4](/uploads/a21b7cc6f5cf35c6c175170822d3ca13/vivado_cpld_afcv4.jpg)
![vivado_cpld_afcv4_2](/uploads/5e192c7989c203e66a612f8f92b7d1bf/vivado_cpld_afcv4_2.jpg)
Does anyone know if that was expected?
Thanks!https://ohwr.org/project/afc/issues/167SI549 - OE not connected to SI57X_SEC_OE.2021-08-30T10:46:08ZMarcin KiepielaSI549 - OE not connected to SI57X_SEC_OE.OE of SI549 (pin 1) is not connected to SI57X_SEC_OE signal.
The 0R resistor should be added to make this connection (similarly like in Kasli project).
![image](/uploads/b9b411899e1584d4c596656a0d1ac038/image.png)AFC v4.0.2Filip ŚwitakowskiFilip Świtakowskihttps://ohwr.org/project/afc/issues/193OSC2 and OSC4 misleading schematic2021-08-27T17:41:58ZAugusto Fraga GiacheroOSC2 and OSC4 misleading schematicOSC2 and OSC4 refer to the same component mounted on the PCB, wouldn't be better to delete OSC4 and just change the OSC2 partnumber for each variant?
![afcv4_osc2_osc4](/uploads/ef149bb6fc86218be8d9fbee39016fc3/afcv4_osc2_osc4.png)
![afcv4_osc2_osc4_pcb](/uploads/c8d25c291526bda791ab5a099b28ca7c/afcv4_osc2_osc4_pcb.png)AFC v4.0.2https://ohwr.org/project/afc/issues/195LNLS logo not visible2021-08-27T17:41:44ZAugusto Fraga GiacheroLNLS logo not visibleThe LNLS logo is not visible on the PCB:
![afcv4-lnl-logo](/uploads/81ee78db790a8d55ac2f9f0c89793b41/afcv4-lnl-logo.jpg)
![lnls-logo-afc-invisiblepng](/uploads/4e9d9b9385ef710c83a6336266a3beba/lnls-logo-afc-invisiblepng.png)
Here is a better quality logo imported to Altium already: [logos.PcbDoc](/uploads/cc0b70b9d119765d9e47ba6fa74620ba/logos.PcbDoc)
It is a little larger, placements suggestions bellow:
![lnls-logo-afc-bottom](/uploads/5714d2a708c01a5c13c19dce895e3376/lnls-logo-afc-bottom.png)
![lnls-logo-afc](/uploads/faa006d7227cab0965d34423143ee3b8/lnls-logo-afc.png)AFC v4.0.2https://ohwr.org/project/afc/issues/187Ground test points (TPD33, B6, B5) getting in the way of FMC modules2021-08-19T14:54:13ZAugusto Fraga GiacheroGround test points (TPD33, B6, B5) getting in the way of FMC modulesWhen assembling our FMC modules we had to desolder test points TPD33, B6 and B5 as those were preventing the FMC modules from fitting properly:
![afcv4-gnd-tp-fmc](/uploads/e337d75ff6bbe423b0b676937d80fbde/afcv4-gnd-tp-fmc.png)
We can move the test points to another place or mark those as not mounted by default.AFC v4.0.2https://ohwr.org/project/afc/issues/189DAC_VADJ_RSTn still connected to the LPC1768 GPIO2021-08-18T14:09:35ZAugusto Fraga GiacheroDAC_VADJ_RSTn still connected to the LPC1768 GPIOThe last revision moved the DAC_VADJ_RSTn signal to the IC66 I/O expander but left it still connected to the LPC1768 GPIO:
![afcv4_dac_vadj_bug](/uploads/77bc9bf612f5820870230d2a17b532a1/afcv4_dac_vadj_bug.png)AFC v4.0.2https://ohwr.org/project/afc/issues/191FIN1101 LVDS buffers raising input common voltage to 3V2021-08-18T14:06:10ZAugusto Fraga GiacheroFIN1101 LVDS buffers raising input common voltage to 3VAs discussed through email with Anna, the LVDS buffers IC52 and IC50 are raising the common mode voltage in its inputs to 3V. From my tests a weak biasing resistor voltage divider is enough to overcome this. I suggest adding 10K resistors to bias FMC2_CLK2_BDIR and TCLKA to P3V3_CLKSW / 2.AFC v4.0.2https://ohwr.org/project/afc/issues/194Pulldown on select pin of AMC JTAG mux (IC46)2021-08-18T14:05:53ZKrzysztof MaciasPulldown on select pin of AMC JTAG mux (IC46)Weak pulldown should be connected to select input of SN74CB3T3257PW (IC46) to keep defined state when there is no P3V3.AFC v4.0.2https://ohwr.org/project/afc/issues/192Generate Table of Contents for PDF documentation files2021-08-18T14:03:12ZAugusto Fraga GiacheroGenerate Table of Contents for PDF documentation filesI have noticed that the PDF documents generated for AFCv4 don't have an embedded Table of Contents which makes them hard to navigate through using a PDF viewer. I suggest to enable Table of Contents generation by default into the OutJob file.
![afcv4_table_of_contents](/uploads/f322dd30663b6c8fe8d982c0d74b96f6/afcv4_table_of_contents.png)AFC v4.0.2https://ohwr.org/project/afc/issues/190Connect JTAG pullups to P3V32021-08-18T14:02:49ZKrzysztof MaciasConnect JTAG pullups to P3V3Pull-up resistors on PROG_TDI and PROG_TMS should be connected to P3V3 instead of P3V3MP.AFC v4.0.2https://ohwr.org/project/afc/issues/180Rename MLVDS nets2021-08-18T13:56:35ZMikolaj SowinskiRename MLVDS netshttps://ohwr.org/project/afc/issues/131#note_117049AFC v4.0.2https://ohwr.org/project/afc/issues/184Leaving the USB cable connected prevents MMC from booting2021-08-18T13:56:19ZAugusto Fraga GiacheroLeaving the USB cable connected prevents MMC from bootingFrom #177
Leaving the USB cable connected when powering up the AFC board causes MMC to boot into the serial bootloader. This happens because the RTS line is held '1' (output cmos level, not to be confused with the signal level set by software) when the serial port is unused (closed) and this signal is inverted by IC22 before going to P2.10, causing the MMC micro to enter the bootloader when reseting (my fault).
![screenshot-2021-05-04_11-30-54](/uploads/878d58889dde4aebb2f6c5b21c3a0ed9/screenshot-2021-05-04_11-30-54.png)
To fix it, we should remove IC22, R441 and R446, so P2.10 will be held high when the USB cable is connected but the serial port is closed or when the USB cable is unplugged. Opening the serial port causes DTR and RTS to go to '0' at the same time, C306 should prevent any unwanted reset in this case, but any manual reset while the serial port is open will cause the MMC micro to enter to the bootloader unless you instruct the serial terminal software to set RTS and DTR to '1' again (to '0' from the software perspective).
With the modifications I mentioned, here is a python script for putting the microcontroller into bootloader mode:
```python
#!/usr/bin/env python3
import serial
import time
serport = serial.Serial()
serport.setPort("/dev/ttyUSB3")
serport.open()
# Activate the bootloader
serport.setRTS(1) # set RTS line to 0V
serport.setDTR(0) # set DTR line to 3.3V
time.sleep(0.1)
serport.setDTR(1) # set DTR line to 0V
```AFC v4.0.2https://ohwr.org/project/afc/issues/179MMC JTAG/SWD cable can't be used when P3V3 is off and the AFC is inserted in ...2021-08-18T13:55:59ZAugusto Fraga GiacheroMMC JTAG/SWD cable can't be used when P3V3 is off and the AFC is inserted in the crateWhen P3V3 is off, the IC46 connects the AMC_TDI/TDO/TCK/TMS JTAG signals to MMC_TDI/TDO/TCK/TMS preventing an external debugger from accessing the MMC microcontroller through J9.
![screenshot-2021-05-10_13-44-34](/uploads/702cd2cdafd756d6912c62cc03ec0ef0/screenshot-2021-05-10_13-44-34.png)
To fix it, the IC46 OE signal must be driven ~~low~~ high when P3V3 is off and J9 is connected.AFC v4.0.2https://ohwr.org/project/afc/issues/168R260/R261 inconsistency2021-07-21T15:23:17ZMikolaj SowinskiR260/R261 inconsistency`R260` and `R261` have 1.8k value in comments, however 910R component is selected.
The right value is 1.8k, what allows for 1.8 to 3.3 V VADJ range.AFC v4.0.2https://ohwr.org/project/afc/issues/162Should MMC TRSTn be connected to other TRSTn?2021-07-01T15:17:22ZMikolaj SowinskiShould MMC TRSTn be connected to other TRSTn?*Based on AFCZ review by P. Kulik*
> Currently MMC TRSTn is connected directly to AMC_TRSTn and through diode to FMC1,2 and RTM.
IMO MMC TRSTn shouldn't be connected to FMC and RTM JTAG and should be connected to AMC JTAG only when P3V3 is low (the same condition as in IC12).
https://github.com/elhep/AFCZ/issues/105AFC v4.0.2https://ohwr.org/project/afc/issues/164Add RC filter on INA inputs2021-07-01T14:31:27ZMikolaj SowinskiAdd RC filter on INA inputs*Based on AFCZ review by P. Kulik*
> INA documentation states that "In general, filtering the INA3221 input is only necessary if there are transients at exact harmonics of the 500-kHz (±30%) sampling rate that are greater than 1 MHz."
> Switching frequency of Exar bucks can be adjusted, so filtering these inputs would give us greater flexibility without possible issues with current sensing. We also don't have control over switching frequencies on FMCs and RTM.
https://github.com/elhep/AFCZ/issues/99
We're not using Exar here, however argument of not having control over FMCs and RTM switching frequencies seems convincing to me.AFC v4.0.2https://ohwr.org/project/afc/issues/124Define basic assembly variants2021-06-08T01:02:06ZMikolaj SowinskiDefine basic assembly variantsIt may be beneficial to add some assembly variants to the project. It will also make us sure that the variants we need are feasible.
Please describe desired assembly variants in the comments.AFC v4.0https://ohwr.org/project/afc/issues/131Remove voltage translators for the M-LVDS inputs2021-06-08T00:40:50ZGustavo BrunoRemove voltage translators for the M-LVDS inputsMLVDS circuit could be simplyfied by using the separate receiver/driver signals from the M-LVDS and using different pins for input and output in the FPGA. This would remove the need for bus direction selection, and the FPGA gateware can just ignore the inputs when transmitting in the channel.
In this manner, we could employ the 8-bit SN65MLVD082 (or 080 for Type-1 receiver), allowing for better skew between channels (350ps, before it was 800ps), specially in the reception, as the voltage translation from the 3.3V M-LVDS driver to the 1.5V bank could be done by using only resistors and/or fast diodes.
The output would still need a voltage translator, but this can be unidirectional and do not need to be controlled by the FPGA. NXP 74AVC8T245 has 8 channels and allow for data rates above 200Mbps in this application. To avoid glitching the bus while programming, this translator OE could be set up as proposed in issue #87.
This would also simplify schematics, and the faster transition between receiving and sending could allow for better reuse of the bus for trigger signaling. And this modification would not need demand more pins in the FPGA. The main downside would be the lost of the ability to switch between Type 1 and Type 2 receivers dinamically, as the 8-pin MLVDS options have only one receiver option.AFC v4.0Tomasz PrzywózkiTomasz Przywózki