AMC FMC Carrier AFC issueshttps://ohwr.org/project/afc/issues2021-02-25T12:18:46Zhttps://ohwr.org/project/afc/issues/178AFC v4 Prototype Testing Campaign2021-02-25T12:18:46ZMikolaj SowinskiAFC v4 Prototype Testing CampaignAs manufacturing of the prototypes is in the advanced phase in TechnoSystem and Creotech it is high time to draw a testing campaign. Together with @danielot we've agreed to use OHWR for high-level organization and hardware-related issues.
It is difficult to run the board without MMC, so some aspects of testing will be tightly related to AFCv4 OpenMMC port. It is agreed that @KMacias will make o PR to the [LNLS OpenMMC repo](https://github.com/lnls-dig/openMMC) and a dedicated branch for AFC4 will be created there. All issues related to MMC should be reported to [that repo](https://github.com/lnls-dig/openMMC/issues) (and **not** here).
All involved in testing who wants to contribute to MMC should created their own forks and submit PR to the LNLS repository.
I've created a number of *meta-issues* covering main subsystems of AFC with some ideas of what should be tested. If you find these lists incomplete, please add your positions. It would be great if all involved in testing campaign would report successful results to these meta-issues. For found bugs please create separate issues.
* Power supply #169
* FMC Connectors #170
* MGT Links #171
* DDR Memory #172
* Clocking system #173
* RTM Connector #174
* MLVDS #175
* I2C Subsystem #176
* USB / JTAG #177AFC v4.0https://ohwr.org/project/afc/issues/177[Testing] USB / JTAG2021-07-21T13:32:18ZMikolaj Sowinski[Testing] USB / JTAG- [x] JTAG from USB
- [x] JTAG from AMC
- [x] JTAG from connector
- [x] Primary UART
- [x] Secondary UART
- [x] MMC console
- [x] MMC programming via USB
- [x] JTAG to FMC1
- [x] JTAG to FMC2
- [x] JTAG to RTM
- [x] FPGA JTAGAFC v4.0https://ohwr.org/project/afc/issues/176[Testing] I2C Subsystem2021-03-16T09:36:58ZMikolaj Sowinski[Testing] I2C Subsystem- [x] TCA9548 MMC
- [x] TCA9548 FPGA
- [ ] INA3221 x3
- [x] LM75 x4
- [ ] MAX6642
- [x] 8V54816ANLG
- [x] AT24MAC602
- [ ] AT24C64D
- [x] MCP79410AFC v4.0https://ohwr.org/project/afc/issues/175[Testing] MLVDS2021-02-25T12:18:41ZMikolaj Sowinski[Testing] MLVDSAMC ports 17-20AFC v4.0https://ohwr.org/project/afc/issues/174[Testing] RTM Connector2021-02-25T12:18:41ZMikolaj Sowinski[Testing] RTM Connector* Power supplies
* LVDS lines
* I2C
* RTM PS#
Clocking, I2C, JTAG and MGT links are suggested to be reported in respective issues.AFC v4.0https://ohwr.org/project/afc/issues/173[Testing] Clocking system2021-02-25T12:18:41ZMikolaj Sowinski[Testing] Clocking systemLots of variations here... But let's try do our best:
* TCLKx and FCLK
* FPGA_CLKx
* RTM clocks
* MGT clocks
* FMC clocs
* WR oscillatorsAFC v4.0https://ohwr.org/project/afc/issues/172[Testing] DDR Memory2021-04-13T12:42:18ZMikolaj Sowinski[Testing] DDR MemoryMIG design with data rate of 1866 MT/sAFC v4.0https://ohwr.org/project/afc/issues/171[Testing] MGT Links2021-04-13T12:51:00ZMikolaj Sowinski[Testing] MGT LinksThere are many variants and we should try to test them all. Xilinx IBERT is proffered, whenever possible use 6.6 Gbps line rate.
* AMC P0-P15
* RTM GTP 0-7
* FMC1 DP0-DP3
* FMC2 DP0-DP3AFC v4.0https://ohwr.org/project/afc/issues/170[Testing] FMC Connectors2021-02-25T12:18:41ZMikolaj Sowinski[Testing] FMC Connectors* Power supply
* LA, HA, HB connectivity
* PRSNT_M2C
* PG_C2M
* PG_M2C
* VADJ level negotiation with MMC (was this ever implemented?)
Clocking, I2C, JTAG and MGT links are suggested to be reported in respective issues.AFC v4.0https://ohwr.org/project/afc/issues/169[Testing] Power supply2021-03-18T16:23:55ZMikolaj Sowinski[Testing] Power supply- [x] Verify all voltage levels
- [x] Operation from onboard power connector
- [x] Operation from AMC connector
- [ ] Verify VADJ regulation range
- [ ] Verify INA readoutsAFC v4.0