1. 23 Dec, 2020 1 commit
  2. 14 Dec, 2020 2 commits
  3. 09 Dec, 2020 1 commit
  4. 07 Sep, 2020 1 commit
  5. 27 Aug, 2020 1 commit
  6. 16 Aug, 2020 1 commit
  7. 03 Aug, 2020 1 commit
  8. 07 Jul, 2020 1 commit
    • Aylons's avatar
      Added pinout generator file · 713e937a
      Aylons authored
      THe python script that generates CSV and the ODS file for general pin
      verification and as a design helper were added to the design reports folder.
      713e937a
  9. 06 Jul, 2020 1 commit
  10. 03 Jul, 2020 1 commit
  11. 01 Jul, 2020 1 commit
  12. 30 Jun, 2020 1 commit
  13. 24 Jun, 2020 1 commit
  14. 11 Jun, 2020 1 commit
  15. 10 Jun, 2020 1 commit
  16. 09 Jun, 2020 2 commits
  17. 08 Jun, 2020 1 commit
  18. 02 Jun, 2020 1 commit
  19. 27 May, 2020 1 commit
  20. 03 Jun, 2015 2 commits
  21. 01 Aug, 2014 1 commit
  22. 16 May, 2014 1 commit
  23. 04 Apr, 2014 1 commit
  24. 21 Feb, 2014 2 commits
  25. 10 Feb, 2014 1 commit
  26. 29 Jan, 2014 1 commit
  27. 02 Jan, 2014 1 commit
  28. 01 Jan, 2014 1 commit
    • Greg's avatar
      unified all RC · 9cff1b8a
      Greg authored
      All RC come from CERN library
      Seriously limited BOM
      Almost all issues solved
      PCB - acute angles removed
      improved plane layout- limited cutouts over high speed signals
      added OutJob file
      9cff1b8a
  29. 25 Nov, 2013 1 commit
    • Greg's avatar
      MGT connection upgrade - AMC Ports 12-15 added, · d4185d2a
      Greg authored
      P3V3 aux regulator added in stand-alone mode
      Port0/1 and 2-lane FP2 operation now possible
      quad 116 connected to the clock crossbar
      lot of small bugs fixed according to "issues" list
      d4185d2a
  30. 24 Nov, 2013 1 commit
  31. 05 Nov, 2013 1 commit
  32. 04 Nov, 2013 1 commit
  33. 03 Nov, 2013 1 commit
    • Greg's avatar
      fixed several issues · c165fad1
      Greg authored
      wrong voltage measurement on FMC P12V - before the switch
      Added JTAG support for RTM_CON
      Added RTM power switches and I2C buffer
      moved both USB ports to the front panel
      swapped GTP - FP1 and FP2 to optimize FPGA timings
      cleaned net names in GTP schematic
      c165fad1
  34. 25 Oct, 2013 1 commit
  35. 26 Aug, 2013 1 commit