- 03 Jun, 2015 2 commits
- 01 Aug, 2014 1 commit
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Filip Świtakowski authored
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- 16 May, 2014 1 commit
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Greg authored
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- 04 Apr, 2014 1 commit
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Greg authored
Added OHL license on the schematics updated mounted/not mounted designators.
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- 21 Feb, 2014 2 commits
- 10 Feb, 2014 1 commit
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Greg authored
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- 29 Jan, 2014 1 commit
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Greg authored
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- 02 Jan, 2014 1 commit
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Greg authored
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- 01 Jan, 2014 1 commit
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Greg authored
All RC come from CERN library Seriously limited BOM Almost all issues solved PCB - acute angles removed improved plane layout- limited cutouts over high speed signals added OutJob file
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- 25 Nov, 2013 1 commit
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Greg authored
P3V3 aux regulator added in stand-alone mode Port0/1 and 2-lane FP2 operation now possible quad 116 connected to the clock crossbar lot of small bugs fixed according to "issues" list
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- 24 Nov, 2013 1 commit
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Greg authored
inverted all HPC lines
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- 05 Nov, 2013 1 commit
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Greg authored
detected swapped RTM connectors - some work need to be done on layout version without polygons to reduce PCB size and to make checking easier
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- 04 Nov, 2013 1 commit
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Greg authored
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- 03 Nov, 2013 1 commit
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Greg authored
wrong voltage measurement on FMC P12V - before the switch Added JTAG support for RTM_CON Added RTM power switches and I2C buffer moved both USB ports to the front panel swapped GTP - FP1 and FP2 to optimize FPGA timings cleaned net names in GTP schematic
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- 25 Oct, 2013 1 commit
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Greg authored
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- 26 Aug, 2013 1 commit
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Greg authored
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