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AMC FMC Carrier AFC
Commit be53d378 authored by Greg's avatar Greg
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added low jitter clock bypass - implemented on PCB

parent 7ee20a81
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Showing with 19 additions and 32 deletions
PCB_uTCA_FMC_Carrier v3/AMC_FMC_Carrier v3.PrjPcb
View file @ be53d378
......@@ -2,6 +2,8 @@
Version=1.0
HierarchyMode=2
ChannelRoomNamingStyle=0
OutputPath=
LogFolderPath=
ReleasesFolder=
ReleaseVaultGUID=
ReleaseVaultName=
......@@ -28,12 +30,6 @@ PowerPortNamesTakePriority=1
PushECOToAnnotationFile=1
DItemRevisionGUID=
ReportSuppressedErrorsInMessages=0
OutputPath=
LogFolderPath=
[Preferences]
PrefsVaultGUID=
PrefsRevisionGUID=
[Document1]
DocumentPath=AMC_Connector.SchDoc
......@@ -908,6 +904,10 @@ DocumentPath=Project Outputs for AMC_FMC_Carrier v3\AMC_FMC_Carrier.CSV
DItemRevisionGUID=
[GeneratedDocument3]
DocumentPath=AMC_FMC_Carrier_35u_tears.PcbDoc.htm
DItemRevisionGUID=
[GeneratedDocument4]
DocumentPath=Project Outputs for AMC_FMC_Carrier v3\Design Rule Check - AMC_FMC_Carrier_35u_tears.html
DItemRevisionGUID=
......@@ -915,11 +915,13 @@ DItemRevisionGUID=
Name=Default Configuration
ParameterCount=0
ConstraintFileCount=0
[PCBConfiguration1]
ReleaseItemId=
CurrentRevision=
Name=Default Configuration
Variant=[No Variations]
GenerateBOM=0
OutputJobsCount=0
[Generic_SmartPDF]
AutoOpenFile=0
......@@ -1091,12 +1093,12 @@ OutputName1=Mixed Sim
OutputDocumentPath1=
OutputVariantName1=
OutputDefault1=0
OutputType2=SIMetrixSimulation
OutputType2=SIMetrix_Sim
OutputName2=SIMetrix
OutputDocumentPath2=
OutputVariantName2=
OutputDefault2=0
OutputType3=SIMPLISSimulation
OutputType3=SIMPLIS_Sim
OutputName3=SIMPLIS
OutputDocumentPath3=
OutputVariantName3=
......@@ -1209,6 +1211,12 @@ OutputDocumentPath17=
OutputVariantName17=
OutputDefault17=0
PageOptions17=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4|PrintScaleMode=1
OutputType18=Logic Analyser Print
OutputName18=Logic Analyser Prints
OutputDocumentPath18=
OutputVariantName18=
OutputDefault18=0
PageOptions18=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4|PrintScaleMode=1
[OutputGroup4]
Name=Assembly Outputs
......@@ -1295,12 +1303,6 @@ OutputVariantName9=[No Variations]
OutputDefault9=0
Configuration9_Name1=OutputConfigurationParameter1
Configuration9_Item1=AddToAllPlots.Set=SerializeLayerHash.Version~2,ClassName~TLayerToBoolean|CentrePlots=False|DrillDrawingSymbol=GraphicsSymbol|DrillDrawingSymbolSize=500000|EmbeddedApertures=True|FilmBorderSize=10000000|FilmXSize=1181102362|FilmYSize=1181102362|FlashAllFills=False|FlashPadShapes=True|G54OnApertureChange=False|GenerateDRCRulesFile=True|GenerateReliefShapes=True|GerberUnit=Metric|IncludeUnconnectedMidLayerPads=False|LeadingAndTrailingZeroesMode=SuppressLeadingZeroes|MaxApertureSize=2500000|MinusApertureTolerance=39|Mirror.Set=SerializeLayerHash.Version~2,ClassName~TLayerToBoolean|MirrorDrillDrawingPlots=False|MirrorDrillGuidePlots=False|NumberOfDecimals=4|OptimizeChangeLocationCommands=True|OriginPosition=Relative|Panelize=False|Plot.Set=SerializeLayerHash.Version~2,ClassName~TLayerToBoolean,16973830~1,16973832~1,16973834~1,16777217~1,16842751~1,16973835~1,16973833~1,16973831~1|PlotPositivePlaneLayers=False|PlotUsedDrillDrawingLayerPairs=True|PlotUsedDrillGuideLayerPairs=True|PlusApertureTolerance=39|Record=GerberView|SoftwareArcs=False|Sorted=False
OutputType10=Board Stack Report
OutputName10=Report Board Stack
OutputDocumentPath10=
OutputVariantName10=
OutputDefault10=0
PageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4|PrintScaleMode=1
[OutputGroup6]
Name=Report Outputs
......@@ -1563,11 +1565,6 @@ OutputName4=Footprint Comparison Report
OutputDocumentPath4=
OutputVariantName4=
OutputDefault4=0
OutputType5=Configuration compliance
OutputName5=Environment configuration compliance check
OutputDocumentPath5=
OutputVariantName5=
OutputDefault5=0
[OutputGroup9]
Name=Export Outputs
......@@ -1670,10 +1667,6 @@ Type71=1
Type72=1
Type73=1
Type74=1
Type75=1
Type76=1
Type77=1
Type78=1
[Difference Levels]
Type1=1
......@@ -1716,9 +1709,6 @@ Type37=1
Type38=1
Type39=1
Type40=1
Type41=1
Type42=1
Type43=1
[Electrical Rules Check]
Type1=1
......@@ -1821,7 +1811,6 @@ Type97=2
Type98=0
Type99=1
Type100=2
Type101=1
[ERC Connection Matrix]
L1=NNNNNNNNNNNWNNNWW
......@@ -1844,14 +1833,12 @@ L17=WNNNNNNNWNNNWWWWN
[Annotate]
SortOrder=3
SortLocation=0
MatchParameter1=Comment
MatchStrictly1=1
MatchParameter2=Library Reference
MatchStrictly2=1
PhysicalNamingFormat=$Component_$RoomName
GlobalIndexSortOrder=3
GlobalIndexSortLocation=0
[PrjClassGen]
CompClassManualEnabled=0
......
PCB_uTCA_FMC_Carrier v3/Clock_management.Harness
View file @ be53d378
AMC_FABRIC_CLOCK=FCLKA_N,FCLKA_P
AMC_TELECOM_CLOCK=TCLKA_N,TCLKA_P,TCLKB_N,TCLKB_P,TCLKC_N,TCLKC_P,TCLKD_N,TCLKD_P
CLK_DIFF=CLK_N,CLK_P
FPGA_SDRAM_CLK=SDRAM_CLK1_N,SDRAM_CLK1_P,BOOT_CLK_IN
FPGA_SDRAM_CLK=FPGA_CLK1_N,FPGA_CLK1_P,BOOT_CLK_IN
I2C=SDA,SCL
MGT_CLK=PCIE_CLK1_P,PCIE_CLK1_N,FP2_CLK1_P,FP2_CLK1_N,FP2_CLK2_P,FP2_CLK2_N,LINK01_CLK_P,LINK01_CLK_N,LINK23_CLK_P,LINK23_CLK_N
PLL_CTRL=VADJ2_SI57X_SDA,VADJ2_SI57X_SCL,PLL_VADJ2_DAC2_SYNC_N,PLL_VADJ2_DAC_SCLK,PLL_VADJ2_DAC1_SYNC_N,PLL_VADJ2_DAC_DIN,VADJ2_SI57X_OE,VADJ2_SI57X_TUNE,VADJ2_CLK_UPDATEN
PCB_uTCA_FMC_Carrier v3/FPGA_SDRAM.Harness
View file @ be53d378
DDR=DQS0_P,DQS0_N,DQS1_P,DQS1_N,DQS2_P,DQS2_N,DQS3_P,DQS3_N,CLK0_N,CLK0_P,RST_N,ODT0,CE0_N,BA0,BA1,BA2,A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11,A12,A13,A14,A15,CAS_N,RAS_N,WE_N,CKE0,DQM0,D0,D1,D2,D3,D4,D5,D6,D7,DQM1,D8,D9,D10,D11,D12,D13,D14,D15,DQM2,D16,D17,D18,D19,D20,D21,D22,D23,DQM3,D24,D25,D26,D27,D28,D29,D30,D31
FPGA_SDRAM_CLK=SDRAM_CLK1_N,SDRAM_CLK1_P,BOOT_CLK_IN,SDRAM_CLK2_N
FPGA_SDRAM_CLK=FPGA_CLK1_N,FPGA_CLK1_P,BOOT_CLK_IN,SDRAM_CLK2_N
MLVDS-FPGA=IO_TX_P17,IO_TX_P18,IO_TX_P19,IO_TX_P20,IO_RX_P17,IO_RX_P18,IO_RX_P19,IO_RX_P20,R\E\_DE_TX_P17,R\E\_DE_TX_P18,R\E\_DE_TX_P19,R\E\_DE_TX_P20,R\E\_DE_RX_P17,R\E\_DE_RX_P18,R\E\_DE_RX_P19,R\E\_DE_RX_P20
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